GB2258564A - Insulated gate bipolar transistor - Google Patents
Insulated gate bipolar transistor Download PDFInfo
- Publication number
- GB2258564A GB2258564A GB9216139A GB9216139A GB2258564A GB 2258564 A GB2258564 A GB 2258564A GB 9216139 A GB9216139 A GB 9216139A GB 9216139 A GB9216139 A GB 9216139A GB 2258564 A GB2258564 A GB 2258564A
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- GB
- United Kingdom
- Prior art keywords
- semiconductor layer
- semiconductor
- layer
- conductivity type
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 claims description 49
- 239000012535 impurity Substances 0.000 claims description 29
- 239000000758 substrate Substances 0.000 claims description 25
- 238000011282 treatment Methods 0.000 claims description 11
- 238000002347 injection Methods 0.000 claims description 5
- 239000007924 injection Substances 0.000 claims description 5
- 238000000034 method Methods 0.000 claims description 4
- 238000009413 insulation Methods 0.000 claims 2
- 239000010410 layer Substances 0.000 description 51
- 238000009792 diffusion process Methods 0.000 description 5
- 230000001965 increasing effect Effects 0.000 description 4
- 238000010894 electron beam technology Methods 0.000 description 3
- 230000005855 radiation Effects 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 238000005215 recombination Methods 0.000 description 2
- 230000006798 recombination Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000002344 surface layer Substances 0.000 description 2
- 230000001419 dependent effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/083—Anode or cathode regions of thyristors or gated bipolar-mode devices
- H01L29/0834—Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thyristors (AREA)
- Bipolar Transistors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
INSULATED GATE BIPOLAR TRANSISTOR 1 1 22SdSt')4
BACKGROUND OF THE INVENTION Field of the Invention
The present invention relates to an insulated gate bipolar transistor (hereinafter abbreviated to "WBV') for use as a power switching device. Discussion of the Related Art Using IGBTs as power switching devices has become popular in recent years. In a power switching IGBT, a reverse conductivity type layer is added to a vertical MOSFET drain region an the drain electrode side. one example of such a cell is shown in Fig. 2. A high-resistance n_ layer 3 is formed on a p + layer 1 through a low-resistance n + layer 2. A p + region 4 is in a surface layer of the n_ layer 3, and an n + region 5 is in a surface layer of the p + region 4. The regions 4 and 5 are selectively formed by, for example, ion diffusion.
A surface portion of the p + region 4, interposed between the n_ layer 3 and the n + region 5, is used as a channel region. A gate electrode 7 connected to a gate terminal G is over the channel region with a gate insulating film 6 between the channel region and the gate electrode 7. A source electrode 8 is insulated from the gate electrode 7 by an insulating film 10, and is connected to a source terminal S. The source electrode 8 is in contact with respective surfaces of the p + region 4 and the n + region 5. A drain electrode 9 is connected to a drain terminal D, and is in contact with a surface of the p + layer 1.
When positive voltages are respectively applied to the gate terminal G and the drain terminal D and the source terminal S is grounded, the MOSFET defined by the n + layer 2, the n_ layer 3, the p + region 4, the n + region 5, the gate electrode 7 and the source electrode 8 is turned on, and electrons flow into the n_ layer through the channel region. Hole injection from the p + substrate 1 into the n_ layer 3 through the n + layer 2 occurs corresponding to the flow of electrons, so that conductivity modulation occurs in the n_ layer 3. As a result, the resistance in this region becomes low, so that a low on-resistance becomes conductive.
In such a conventional IGBT, the rate of recombination between electrons and holes in the n_ layer 3 is low, when the onstate voltage becomes small. This produces undesirably long switching times. To solve this problem, the carrier lifetimes can be shortened by carrier lifetime control treatments such as electron beam radiation or gold diffusion into silicon material for the purpose of increasing the rate of recombination between electrons and holes. However, the on-state voltages become large when those lifetime shortening methods are carried out in practice. That is, the relationship between the on-state voltage and switching time is a trade-off, so that it is very difficult to improve the two characteristics simultaneously.
SUMMARY OF THE INVENTION
An object of the present invention is to provide an IGBT in which the switching time can be improved without increasing the on-state voltage, thus overcoming the trade-off relationship.
Additional objects and advantages of the invention will be set forth in part in the description which follows and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
In order to attain the foregoing objects, according to the present invention, a semiconductor substrate is provided for an insulated gate bipolar transistor having a short switching time and a low on state voltage. The substrate comprises a first semiconductor layer having a first conductivity type and an ion impurity concentration from 1.0 x 10 16 cm- 3 to 1.0 X 10 17 cm- 3; a second semiconductor layer having a second conductivity type on the first semiconductor layer, the ion impurity concentration of the second semiconductor layer being lower than the ion impurity concentration of the first semiconductor layer; and a third semiconductor layer having the second conductivity type on the second semiconductor layer, the ion impurity concentration of the third semiconductor layer being lower than the ion impurity concentration of the first semiconductor layer; wherein the substrate is not subject to a carrier lifetime control treatment.
BRIEF DESCRIPTION OF THE DRAWINGS
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings,
Figure 1 is a graph showing the relationship between the onstate voltagelturn-off time and the impurity density of the p + substrate in the case of an IGBT with a rating of 60OV/100A; Figure 2 is a sectional view of the IGBT according to the present invention; Figure 3 is a graph showing the relationship between the on- state voltage/turn-off time and the impurity density of the p + substrate in the case of an IGBT with a rating of 120OV/50A; and Figure 4 is a graph showing the relations between the onstate voltage/turn-off time of the IGBT and the presence/absence of lifetime control treatment.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
Embodiments of the present invention, inclusive of the fundamental data therefore, will be described hereunder with reference to the drawings.
In the preferred embodiment of the present invention, a three layer semiconductor structure is provided in which an IGBT is formed. The first layer has the opposite conductivity type as the second and third layers, and the first layer has a higher impurity concentration than the second and third layers. The doping ion impurity concentration of the first layer is from 1.0 x 10 16 cm- 3 4 to 1.0 X 10 17 cm-3, inclusive. Carrier lifetime control treatments are not performed on the three layer structure.
If the impurity density of the first layer is less than 1.0 x 10 17 cm- 3 and the impurity density of the second layer is less than that of the first layer, the carrier (electrons and holes) density distribution of the second and third layers becomes flat. As a result, diffused current components caused to flow by the gradient of the carrier density at turnoff time can be suppressed. Accordingly, the turn-off time can be shortened without increasing the on-state voltage by setting the lower limit of the density of the first layer to 1.0 x 10 16 cm-3 as a value before the increase of the on-state voltage.
An IGBT shown in Fig. 2 was produced by the following steps. First, silicon substrates of various impurity densities where used as a p + layer 1 (the first layer). An n + buffer layer (the second layer) 2 and an nbuffer layer (the third layer) 3 were laminated on a surface of the p + substrate 1 by an epitaxial growing method. The layer 2 and the layer 3 were lower in doping impurity density than the p + substrate 1.
Then, polycrystalline silicon was deposited, through an oxide film, on a surface of the layer 3. A gate electrode 7 and a gate oxide film 6 were formed from the polycrystalline silicon and the oxide film by photolithography.
Using the gate electrode 7 as a mask, acceptor ion injection was carried out. At the same time, a p + layer 4 (the first region) was formed by heat diffusion. Then, using the gate electron 7 as a part of a mask, an n + layer 5 (the second region) was formed by donor ion injection and heat diffusion. Thereafter, a source electrode 8 was brought into contact with the p + and n + layers 4 and 5 through an insulating film 10, and a drain electrode 9 was brought into contact with the p + substrate 1, so that the IGBT was finished.
The IGBT was not subjected to a carrier lifetime control treatment such as lifetime killer injection or electron beam radiation. The cell shown in the drawing has a 20pm, width. A large number of such cells were formed in one silicon body.
Fig. 1 is a graph showing the relationship between the onstate voltage (on the left vertical axis) and the turn-off time (on the right vertical axis) vs. the impurity density of the p + substrate 1 in an IGBT with a rating of 60OV/100A (on the horizontal axis). The on-state voltage points are shown as circles, while the turn-off time points are shown as triangles.
In the example shown in Fig. 1, the n_ layer 3 had a thickness of 14 -3 about 50pm and an impurity density of 1.0.x 10 cm. As shown in the graph, the on-state voltage increases rapidly when the density of the p + substrate 1 is less than 10 x 10 16 cm- 3, and the turn-off time increases rapidly when the density is more then 1.0 17 -3 X 10 cm The terminology 'Ion-state voltage" means the voltage between the source terminal S and the drain terminal D, necessary for passing the rated current, for example, 100 A. The terminology "turn-off time" means the time required to reduce the introduction current from 90% to 10% of the stationary on-state under inductive load connection.
Fig. 3 shows the dependency of the on-state voltage (on the left vertical axis) and turn-off time (on the right vertical axis) on the impurity density of the p + substrate (horizontal axis) in the case of an IGBT device with a rating of 120OV/50A. In this - layer 3 had density of 10 x 10 14 cm- 3 example, the n an impuri and a thickness of about 100pm. The on-state voltage points are shown as circles, while the turn-off time points are shown as triangles. Like Fig. 1, Fig. 3 shows that both the on-state voltage and turn-off time are not deteriorated when the impurity density of the p + substrate 1 is in a range of from 1.0 x 10 16 cm- 3 17 - 3 to 1.0 X 10 cm Fig. 4 shows the respective changes of the on-state voltage (left vertical axis) and turn-off time (right vertical axis) dependent on the presence or absence of lifetime control treatment (horizontal axis). in this example, the IGBT had a rating of 60OV/100A and a p + substrate 1 with an impurity density of 1.0 x 1017 cm- 3. As shown in the graph in Fig. 4, the device subjected to lifetime control treatment, such as electron beam radiation, gold diffusion, or the like, has the turn-off time shortened slightly but the on-state voltage increased greatly.
As can be seen from the above description, an IGBT having the shortened turn-off time without increase of the on-state voltage can be produced by limiting the range of the impurity density of the p+ layer under the n+ buffer layer without carrying out any lifetime control treatment. Because there is no lifetime control treatment required, the effect thus obtained is very large.
7 - The foregoing description of preferred embodiments of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and obviously many modifications and variations are possible in light of the above teachings or may be acquired from practice of the invention. The embodiments were chosen and described in order to best explain the principles of the invention and its practical application to thereby enable one skilled in the art to best utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims appended hereto.
Claims (10)
1. A semiconductor substrate for an insulated gate bipolar transistor having a short switching time and a low on state voltage, the substrate comprising:
a first semiconductor layer having a first conductivity type and an ion impurity concentration from 1.0 x 10 16 cm- 3 to 1.0 X 17 - 3. 10 cm J a second semiconductor layer having a second conductivity type on the first semiconductor layer, the ion impurity concentration of the second semiconductor layer being lower than the ion impurity concentration of the first semiconductor layer; and a third semiconductor layer having the second conductivity type on the second semiconductor layer, the ion impurity concentration of the third semiconductor layer being lower than the ion impurity concentration of the first semiconductor layer; wherein the substrate is not subject to a carrier lifetime control treatment.
2. A semiconductor substrate as claimed in claim 1, wherein the first conductivity type is p type.
3. A semiconductor substrate as claimed in claim 2, wherein the second conductivity type is n type.
4. A semiconductor substrate as claimed in claim 3, wherein the second and third semiconductor layers are laminated by an epitaxial growing method 'to the first semiconductor layer.
5. An insulated gate bipolar transistor having a short switching time and a low on state voltage, comprising: a semiconductor substrate comprising: a first semiconductor layer having a first conductivity type and an ion impurity concentration from 1.0 x 10 16 cm-3 to 1.0 X 10 17 cm- 3; a second semiconductor layer having a second conductivity type on the first semiconductor layer, the ion impurity concentration of the second semiconductor layer being lower than the ion impurity concentration of the first semiconductor layer; and a third semiconductor layer having the second conductivity type on the second semiconductor layer, the ion impurity concentration of the third semiconductor layer being lower than the ion impurity concentration of the first semiconductor layer; wherein the substrate is not subject to a carrier lifetime control treatment; a first semiconductor region having the first conductivity type in the third semiconductor layer of the substrate; a second semiconductor region having the second conductivity type in the first semiconductor region; a gate insulation film on a portion of the first semiconductor region and on a portion of the second semiconductor region; and a gate electrode on the gate insulation film.
- 10
6. An insulated gate bipolar transistor as claimed in claim 5, further comprising a drain electrode on the first layer of the semiconductor substrate, and a source electrode on a portion of the first semiconductor region and a portion of the second semiconductor region.
7. An insulated gate bipolar transistor as claimed in claim 6, wherein the first conductivity type is p type.
8. An insulated gate bipolar transistor as claimed in claim 7, wherein the second conductivity type is n type.
9. An insulated gate bipolar transistor as claimed in claim 8, wherein the second and third semiconductor layers are laminated by an epitaxial growing method to the first semiconductor layer.
10. An insulated gate bipolar transistor as claimed in claim 9, wherein the first semiconductor region and the second semiconductor region are formed by ion injection using the gate electrode as a mask.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3195592A JPH0541524A (en) | 1991-08-06 | 1991-08-06 | Insulated-gate bipolar transistor |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB9216139D0 GB9216139D0 (en) | 1992-09-09 |
| GB2258564A true GB2258564A (en) | 1993-02-10 |
| GB2258564B GB2258564B (en) | 1994-12-21 |
Family
ID=16343715
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB9216139A Expired - Fee Related GB2258564B (en) | 1991-08-06 | 1992-07-29 | Insulated gate bipolar transistor |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JPH0541524A (en) |
| DE (1) | DE4225738A1 (en) |
| GB (1) | GB2258564B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0780905A1 (en) * | 1995-12-19 | 1997-06-25 | Kabushiki Kaisha Toshiba | Isolated gate bipolar transistor |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010010401A (en) * | 2008-06-27 | 2010-01-14 | Hitachi Ltd | Horizontal igbt and motor controller using the same |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2150753A (en) * | 1983-11-30 | 1985-07-03 | Toshiba Kk | Semiconductor device |
| EP0327316A2 (en) * | 1988-02-04 | 1989-08-09 | Kabushiki Kaisha Toshiba | Semiconductor device having composite substrate formed by fixing two semiconductor substrates in close contact with each other |
| EP0365107A2 (en) * | 1988-10-19 | 1990-04-25 | Kabushiki Kaisha Toshiba | Manufacturing method for vertically conductive semiconductor devices |
| US4990975A (en) * | 1988-12-16 | 1991-02-05 | Mitsubishi Denki Kabushiki Kaisha | Insulated gate bipolar transistor and method of manufacturing the same |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE4114349C2 (en) * | 1990-05-10 | 2001-05-31 | Fuji Electric Co Ltd | Insulated Gate Bipolar Transistor (IGBT) |
-
1991
- 1991-08-06 JP JP3195592A patent/JPH0541524A/en active Pending
-
1992
- 1992-07-29 GB GB9216139A patent/GB2258564B/en not_active Expired - Fee Related
- 1992-08-04 DE DE19924225738 patent/DE4225738A1/en not_active Withdrawn
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2150753A (en) * | 1983-11-30 | 1985-07-03 | Toshiba Kk | Semiconductor device |
| EP0327316A2 (en) * | 1988-02-04 | 1989-08-09 | Kabushiki Kaisha Toshiba | Semiconductor device having composite substrate formed by fixing two semiconductor substrates in close contact with each other |
| EP0365107A2 (en) * | 1988-10-19 | 1990-04-25 | Kabushiki Kaisha Toshiba | Manufacturing method for vertically conductive semiconductor devices |
| US4990975A (en) * | 1988-12-16 | 1991-02-05 | Mitsubishi Denki Kabushiki Kaisha | Insulated gate bipolar transistor and method of manufacturing the same |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0780905A1 (en) * | 1995-12-19 | 1997-06-25 | Kabushiki Kaisha Toshiba | Isolated gate bipolar transistor |
| US5952682A (en) * | 1995-12-19 | 1999-09-14 | Kabushiki Kaisha Toshiba | Semiconductor device with deep anode and lifetime reduction region |
| CN1084932C (en) * | 1995-12-19 | 2002-05-15 | 东芝株式会社 | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| GB2258564B (en) | 1994-12-21 |
| DE4225738A1 (en) | 1993-02-18 |
| GB9216139D0 (en) | 1992-09-09 |
| JPH0541524A (en) | 1993-02-19 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 20030729 |