GB2257587A - A phase detector and a phase locked loop - Google Patents

Abstract

A phase detecting circuit and a phase locked loop are described. In the phase detector circuit equal magnitude positive and negative currents are applied to a capacitor (305) under the control of signals from a gating circuit (303) responsive to the relative timing of transitions derived from a local oscillator (12) to pulses of fixed duration derived from external sync pulses. Inhibit pulses centred on the transitions and of slightly shorter duration than the fixed duration are applied to block the output signals of the gating circuit. <IMAGE>

Description

A PHASE DETECTOR AND A PHASE LOCKED LOOP The present invention relates to a pulse detector and to a phase locked loop including the phase detector.

It is an object of the present invention to provide an improved phase detector and an improved phase locked loop.

According to an aspect of the invention there is provided a phase detector circuit for producing an output voltage indicative of the phase relationship between a first signal and a second signal, the first signal including a transition from a first logic state to a second logic state and the second signal including a pulse of particular duration, the circuit including gating means having inputs for the first and second signals and producing pairs of output signals of complementary durations representing the time of occurrence of the transition of the first signal relative to the middle of the pulse of the second signal, current source means responsive to each pair of output signals of the gating means to provide positive and negative currents of equal magnitude for the respective durations of the output signals of the particular pair, and capacitor means connected to receive the currents from the current source means and produce therefrom the output voltage, wherein means is provided for restricting the total of the durations of a pair of output signals from the gating means to being substantially less than the duration of a pulse of the second signal.

The gating means may have an input for an inhibit signal symmetrical about the transition of the first signal and of shorter duration than the pulse of the second signal which is applied to the gating means, the inhibit signal serving to reduce the duration of the pair of output signals from the gating means.

An example of a phase detecting circuit and of a phase locked loop in accordance with the invention will now be described with reference to the accompanying drawings, of which: FIGURE 1 is a block diagram of a phase locked loop; FIGURE 2 is a block diagram of a phase locked loop using a particular form of phase detector; FIGURE 3 shows waveforms to be used to explain the operation of the phase detector used in Figure 5; FIGURE 4 is the circuit diagram of the digital logic of the phase detector used in Figure 5; FIGURE 5 is the circuit diagram of current sources used in conjunction with the digital logic of Figure 7 in the phase detector used in Figure 5.

The clocked computer described herein is suitable for use in the digital signal processor that is described in the copending Application No. 88.22114.8, Publication No.

2 225 198, entitled Improvements in or relating to Digital Signal Processors", proprietor Texas Instruments Limited, from which this application was divided. An example of that digital signal processor takes a video signal containing teletext data and provides the teletext data on its own.

In that digital signal processor the phase locked loop is used to stabilise a voltage controlled oscillator with respect to sync pulses supplied to it derived by a sync separator, from the video signal. The particular example of the phase locked loop described below is that found in an example of the digital signal processor. However, it is to be understood that the phase locked loop described herein is not limited in its usefulness to that application.

Referring now to Figure 1, the separated synchronising signals 16, having a frequency of 15,625 Hz are applied to a phase locked loop 11 to control the frequency of a 22 MHz oscillation 17 generated by a voltage controlled oscillator 12. The 22 MHz oscillation 17 from the oscillator 12 is applied to a frequency divider 13 where it is divided by 1408 to produce an output of 15,625 Hz which is applied to a phase detector 14. The output of the phase detector 14 is applied via a filter 15 to control the frequency of oscillation 17 of the voltage controlled oscillator 12.

The oscillation 17 from the oscillator 12 is then available for use by other circuits and in the digital signal processor mentioned above it is applied to a video display system.

The phase locked loop 11 shown in Figure 1 is redrawn in Figure 2 where the phase detector 14 is shown as comprising a line sync logic unit 301, a decoder 302, a phase detector logic unit 303 and precision matched current sources 304. The loop filter 15 of Figure 1 comprises a capacitor 305 to which the current produced by one of the sources 304 is applied and from which the current drawn by the other of the sources 304 is taken. The capacitor 305 may be in two parts connected by a resistor.

In Figure 2 line sync pulses from the sync separator are applied to the unit 301 together with timing information from the counter 13 received via the decoder 302. The incoming line sync pulses have a duration of 4.7 microseconds as shown inverted at (b) in Figure 3 and the unit 301 produces from those pulses short line pulses starting with the leading edges of the incoming pulses and having a duration of approximately 1.8 microseconds as shown at (c) in Figure 3.

The decoder responds to the outputs of the counter 13 to produce a reference signal int he form of a square wave having a transition from 0 to 1 as shown at (a) in Figure 3. The phase locked loop operates to adjust the frequency and phase of the voltage controlled oscillator 12 so that each transition occurs in the middle of each short line pulse.Although it would be possible to use the transition to divide the short line pulse into two parts and use the parts to apply currents of the same magnitude and opposite polarity respectively for the durations of the parts to the capacitor 305 to produce a control voltage for the V.C.O. 12, the decoder 302 is caused to produce an inhibit pulse (d) of Figure 3 of duration 1.6 microseconds centred on the transition, which pulse is used by the unit 303 to reduce the durations for which the currents are applied to the capacitor 305. When the V.C.O. 12 is oscillating at the correct frequency and phase the positive and negative currents are applied to the capacitor 305 for periods of duration 100 nanoseconds only as indicated by (e) and (f) in Figure 3.

The line sync logic 301 also determines the duration of the short line pulses.

An advantage which is obtained from shortening the time periods for which currents are applied to the capacitor 305 is that errors in the phase of the oscillation produced by the V.C.O. 12 that would arise if the positive and negative currents applied to the capacitor 305 were not equal in magnitude are reduced in proportion to the reduction in the time periods. Although the currents to be applied to the capacitor 305 would be smaller if they were to be applied for longer time periods, and therefore the absolute difference in magnitude between the currents could be made smaller, the phase error resulting would still be that proportion of the longer time period.

Figure 4 shows in more detail the phase locked loop shown in Figure 2. In Figure 4 the 22 MHz oscillation from the V.C.O. 12 is applied to the counter and and decoder 13, 302, which produces three outputs on conductors 320, 321 and 322 respectively. The reference signal, that is a square wave to give the advantage of noise averaging, has a transition from 0 to 1 repeated at line frequency 15625 Hz, appears on the conductor 320. The inhibit signals each of duration 1.6 microseconds symmetrically disposed about the reference signal appear on the conductor 321. The inhibit signals are also produced in the middle of each line period so that they overlap the half-line equalising pulses during the field blanking period, so as to block the response of the phase detector to the equalising pulses. An 11 MHz oscillation appears on the conductor 322.

The conductor 322 is connected through two inverters 323 and 324 in series to an input of NAND-gate 325. The output of the gate 325 is connected to the clock input of the first D-type trigger of a five stage binary counter 326 composed of D-type triggers. The Q outputs of the first, second and fifth stages of the counter 326 are connected to the inputs of a NAND-gate 327, of which the outputs is applied to the second input of the NAND-gate 325.

Incoming sync pulses from the sync separator at line frequency 15625, are fed by a conductor 328 to the digit input of a D-type trigger 329, of which the clock input is connected to the output of the inverter 324.

The Q output of the trigger 329 is connected through an AND-gate 330 to resetting inputs of the five stages of the counter 326. The conductor 328 is als, connected through an inverter 331 to an input of an AND-gate 332.

The clock inputs of D-type triggers 333 and 334 are connected to the output of the inverter 323 and respectively receive on their digit inputs the output of the gate 327 and the input pulses on conductor 311. The Q output of the trigger 333 and the Q output of the trigger 334 are applied to the AND-gate 332.

A resetting signal RESET is applied via a conductor 335 to the resetting inputs of the triggers 329, 333 and 334, and to the second input of the AND-gate 330. This signal is used only during testing and takes no part in the normal operation of the circuit. It will not be referred to in the following description.

AND-gates 336, 337 and 339 each have an input connected to the output of the gate 332. A signal LREF is applied via a conductor 341 to inputs of the gates 337 and 339. A signal LREF is applied via conductor 342 to inputs of the gates 336 and 338. A signal LLOCK is applied via a conductor 343 to inputs of the gates 336 and 337. A signal LLOCK applied via a conductor 344 to inputs of the gates 338 and 339.

A signal GOOD is applied via a conductor 345 to an input of the gate 332 and to an input of an AND-gate 340, the other input of which is connected to the conductor 343 to receive the signal LLOCK.

The gates 336, 337, 338, 339 and 340 respectively produce as outputs the signals UF (up-fine), DF (down-fine), UP, DOWN, and T.CONST.

The signals LREF and LREF are the reference signal on the conductor 320 and its inverse. The signals LLOCK and LLOCK are derived from logical circuitry not shown which responds to the time difference between the incoming sync pulses and the transitions of the reference signal; if a succession of sync pulses are close in time to the transitions then the signal LLOCK is produced, otherwise LLOCK is produced. The GOOD signal is produced by logical circuitry (not shown) in response to the incoming sync pulses and is produced unless the incoming sync pulses are missing or include a lot of spurious pulses due to noise which would interfere with the operation of the phase locked loop.

The signals UF, DF, UP and DOWN are applied to the current generator circuit shown in Figure 8. The signal T.CONST. is used to operate a switch connected in parallel with a resistor connecting together two parts of the capacitor 305 (Figure 5) so as to increase the time constant of the loop filter to improve the noise performance after lock has been achieved.

In the operation of the circuit shown in Figure 7, the counter and decoder 13,302 produces the reference signal and the inhibit signal from the 22 MHz oscillation from the V.C.O. 12. Before a negative going sync pulse appears on the conductor 328 the trigger 329 is held in the 11111 state.

At this time the Q output from the trigger 329 is low causing the output from the gate 330 to be low and hold the stages of the counter 326 in the "0" state. When reset the outputs of the counter 326 make the output of the gate 327 go high. Although the gate 325 is open the counter 326 cannot start to count the pulses of the 11 MHz oscillation because it is held by the resetting signal. The high output of the gate 327 causes the trigger 333 to be set to "1".

When a sync pulse occurs the trigger 329 is set terminating its 5 output and releasing the counter 326 which starts to count the 11 MHz pulses. This occurs in response to line synchronising pulses and the line synchronising parts of the field synchronising pulses.

The counting continues until the total in the counter 326 reaches nineteen when the output of the gate 327 goes low. The trigger 333 is set to "0" at the next pulse of the 11 MHz oscillation after the output of the gate 327 goes low. This means that the Q output of the trigger 333 is high for twenty pulses of the 11 MHz oscillation, or 1.82 microseconds, after the start of counting. The gate 332 receives the Q output from the trigger 333 as one of its four inputs.

The incoming sync pulses are also applied via the inverter 331 to the gate 332 so that the gate receives each pulse as soon as it starts. The Q output of the trigger 333 is high at this time because it was set when the counter 326 was reset at the end of the preceding incoming sync pulse and was held in that state by the trigger 329.

Other inputs of the gate 332 are the Q output of the trigger 334 and the GOOD signal. The trigger 334 is set in response to the INHIBIT signal from the counter and decoder 13,302 so that the gate 332 does not produce a high output when the INHIBIT signal is present. The GOOD signal is present unless the incoming signal is bad for some reason.

The gate 332 therefore produces a high output for the part of the short sync pulse ((c) of Figure 3) period starting with the leading edge of the incoming sync pulse until the end of the Q output from the trigger 333 that is not overlapped by an inhibit pulse (i.e. when the Q output from trigger 334 is high). This assumes that the GOOD signal is present. If the V.C.O. 12 is locked to the incoming sync pulses the LLOCK signal is present, so that the two parts of the short sync pulse not overlapped by the inhibit pulse enable the gates 336 and 337 to respond to the signals LREF and LREF and cause small (fine adjustment) urrents to be applied to the capacitor 305 for fine tuning of the control voltage for the v.C.O. 12. The loop gain is relatively low under these conditions giving improved noise rejection.Also under these circumstances the signal T.CONST. is produced by the gate 340 to close the switch to join the two parts of the capacitor in parallel and increase the time constant of the phase locked loop. If the V.C.O.

12 is not locked to the incoming sync pulses the signal LLOCK is produced enabling the gates 338 and 339, the outputs of which control larger (coarse adjustment) currents to be applied to the capacitor 305. At this time the signal T.CONST. is not produced so that the two parts of the capacitor 305 are not joined which decreases the time constant of the control loop to increase its capture range.

It should be noted that the use of the counter 326 and the gates associated with it as described above has the advantage that although a spurious pulse in the incoming signal may start the counter and cause current to be fed the capacitor 305 for the duration of the pulse and thereby produce a small error in the voltage on the capacitor 305, the circuit will still respond correctly to the proper sync pulses and put right those errors.

Figure 5 is the circuit diagram of the precision matched current sources 304 (Figure 5). The signals UF, DF, UP and DOWN from Figure 7 are applied respectively to conductors 350, 351, 352 and 353. The currents are determined by a circuit 354 connected to an external resistor (not shown) at a terminal BIAS. The output current is fed along conductor 355 to the capacitor 305 (Figure 5).

The conductor 350 is connected via a CMOS inverter 356 to the gate of a MOSFET 357 connected in series with a MOSFET 358 between a supply conductor Vcc and the output conductor 355.

The conductor 351 is connected directly to the gate of a MOSFET 359 connected in series with a MOSFET 360 between a grounded supply conductor GND and the output conductor 355.

The conductor 352 is connected through a CMOS inverter and complementary MOSFET switches 361 to the gate of a MOSFET 362 connected between the supply conductor Vcc and the output conductor 355.

The conductor 353 is connected through a CMOS inverter and complementary MOSFET switches 363 to the gate of a MOSFET 364 connected between the supply conductor GND and the output conductor 355.

MOSFET's 365 controlled by the current determining circuit 354 feed a constant current to a circuit 366 which controls the current passed by the MOSFET 358 and together with the inverter and switches 361 controls the current passed by the MOSFET 362.

MOSFET's 367 controlled by the current determining circuit 354 feed a constant current to a current mirror circuit 368 which in turn feeds a constant current to a circuit 369. The current passed by the MOSFET 360 is controlled by the circuit 369 and the current passed by the MOSFET 364 is also controlled by the circuit 369.

The current supplied by the MOSFET's 365 is twice that supplied by the MOSFET's 367, but the current mirror 368 is constructed so as to feed to the circuit 369 twice the current it itself receives from the MOSFET's 367.

Therefore, the currents fed to the circuits 366 and 369 are of equal magnitude but of opposite polarity due to the polarity reversal produced by the current mirror 368.

When the circuit is required to produce small currents in response to the signals UF and DF, the MOSFET's 357 and 359 are rendered conducting by the signals thereby allowing the currents passed by the MOSFET's 358 and 360 to flow to the output conductor 355. The circuits 366 and 369 operate as current mirrors to control the currents passed by the transistors 358 and 360 in response to the currents the circuits 366 and 369 themselves receive.

When larger currents are required these are provided by the MOSFET's 362 and 364 in response to the UP and DOWN signals on conductors 352 and 353. Again the circuits 366 and 369 control the currents passed by operating as current mirrors but in conjunction with MOSFET's X14 and Xl9 rendered conducting by the UP and DOWN signals.

In the circuit 366 the MOSFET's XC5 and XC6 are controlled by the voltage on the output conductor 355. The MOSFET's XC4, XC5 and XC6 influence the voltage produced on the gate of MOSFET X12 due to the current from MOSFET's 365, and the control provided by the MOSFET's XC5 and XC6 serves to adjust the current fed to the conductor 355 through the MOSFET 362 or through the MOSFET 358 to be more nearly a constant multiple of the current from the MOSFET's 365. The MOSFET's XC1, XC2 and XC3 in the circuit 369 operate in the same way to adjust the current fed to the conductor 355 through the MOSFET 364 or through the MOSFET-360 to be more nearly a constant multiple of the current fed to the circuit 369 from the MOSFET's 367 via the current mirror 368.As a result of the current adjustments the positive and negative currents supplied by the circuit of Figure 8 are accurately matched in magnitude for a large range of voltages on the conductor 355.

It should be noted that all of the MOSFET s used in Figure 5 to control the magnitudes of the currents, as distinct from those operating as switches, have the same channel length.

The use of the inhibit pulse to reduce the time periods for which the currents are applied to the capacitor 305 has the advantage of reducing the phase errors in the adjustment of the V.C.O. 12 due to mismatching of the positive and negative currents from the current sources.

The phase detector can, of course, be used for other purposes than synchronising an oscillator to incoming television sync pulses. The reduction in the charging time periods for capacitor is particularly advantageous for applications in which the periods would be of relatively long duration.

Claims (6)

CLAIMS:

1. A phase detector circuit for producing an output voltage indicative of the phase relationship between a first signal and a second signal, the first signal including a transition from a first logic state to a second logic state and the second signal including a pulse of particular duration, the circuit including gating means having inputs for the first and second signals and producing pairs of output signals of complementary durations, each pair representing the time of occurrence of the transition of the first signal relative to the middle of the pulse of the second signal, current source means responsive to each pair of output sianals of the gating means to provide positive and negative currents of equal magnitude for the respective durations of the output signals of the particular pair, and capacitor means connected to receive the currents from the current source means and produce therefrom the output voltage, wherein means is provided for restricting the total of the durations of a pair of output signals from the gating means to being substantially less than the duration of a pulse of the second signal.

2. A phase detector circuit according to claim 1 including a source of an inhibit signal of shorter duration than the pulse of the second signal and symmetrically disposed about the transition of the first signal, the gating means having a further input to which the inhibit signal is applied so that during an inhibit signal the gating means produces no output signal.

3. A phase detector circuit substantially as described herein and as illustrated by Figures 2, 3, 4 and 5 of the accompanying drawings.

4. A phase locked loop including a phase detector circuit according to claim 1 or 2, a voltage controlled oscillator for producing an oscillation of frequency dependent on the output voltage from the phase detector circuit, a first counter connected to receive the oscillation from the oscillator and responsive to an input signal to produce the second signal, and a second counter connected to receive the oscillation from the oscillator to produce the inhibit signal.

5. A phase locked loop according to claim 4 including a substantially direct path for at least a part of the input signal to the gating means, so as to provide substantially immediate control of the current source means in response to the input signal.

6. A phase locked loop substantially as described herein and as illustrated by Figures 2, 3, 4 and 5 of the accompanying drawings.