GB2251860A

GB2251860A - Ceramic tilled fluoropolymeric composite material

Info

Publication number: GB2251860A
Application number: GB9127158A
Authority: GB
Inventors: David J Arthur; Iii Allen F Horn; Gwo S Swei; Brett Kilhenny
Original assignee: Rogers Corp
Current assignee: Rogers Corp
Priority date: 1991-01-17
Filing date: 1991-12-20
Publication date: 1992-07-22
Also published as: ITMI920063A1; FR2671932A1; JP3409066B2; IT1262930B; GB9127158D0; ITMI920063A0; DE4200583A1; JPH05202259A

Abstract

An electrical substrate material comprises a ceramic filled fluoropolymer wherein the ceramic is coated with a silane and the ceramic has a volume % fraction of between 26-45. The substrate exhibits excellent chemical resistance, particularly to alkaline environments. Preferably the silane comprises a blend of at least one phenyl silane and at least one fluorosilane. The silane is preferably coated to a level of greater than 2 to 10% of the total weight of ceramic filler. The present invention has particular utility in filling openings, e.g. ground planes and in bonding multilayer printed wiring boards or constructing printed wiring boards by foil lamination. The ceramic filler is preferably fused amorphous silica. The fluoropolymer is preferably a polymer of tetrafluoroethylene, hexafluoropropene or perfluoroalkyl vinyl ether.

Description

7 2 5 1 J, ', 1 CERAMIC FILLED FLUOROPOLYMERIC COMPOSITE MATERIAL This

invention relates to an electrical substrate material comprising fluoropolymeric material and ceramic f iller material which is particularly well suited for use as a bonding ply in a multilayer circuit board and in other electronic circuit applications requiring the ability to f low as well as good thermal, mechanical and electrical properties. The fluoropolymeric composite material of this invention also exhibits resistance to chemical degradation, particularly high pH (alkaline) environments.

US Patent No. 4,849,284, which is incorporated herein by reference, describes a ceramic filled fluoropolymerbased electrical substrate material (sold by Rogers Corporation under the trademark RO-2800). This electrical substrate material preferably comprises polytetrafluoroethylene filled with silica along with a small amount of microfiberglass. In an important feature of this material, the ceramic filler (silica) is coated with a silane coating material which renders the surface of the ceramic hydrophobic and provides improved tensile strength, peel strength and dimensional stability. The composite material of US Patent No. 4,849,284 discloses a volume % f iller fraction (on a void free basis) of at least 50 for use as a circuit substrate or a bonding ply.

The ceramic filled fluoropolymer-based electrical substrate material of US Patent No. 4,849,284 is well suited for forming rigid printed wiring board substrate materials and exhibits improved electrical performance over other printed wiring board materials. Also, the low coefficients of thermal expansion and compliant nature of this electrical substrate material results in improved surface mount reliability and plated through-hole reliability. As is known, individual. sheets of this electrical substrate material may be' stacked to form a 35 multilayer circuit board. In fact, thin film formulations of the material disclosed in U.S. Patent No 4,849,284 (and 2 sold by Rogers Corporation under the trademark RO-2810) may be used as a bonding ply to bond together a plurality of stacked substrate layers so as to form the multilayer circuit board.

It will be appreciated that high volume fractions (greater than 55 volume %) of ceramic filler will significantly and adversely effect the rheology (e.g. flow) of the ceramic filled fluoropolymer composite. This is particularly important when the composite is used as a bonding film or in filling openings in previously rigid structures. While ceramic filler volume fractions of 50-55% provide significantly improved rheological properties relative to higher filler fractions, there is a perceived need to provide even better flow properties to the fluoropolymeric composite without appreciably altering the excellent thermal, mechanical and electrical properties.

In addition to the adverse effects on rheology, it has also been determined that ceramic filler volume fractions of 50% and greater also have an adverse impact on the chemical resistance of the filled fluoropolymeric composite with respect to certain hostile environments, particularly high pH (alkaline) baths. Such high pH baths (e.g., greater than pH = 12) are required for electroless copper deposition, which is a highly desirable and often used process in the manufacture of fine line circuitry (i.e., multichip modules). It has been found that high levels (50 volume % and greater) of ceramic filler may impart poor chemical resistance to the fluoropolymeric circuit material during long exposures in such alkaline baths. The resultant degradation caused by the poor resistance to the alkaline baths leads to a reduction in the hydrophobicity of the fluoropolymeric composite. In turn, this reduction leads to increased moisture absorption with a corresponding and highly undesirable decrease in the electrical properties of the composite circuit material.

1 3 In US Patent No. 5,061,548 (fully incorporated herein by reference) it had been discovered that the ceramic f iller content of the material disclosed in US Patent No. 4,849,284 may be as low as 45 volume % on a void-free basis and still retain adequate thermal, mechanical and electrical properties to be used as a bonding ply in multilayer circuit materials and as a f illing material for certain rigid structures. The ceramic filled fluoropolymeric composite material of US Patent 5,061,548 has improved rheology relative to the material of US Patent No. 4,849,284 and is useful in those applications requiring access holes and feature filling by resin flow without an excessive increase in the material's zaxis CTE.

The objective of the present invention is to reduce and/or alleviate the serious chemical degradation associated with the high filler content (e.g., 50 % and greater) fluoropolymer composites of us Patent No. 4,849,284 during long exposure to high pH baths.

In accordance with the present invention, objective is achieved by employing lower ceramic filler levels of as low as about 26 volume % on a void free basis, said filler being silicone coated.

The resultant ceramic filled composite has excellent mechanical and electrical properties; and exhibits a significant improvement (relative to composites of higher filler levels) in alkaline resistance.

In accordance with another important feature of this invention, it has been discovered that relatively large amounts of silane coating of up to 2-10% (of the total weight of the ceramic filler) leads to improved properties, particularly with respect to laser drilling for forming plated througholes and solid post vias. The use of 10% (and preferably 6 %) coating is surprising and unexpected as it had been generally believed (as described in US Patent No. 4,849,284) that silane levels should be between 1 4 to 2 %; and that no appreciable improvements were obtained in high levels of up to 6-10 %.

The preferred silane coating comprises a blend of phenylsilane and fluorosilane. This combination imparts excellent chemical resistance to alkaline baths and also promotes laser drilling capability. Also, the combination of the relatively less expensive phenylsilane and the more expensive fluorosilane provides an extremely cost effective coating.

The above-discussed and other features and advantages of the present invention will be appreciated and understood by those of ordinary skill in the art from the following detailed description and drawings, wherein:

FIGURE 1A and 1B are respective cross-sectional elevation views of a rigid structure having openings prior and subsequent to being filled with the composite material of the present invention; FIGURE 2 is a cross-sectional elevation view of a multilayer circuit board employing the thermoplastic composite material in accordance with the present invention as a thin film bonding ply; FIGURE 3 is a graph showing the ef f ect of silane and coated silica filler level M on laserability of the composite material at 248 nm, 3.gj/cm2 beam energy; and 25 FIGURE 4 is a cross- sectional elevation view of a circuit board in accordance with the present invention. The ceramic filled fluoropolymeric composite of the present invention is substantially similar to the composite described in US Patents No. 4,849,284 and No 30 5,061,548 (both of which have been fully incorporated herein by reference) with the exception that (1) in a first embodiment, ceramic is present on a void-free basis in an amount of as low as about 26 volume %; and (2) in a second embodiment, the ceramic filler is coated with up to 10% silane (with respect to the total weight of the ceramic filler). All of these embodiments preferably utilize a blend of phenylsilane and fluorosilane for coating the ceramic filler. In a preferred embodiment, the f irst embodiment of the present invention comprises a composite of particulate ceramic filler present at a volume fraction of about 0.26 to less than 0.45 and fluoropolymer (e.g. PTFE) present at a volume fraction of 0.74 to 0.55 on a void-free basis. The preferred ceramic filler is fused amorphous silica. All other compositional features and methods of manufacture are 10 the same as that disclosed in US Patent No. 4,849,284 (including the ceramic being coated with a silane) with the exception of preferred higher weight percents of silane coating and the preferred silane blends, both of which will be described hereinafter. Accordingly, reference is to be made to US Patent No. 4,849,284 for those details. The materials comprising the present invention can be produced either by "wet blending" PTFE polymer in dispersion with the ceramic filler and coagulation or by dry blending of PTFE fine powders with the ceramic filler. 20 The reduction in f iller content to as low as about 26 volume % leads to significant increase in the resistance of the fluoropolymer composite material to alkaline environments. In the comparison of examples 1 and 2 shown in Table 1 below, example 1 is a composite of the type 25 described in US Patent No. 4,849,284 having a composition of 50% PTFE fluoropolymer, 50% silica filler and a phenyl silane filler coating of 2 weight %. Example 2 is a composition in accordance with the present invention having a composition of 37.1% silica filler, 62.9% PTFE fluoropolymer and a blend of phenyl and fluoro-silanes (3:1 ratio) of 6 weight % (with respect to the total f iller weight).

6 TABLE 1

Example 1 Example 2 Xylene Absorption M 5.3 2.7 H20 Absorption (%).05.02 H20 Absorption (%) 1.7.07 Insulation Resistance 90 > 300 (M ohm) CTE (ppmOC) 40 60 Laser Ablation Threshold 1.7 1.3 (j/cm2) After 24 hours in O.1M NaOH, 1% Triton, 23C After 8 hours in O.1M NaOH, 1% Triton, 60C is The results of Table 1 clearly show that H20 absorption (after treatment in an alkaline bath) significantly decreases with decreased filler amount (e.g., 0.07% for the present invention versus 1.7% for the material of US Patent No 4,849,284). It will be appreciated that acceptable H20 absorption should be less than about 0.1%. The results of Table 1 are verified in the additional examples 3-12 of Table 2. In examples 6-11, the silane coating comprises a blend of phenyl silane and fluorosilane. Example 12 utilizes a phenyl silane coating.

7 TABLE 2

Example SILICA %/SILANE SP.GRAV INITIAL' Conditioned2 H20 Absorption H20 Absorption 3 30 0 2.2047 0.5152 0.5895 DRY 4 40 0 2.1970 1.1160 1.2474 DRY so 0 2.1452 2.3566 2.0443 DRY 6 29.3 2.1971 0.0435 0.0428 DRY 7 39 2.1800 0.0361 0.0886 DRY 8 48.6 2.1201 0.0774 0.4099 DRY 9 27.9 2.1859 0.0458 0.0500 DRY 37.1 2.1654 0.0140 0.0727 DRY 11 46.1 2.1163 0.0613 0.5869 DRY 12 48.6 2.1130 0.0400 1.7640 DRY CONTROL _# H20 absorption (24 hours, 50OC) with no alkaline bath pre-conditioning 2 H20 absorption (24 hours, 50C) after 24 hours in 0.1M NaOH, 1% Triton, 23C 8 Table 2 again shows that decreasing filler content leads to an increase in chemical resistance to high pH treatment as evidenced by the decrease in water absorption with decreasing f iller content. A comparison of Examples having equal silane coatings (such as examples 3-5, 6-8 and 9-11) shows that the increased chemical resistance is provided, at least in part, by the lower filler levels. It will be appreciated that the low levels (e.g., 27 and 37 volume %) in accordance with the present invention are significantly improved with respect to the 50 volume % levels associated with composite of US Patent No 4,849,284. Thus, a f illed f luoropolymeric circuit material composite of this invention having a f iller level of about 26 (note that Table 3 depicts examples having f iller contents down to about 26 volume %) to less than 45 volume % provide significant advantage relative to the material of both US Patent No 5,061,548 (filler levels of 45 to less than 50 volume %) and US Patent No 4,849,284 (filler levels of 50 volume % and greater).

In accordance with still another feature of this invention, it has been found that higher coating levels of up to 10% (and preferably 6%) by weight of the total ceramic filler contribute to improved laser ablation results. This discovery is unexpected as it had been believed and suggested in US Patent 4,849,284 that silane coating levels of 1 to 2% were preferred, and that above 2%, the effect of the silane coating is negligible. Two criteria used in determining laser ability of circuit materials include (1) the energy level required for ablation (lower levels are preferred); and (2) the deviation from perfectly straight (no taper) ablated hole walls (with 0 degrees deviation being preferred). Figure 4 shows the cross-section of a circuit board having a laser abalted hole 2 formed in a substrate 4 (made from the composite of this invention) having a layer of copper 6 thereon. The angle "a" represents the deviation from a A 9 straight wall. Table 3 shows the laser ablation results for an array of coating amounts and ceramic filler amounts for dry and wet blended compositions. Examples 13-30 and 32-38 use silica filler while examples 31 and 39 use quartz filler.

1 TABLE 3 LASER ABLATION THRESHOLD AT 248 nm FOR VARIOUS PTFE/CERAMIC COMPOSITIONS Example Blend Method Filler Content Coating Filler Size Ablation Threshold (j/cm2 13 DRY 46.1 6% 3:1 lou 1.3 14 WET 46.1 6% 3:1 lou 1.3 is WET 37.1 6% 3:1 lou 1.3 16 WET 43.8 10% 3:1 1.su 1.3 17 DRY 37.1 6% 3:1 lou 1.3 18 DRY 27.9 6% 3:1 lou 1.7 19 WET 35.3 10% 3:1 1.5u 1.7 WET 27.9 6% 3:1 lou 1.7 21 WET 26.7 10% 3:1 1.5u 1.7 22 WET 48.6 2% 3:1 lou 1.7 23 DRY 48.6 2% 6124 lou 1.7 24 DRY 48.6 2% 6124 lou 1.7 DRY 48.6 2% 3:1 lou 1.7 k r.' r I,> C.

11 TABLE 3 (continued) Example Blend Method Filler Content Coating Filler Size Ablation Threshold (j/cm2) 26 DRY 39.0 2% 3:1 lou 1.7 27 WET 39.0 2% 3:1 lou 2.7 28 WET 48.6 2% 3:1 lou 2.7 29 DRY 48.6 2% 3:1 lou 2.7 DRY 39.0 2% 3:1 lou 2.7 31 DRY 29.3 2% 6124 Quartz 2.7 32 DRY 29.3 2% 3:1 lou 2.7 33 WET 29.3 2% 3:1 lou 2.7 34 WET 35.3 10% 3:1 1.5u 2.7 WET 40 % Untreated lou 3.9 36 DRY 50 % Untreated lou 3.9 37 WET 30 % Untreated lou 3.9 38 DRY 30 % Untreated lou 3.9 39 DRY 30 % Untreated Quartz 3.9 12 The results of Table 3 indicate that high filler levels and high coating amounts provide the best laser ablation results (in terms of the lowest ablation threshold energy). Laser ablation results worsen as either filler level, or coating level, or both go down. The filler coating can significantly reduce ablation threshold, even for low filler levels such as 26%. This is quite evident when examples 18 and 20 are compared with example 36. In Table 3, coatings indicated by the ratio 3:1 are three parts phenyl silane to one part fluorosilane. The coating identified as 6124 is phenyl trimethoxy silane and the fluorosilane is tridecafluoro-1,1,2,2-tetrahydrooctyl-l-triethoxysilane having a chemical formula of C6F13CH2CH2Si(OCH2CH3h and hereinafter referred to as C6F.

This effect of composition on laserability (at 248 nm for 3.9 j/cm2 beam energy) is also shown in Figure 3 where the diagonal lines represent the derivation from straight of a lased hole walls (with the lower angle being preferred). in Figure 3, the "Silica Filler Levels" include the volume % contributed by the silane coating. Figure 3 indicates that higher silane amounts and/or higher ceramic filler amounts lead to improved laser ablation (hole wall quality). Note that low levels of ceramic filler preferably use high levels of silane.

In accordance with still another feature of this invention, it has been found that the silane coating is preferably a blend of phenylsilane and fluorosilane. The fluorosilane imparts chemical resistance to alkaline exposure while the phenysilane promotes laser drilling; and is less expensive than the fluorosilane. Table 4 demonstrates the superiority of fluorosilane to phenylsilane in imparting resistance to alkaline degradation. The preferred blend is phenylsilane to fluorosilane in weight ratio of 3:1. Examples of suitable 13 phenylsilanes and fluorosilanes are described in detail in US Application Serial No 279,474 filed December 2, 1988 (now US Patent No...) and fully incorporated herein by reference 14 TABLE 4

SILANE SILANE TYPE(%) LEVEL C6F C6F C6F 6 6124 4 INITIAL' CONDITIONED2 H20 ABSORPTION(%) H20 ABSORPTION(%) 2.142 0.03 0.33 2.143 2.139 2.097 EXAMPLE FILLER CONTENT(%) 48.6 47.3 46.1 47.3 BLEND METHOD DRY DRY DRY DRY 41 42 43 0.04 0.04 0.02 0.41 0.50 0.99 1 H20 Absorption (48.hrs., 500 without alkaline pre-conditioning H20 Absorption (48 hrs., WC) after 24 hrs. in 0.1M aqueous NaOH, 1 weight % Triton X-100, 23C.

0 (11 .# 1 1 By this reduction in f iller content, the rheology of the material of the present invention is improved to the point that it will "flow" and fill comparatively large openings in thick metal foils or inner layers of circuitry that cannot be filled by some of the highly filled (greater than 55 volume % fraction) materials disclosed in US Patent No 4,849,284.

An important feature of the present invention is the fact that the rheology is improved without excessively increasing the Z-axis coefficient of thermal expansion (CTE) of the material. The Z-axis CTE of the 30-45 volume % filler formulation has been measured to be considerably less than the widely used fiber reinforced PTFE over the temperature range of -55 to + 125'C (typically about 200 is ppm/C (see Table 5). Multilayer circuit boards made from RO 2800 laminate bonded together with bonding ply layers of the present invention will exhibit an overall CTE considerably lower than that of a fiber reinforced PTFE board. The decreased CTE is important in increasing the reliability of plated through holes and vias to withstand thermal cycling and high temperature assembly.

TABLE 5

Example Material -55/+125 Silane %/ Filler % ppm/c 44 2130 94 2140 68 46 2/50 41 47 6/30 84 48 6/40 72 49 6/50 47 The present invention extends the number of applications in which ceramic filled PTFE composite materials can be used for constructing useful printed wiring boards. The present invention has the particular 16 utility in f illing openings in already rigid structures, such as etched CIC voltage or ground planes and restraining cores, or circuitry bonded to such structures. For example, in Figure 1A, a rigid ground plane structure is depicted in 5 cross-section at 50 several having openings 52. Sheets 54, 56 of the present invention (e.g., about 0.26 to 0.45 volume fraction ceramic) are then positioned on either side of ground plane 50. In Figure 1B, the stack-up 58 of Figure 1A is laminated under heat and pressure. The composition of this invention will permit good f low so as to completely f ill the openings while also providing excellent thermal, mechanical and electrical properties.

In addition and referring to Figure 2, the composite of this invention may be processed into a sheet in its undensified, unsintered form and used for bonding multilayer printed wiring boards or constructing printed wiring boards by foil lamination. Turning now to Figure 2, such a multilayer circuit board is shown generally at 10. Multilayer board 10 comprises a plurality of layers of substrate material 12, 14 and 16, all of which are comprised of an electrical substrate material, preferably the ceramic filled fluoropolymeric material of US Patent No 4,849,284 sold under the RO-2800 trademark. Each substrate layer 12, 14 and 16 has a conductive pattern 18, 20, 22 and 24 respectively thereon. Note that a substrate layer having a circuit pattern thereon defines a circuit substrate. Plated through holes 26 and 28 interconnect selected circuit patterns in a known manner.

In accordance with the present invention, separate sheets 30 and 32 of substrate material having a composition in accordance with the present invention are used as an adhesive or bond ply to laminate individual circuit substrates together. In a preferred method of forming such a laminate, a stack-up of circuit substrates altered with one or more layers of the bond ply is made. This stack-up is then fusion bonded whereby the entire multilayer j? 17 assembly is melted and fused into a homogeneous construction with consistent electrical and mechanical properties throughout. Significantly, note that the adhesive bond ply layers 30 and 32 may be used to laminate 5 circuit substrates comprised of materials other than the silane coated ceramic filled fluoropolymer of US Patent No 4,849,284. Although, in a preferred embodiment, a multilayer circuit board includes circuit substrates which are all comprised of the electrical substrate material of US Patent No 4,849,284.

The highly filled composites referred to in US Patent 4,849,284 (e.g. 50 + vol % filler) are very suitable for most printed wiring board designs (e. g., large multilayer boards for mainframe computers (CPU boards), military surface mount assemblies and microwave circuit board bonded assemblies). However, for special MLB applications requiring thick voltage planes relative to the dielectric thickness (e.g., thick power planes, thick restraining foils for CTE control), a lower filler content is required (e.g., 45-50 vol %) to provide adequate flow, as indicated in aforementioned US Patent 5,061,548. The lower filler amounts of about 26% to less than 45% in accordance with this invention is a response to the evolution of circuit process technology for the fabrication of multichip modules which specifically require laser drilling of small holes, good flow, and alkaline resistance for electroless baths. The low filler amounts of this invention may not make a good conventional Multilayer Board (as will the material described in US Patent 4,849,284), but the material of US Patent 4,849,284 is not suitable for certain multichip module applications which are emerging as a preferred packaging technology for high speed high density designs.

18

Claims

1. An electrical substrate material comprising fluoropolymeric material and ceramic filler material characterized in that said filler material is in an amount of at least about 26 to less than 45 volume percent of the total substrate material and said ceramic filler being coated by a silane coating.

2. The material as claimed in claim 1 characterized in that said fluoropolymeric material is selected from the group comprising polytetrafluoroethylene, hexa fluoropropene, tetrafluoroethylene or perfluoro alkyl vinyl ether.

3. The material as claimed in claim 1 or 2 characterized in that said ceramic filler comprises silica.

4. The material as claimed in any one of the claims 1 to 3 characterized in that said silane coating is selected from the group comprising pchloromethyl phenyl trimethoxy silane, amino ethyl amino trimethoxy silane, a mixture of phenyl trimethoxy silane, and amino ethyl amino propyl trimethoxy silane, fluorosilane and a blend of at least one fluorosilane and at least one phenylsilane.

5. The material as claimed in any one of the claims 1 to 3 characterized in that said silane coating is in an amount of greater than 2 to about 10 weight percent relative to the weight of the ceramic filler.

6. The material as claimed in claim 5 characterized in that said silane coating comprises a blend of at least one fluorosilane and at least one phenylsilane.

7. The material as claimed in claim 1 characterized by at least one layer of conductive material being disposed on at least a portion of said electrical substrate material.

8. The material as claimed in any one of the claims 1 to 6 characterized in that it forms an adhesive layer sandwiched between at least a first and a second layer in a multilayer circuit.

a 19

9. The material as claimed in any one of the claims 1 to 6 characterized in that it is used to fill at least one opening (52) provided in a rigid substrate (50).

10. An electrical substrate material substantially as hereinbefore described with reference to the accompanying drawings.