GB2247565A

GB2247565A - A method of testing a semiconductor device

Info

Publication number: GB2247565A
Application number: GB9018448A
Authority: GB
Inventors: David John Pedder
Original assignee: General Electric Co PLC
Current assignee: General Electric Co PLC
Priority date: 1990-08-22
Filing date: 1990-08-22
Publication date: 1992-03-04
Anticipated expiration: 2010-08-22
Also published as: GB9018448D0; GB2247565B

Abstract

The method comprises flip chip bonding said device 1 to a test and burn-in substrate 3 having solderable metallisation pads 4 smaller than the pads of said device 1, subjecting said device 1 to test and burn-in procedures and thereafter debonding the device 1 from said substrate while retaining at least the major portion of the solder originally provided in the bumps 2 of said device 1. <IMAGE>

Description

A method of testing a semiconductor device The invention relates to a method of testing a semiconductor device.

A classical problem in the assembly of any hybrid circuit, comprising a number of packaged or unpackaged IC devices to be assembled on an appropriate circuit interconnection substrate, is connected with the fact that the probability that each chip in the assembly is actually functional is less than unity. The yield of the assembled hybrid is then the product of all the individual chip yield probabilities and the assembly yield, or, expressed mathematically: Y = [ F.(B)m ] n where Y = final circuit yield F = probability that an IC is functional B = probability of forming individual IC to substrate connection m = number of connections per chip n = number of ICs in the circuit assembly.

This power law dependance of circuit yield means that is essential to employ very high yield assembly processes and to have a high confidence that every IC is functional prior to committing it to the assembly. The flip chip solder bonding technique, in which an array of solder bumps are provided over the contact pads on the naked IC and the IC attached to the substrate in an inverted attitude, has been shown to provide an appropriately high yield.

In uncooled IR detector arrays, for example, 100% bond yield has been obtained in devices with 10,000 solder bond connections, implying an individual bond yield of 99.99% or better.

Unfortunately with the use of naked, unpackaged ICs, such as are employed in many forms of hybrid circuit construction, the individual IC probability of functionality is not as high as this.

More typical figures are between 90% and 99%. This is partly due to the difficulty of testing bare, unpackaged ICs thoroughly, particularly at the final operating frequency, and to the statistical nature of testing high complexity devices where the test patterns can only sample a portion of the device's functional requirements. This then means that, as the number of ICs in the assembly increase, the circuit yield will decrease and rapidly approach the point where it becomes unacceptably low. The dependance of circuit yield on IC confidence and assembly yield probability is illustrated in Figure 1. It is clear, from Figure 1, that a bonding process with 99.99% yield and an IC confidence figure of 99% is required to exceed a first pass yield of over 80% in a ten chip multi chip assembly with 100 1/0 devices.

There is therefore a clear requirement to devise methods that ensure high individual IC functional confidence and, where this is not possible, to develop methods for the identification and replacement of defective devices. Equally it is important to ensure that the circuit will remain functional once it has been assembled by ensuring that the devices are not prone to early failure (or infant mortality). This aspect of yield is normally addressed by adopting burn-in procedures that subject devices to accelerated stress testing prior to circuit assembly to ensure that infant mortalities are weeded out at the test stage. Again such procedures are generally difficult to employ with unpackaged devices except where tape automated bonding is employed.

According to the invention there is provided a method of testing a semiconductor device having solderable metallisation pads and solder bumps, the method comprising the steps of flip chip bonding said device to a test and burn-in substrate having solderable metallisation pads smaller than the pads of said device, subjecting said device to test and/or burn-in procedures and thereafter debonding the device from said substrate while retaining at least the major portion of the solder originally provided in the bumps of said device.

The step of debonding may be carried out by raising the temperature of the bonded surfaces of said device and substrate at or above the melting temperature of the solder and thereafter separating the device from the substrate by application of a force acting along an axis perpendicular to the bonded surfaces of said device and substrate.

Preferably said device is separated from said substrate by pulling said device away from the substrate by using a vacuum clamping chuck. The bonded surfaces of said device and substrate are protected from oxidation thereof.

In order to avoid oxidation the bonded surface may be kept in an inert or reducing atmosphere or environment during the period the temperature of the bonded surfaces is raised and during any elevated temperature burn-in procedure.

The solder bumps on the semiconductor device may be protected from oxide, for example, by the use of a rosin flux.

The invention will now be described further by way of example with reference to the accompanying drawings in which: Figure 1 is a graph which shows a circuit yield versus IC count; Figure 2 illustrates a silicon IC device with solder bumps and a test and burn-in silicon substrate with solderable metallisation pads; Figure 3 illustrates the device of Figure 2 flip chip bonded to the substrate of Figure 2 for the purpose of testing and burn-in procedure to to be carried out on said device; Figure 4 illustrates the device of Figure 3 debonded from the substrate; and Figure 5 illustrates the tested and burn-in devices bonded to the MCM substrate.

Referring to Figure 1 a silicon IC device 1 is provided with solderable metallisation pads (not shown) and solder bumps 2.

The solderable metallisations include Cr-Cu-Au and Ti-Pt, whereas solder compositions include 95wt.XPb-5wt.%Sn (liquidus temperature 310 C) or the Sn-Pb eutectic alloy. The pad dimensions are typically 100 to 120 microns square.

The devices are first flip chip bonded, as shown in Figure 2, to a compact test and burn-in silicon substrate 3 which is larger than the IC device 1, and is provided with solderable metallisation pads 4 and solder bumps if required. The pads 4 are significantly smaller in dimensions than those on the IC devices.

The silicon substrate 3 is constructed with a multilayer aluminium-polyimide metallisation structure 5, with typically four layers of interconnect, a ground plane, a power plane and two layers for signal trace routing. The track geometries on the silicon substrate 3 are between 10 and 25 micron l-,ne widths at track pitches of 40 to 100 microns, while dielectric thicknesses are in the 5 to 20 micron range. Such geometries allow controlled impedance, 50 ohm lines to be defined. Alternative materials include copper as the conductor material and a range of alternative polymers, including BCB and PPQ. The flip chip solder bonds and the silicon substrate interconnect provides very low electrical parasitic interconnections between the customised location of the IC pads and the standarised location external connection points on the silicon test and burn-in substrate 3. The test and burn-in substrate 3 is accessed by means of a standard probe card 6, high performance membrane probe card or other means of connection, to allow testing of the flip chip bonded device. Provided that the probe card construction allows it, the devices may then be tested at frequency and burn-in procedures followed as required. Precautions are taken to avoid oxidation of the solder bond surfaces during any elevated temperature burn-in procedures, for example through the use of closed, inert atmospheres, vacuum techniques or reducing atmospheres, or inert fluids.

After test and burn-in, the device 1 is separated from the test substrate by following a debonding process in which the device is raised to an elevated temperature at or above the solder melting temperature and the softened or fused solder bonds fractured, illustrated as in Figure 4, by means of a tensile force applied to the device. The use of smaller pads 4 on the substrate 3 ensures that the bonds will separate with the majority of the solder volume retained on the IC device 1. Devices that have passed the test and burn-in procedures may then be bonded onto the final multi chip module silicon substrate 7, as illustrated in Figure 5, with high confidence of functionality and without the need for difficult bond site dressing or rebumping procedures. In this case the solderable pads on the final MCM substrate may be of the same size as those on the IC device, in order to maximise bond strength and to minimise electrical and thermal resistance. Equally smaller pads may be retained on the MCM substrate in order to provide further rework potential. The standardised test and burn-in substrates are then potentially available for reuse, making their use less of a cost penalty.

Claims

1. A method of testing a semiconductor device having solderable metallisation pads and solder bumps, the method comprising the steps of flip chip bonding said device to a test and burn-in substrate having solderable metallisation pads smaller than the pads of said device, subjecting said device to test and/or burn-in procedures and thereafter debonding the device from said substrate while retaining at least the major portion of the solder originally provided in the bumps of said device.

2. A method as claimed in Claim 1, in which said step of debonding is carried out by raising the temperature of the bonded surfaces of said device and substrate at or above the melting temperature of the solder and thereafter separating the device from the substrate by application of a force acting along an axis perpendicular to the bonded surfaces of said device and substrate.

3. A method as claimed in Claim 2, in which said device is separated from said substrate by a vacuum clamping chuck acting on said device.

4. A method as claimed in any one of Claims 1 to 3, in which the bonded surfaces of said device and substrate are protected from oxidation thereof.

5. A method as claimed in Claim 4, in which said bonded surfaces are kept in an inert atmosphere or reducing atmosphere during the period the temperature of the bonded surfaces is raised and during an elevated temperature burn-in procedure.

6. A method as claimed in any one of the preceding claims, in which said device is a silicon integrated circuit device.

7. A method as claimed in any one of the preceding claims, in which said substrate is a multi chip module type substrate.

8. A method as claimed in any one of Claims 1 to 6, in which said substrate is a silicon substrate having a multilayer aluminium-polyimide metallisation structure.

9. A method as claimed in Claim 8, in which said structure has a ground layer, a power layer and two layers for signal trace routing.

10. A method as claimed in any one of the preceding claims, in which said substrate is accessed by a probe card to allow testing of the flip chip bonded device.

11. A method as claimed in any one of the preceding claims, in which the solder bumps are protected from oxidation by a layer of rosin.

12. A method as claimed in any one of Claims 1 to 10, in which the solderable metallisation pads are formed of Cr-Cu-Au or Ti-Pt and the solder composition includes 95wt.% Pb-Swt.%Sn or Sn-Pb eutectic alloy.

13. A method of testing a semiconductor device substantially as hereinbefore described with reference to, and as illustrated in, the accompanying drawings.