GB2247124A - Duty-cycle to analog demodulator - Google Patents

Abstract

A demodulator circuit comprising in combination; (a) first circuit means for receiving a digital input signal that is modulated to represent an analog input signal (VIN) and producing in response thereto a switch control signal (131) including a sequence of pulses; (b) a first current source (43A); (c) switching means (54) for electrically coupling the first current source to a first summing node (176) during the pulses of the switch control signal; (d) integrating circuit means having a first input coupled to the first summing node and an output for integrating a current flowing from the first summing node to the first input; (e) a sample and hold circuit having an input coupled to the output of the integrating circuit means and an output, and a sample control input responsive to the digital input signal; (f) a feedback resistor coupled between the output of the sample and hold circuit and the first summing node, the output of the sample and hold circuit means producing an analog output signal (VOUT) that accurately represents the analog input signal, the sample and hold circuit operating to subtantially reduce ripple voltage on the analog output signal. <IMAGE>

Description

ISOLATION AMPLIFIER INCLUDING PRECISION VOLUAGB- TO-DUTY-CYCLE CONVERTER AND LOW RIPPLE. HIGH BANDWIDTH CHARGE BALANCE DEMODULATOR The invention relates to isolation amplifiers and to modulation and demodulation techniques that may be useful in isolation amplifiers, including circuitry for converting voltageto-frequency, phase, or pulse width representations thereof, and to circuitry for converting such representations back to a voltage or current signal representative of the original analog voltage, and also including a high precision voltage-to-dutycycle conversion technique and a low ripple, high bandwidth technique for converting such representations back to an analog signal representative of the original input voltage.

Voltage-to-duty-cycle conversion techniques and voltage-to-frequency conversion techniques are commonly used in various applications. Recovery of an analog input voltage is frequently accomplished by duty-cycle-to-voltage demodulators or frequency-to-voltage demodulators. Examples of common applications of such circuits include switching power supplies, DC-to-DC converters, and isolation amplifiers. In the prior art, precision voltage-to-duty-cycle conversion has been performed by comparing a linear triangular waveform voltage to an analog input voltage level, producing a '1' level when the triangular waveform voltage exceeds the analog input voltage, and producing a .0" level when the triangular waveform voltage is less than the analog input voltage.As the analog input voltage is increased, the duty cycle of the digital output waveform is decreased proportionally. The accuracy of - the voltage-to-duty-cycle transfer function depends greatly upon the linearity of the triangular waveform and on the accuracy of the comparator used, and some of the information contained in the analog input voltage is lost. Also, the accuracy of such prior voltage-to-duty cycle conversion circuits is subject to input offset errors, i.e., errors in the relationship between a zero value of the analog input voltage and the corresponding 50 percent duty cycle of the duty-cycle-modulated (DCH) digital output waveform.

Charge balanced demodulators of the type that perform frequency-to-voltage conversion or duty-cycle-to-voltage conversion are well-known. Such circuits receive a frequency modulated or duty-cycle encoded input pulse signal. This signal typically is applied to a high pass filter and applied to the input of a suitable demodulation interface circuit, which can be a one-shot circuit for a frequency-to-voltage converter or an edge triggered latch circuit for a duty-cycle-to-voltage converter. The output of the demodulation interface circuit controls a switch that couples a constant reference current to the inverting input of an operational amplifier, the non inverting input of which is connected to ground. The output of the operational amplifier is connected through an integrating circuit including an integrating feedback capacitor and a parallel feedback resistor to the inverting input.The average current through the feedback capacitor must be zero, and the output voltage of the operational amplifier assumes a value necessary to cause the inverting input to be at a virtual ground voltage. The transfer characteristic of the output voltage to the modulated input signal frequency or duty-cycle is very accurate, but the output voltage contains a large amount of ripple voltage. Although the amount of ripple voltage can be decreased by increasing the feedback capacitance, the bandwidth also is decreased. The trade-off between the bandwidth and ripple voltage is a significant limitation in many systems, such as in servo loops, wherein the ripple must be low but low bandwidth may cause loop instability.

Previous techniques used to minimize ripple voltage without affecting bandwidth have been less than satisfactory because they limit the range of carrier frequencies at which the demodulator can operate and/or they limit the accuracy of the transfer characteristic. For example, using a low pass filter in series with an output is not effective if a large operating frequency range is required. Furthermore, such filters are expensive. Another technique is to use the charge balanced demodulator as a feedback component in a phase locked loop, but this technique suffers from lack of versatility and is complex and expensive. Another technique has been to utilize a sample and hold circuit at a demodulator output and sample the output at a specific time during the demodulation cycle.This technique often adds greater error to the circuitry than already existed due to offsets and sample timing errors in the sample and hold circuit.

Isolation amplifiers are a common application of voltage-to-duty-cycle conversion circuits and charge balanced demodulators. The analog input voltage is converted to a digital signal, the duty-cycle of which represents the amplitude of the analog input voltage.

This digital signal can be accurately transmitted over a standard isolation barrier, such as an optically coupled device or a transformer. After transmission o ar the isolation barrier, the input voltage signal is reconstructed by a duty-cycle to voltage demodulator. The accuracy of such isolation amplifiers has been limited by the above-mentioned inaccuracies of prior voltage-toduty-cycle converters and prior charge balanced demodulators.

A problem of demodulators in circuits such as isolation amplifiers is that noise signals may be close to the modulator/demodulator carrier signal frequency. If this is the case, the modulator produces a difference signal of relatively low frequency, the carrier signal itself, and a sum signal having the frequency equal to the sum of the noise signal and the carrier signal.

Ordinarily, it is quite easy to filter out the carrier signal and the sum signal, but difficult to filter out the difference signal(because its frequency is low) without also filtering the desired low frequency modulation signal.

Another probi em wi th prior isolation amplifiers is the difficulty of achieving a precise, transfer function that is relatively independent of temperature and variations in processing parameters.

It is another object of the invention to provide a voltage-to-duty-cycle converter circuit that is accurate despite non-linearities in a triangular waveform input voltage thereto.

It is another object of the invention to provide a charge balanced demodulator which has low ripple and high bandwidth without degrading the accuracy of the transfer chacteristic.

It is another object of the invention to provide a lost cost, high performance isolation amplifier capable of undergoing very large, rapid changes in the differences between ground voltages on opposite sides of the isolation barrier without loss of infcrmation or data than is the case for the closest prior art isolation amplifiers.

Briefly described, and in accordance with one embodiment thereof, the invention provides a modulatordemodulator system including a modulator circuit including a first current switching circuit for producing a first current that is switched between positive and negative values in response to a duty-cycle-modulated signal produced by the modulator circuit in response to an analog input voltage, an isolation barrier for transmitting the duty-cycle-modulated signal to a demodulator circuit included in the isolation amplifier, the demodulator circuit including a second current switching circuit for producing a second current that is switched between positive and negative values in response to the duty-cycle-modulated signal transmitted across the isolation barrier.In one described embodiment of the invention, the demodulator is a charge balanced demodulator wherein a sample and hold circuit has an analog input coupled to an output of an integrating circuit that integrates the second current to produce an output of the sample and hold circuit and an analog output voltage that is accurately representative of the analog input voltage. The analog output voltage is coupled by a feedback resistor to the input of an operational amplifier included in the integrating circuit. A charge balance capacitor of the integrating circuit is connected between the output of the operational amplifier and an input thereof. In a described embodiment of the invention, the first and second current switching circuits are precisely matched to produce the same ratios of positive to negative values in response to the duty-cycle-modulated signal.Both the demodulator circuit and modulator circuit are fabricated on separate portions of a single large semiconductor chip, and trimmable components are precisely trimmed to produce the precise matching. The semiconductor chip then is cut into separate pieces to provide a modulator chip and a demodulator chip which are packaged in a single package and connected to terminals of small capacitors which constitute the isolation barrier. In one described embodiment, the modulator includes an integrating circuit which integrates the algebraic sum of the input current and the first current. The output of that integrating circuit is applied to one input of a hysteresis comparator, the output of which drives the first current switching circuit.A signal synchronized to a known noise signal is applied to the other input of the hysteresis comparator, causing the modulator carrier frequency to be synchronized to the noise signal. This prevents the modulator from generating a low frequency beat signal that would be difficult to filter. In another embodiment, the sample and hold circuit is implemented by a "bucket brigade" sample and hold circuit which includes two sample and hold circuits cascaded together to further reduce voltage ripple in the analog output voltage.

Fig. 1 is a circuit diagram of a charge balanced demodulator of the present invention.

Fig. 2 is a timing diagram useful in explaining the operation of the charge balance demodulator of Fig. 1.

Fig. 3 is a circuit diagram of a prior art isolation amplifier utilizing a voltage-to-duty-cycle modulator and a dutycycle-to-voltage demodulator.

Fig. 4A is a block diagram of a voltage-to-duty-cycle modulator with switched positive and negative current feedback and including a free-running oscillator.

Fig. 4B is a voltage-to-duty-cycle modulator with switched positive and negative current feedback and a hysteresis comparator that establishes an internal oscillation frequency.

Fig. 4C is a block diagram of an isolation amplifier with voltage-to-duty-cycle modulation as in Fig. 4B and dutycycle-to-voltage demodulation.

Fig. 4D is an isolation amplifier with voltage-to-dutycycle modulation and a duty-cycle-to-voltage demodulator that includes a sample and hold circuit in an integrator feedback loop to reduce output voltage ripple.

Fig. 5 is a detailed schematic circuit diagram of the isolation amplifier of Fig. 4D.

Fig. 6 is a timing diagram for the circuit of Fig. 5.

Fig. 7 is an improved bucket brigade' sample and hold circuit which can be utilized in the circuit of Fig. 6.

Fig. 8 is a timing diagram for the sample and hold circuit of Fig. 7.

Fig. 9 is a diagram illustrating fabrication of the modulator and demodulator sections of an isolation amplifier on a single semiconductor chip, cutting the chip in halr and packaging the separate modulator and demodulator chips in a package on opposite sides of an isolation barrier component.

Fig. 10 is a diagram of a current source circuit that can be used in the circuits of Figs. 1, 4A-D, and 5.

Referring now to Fig. 1, charge balanced demodulator circuit 1 receives digital input voltage VIN on conductor which is connected to one terminal of a capacitor 3. The other terminal of capacitor 3 is connected by conductor 6 to one terminal of resistor 4, the other terminal of which is connected to demodulator - ground conductor 5 and to one terminal of resistor 7, the other terminal of which is connected to a positive power supply voltage +V. Conductor 6 is also connected to a sample control input of a sample and hold circuit 22 and a demodulation interface circuit 8. Demodulation interface circuit 8 can include an edge triggered flipflop for turning switch 12 on i response to a positive pulse and turning switch 12 off in response to a negative pulse to achieve duty-cycle-to-voltage conversion. The output of demodulation interface circuit 8 is connected by a conductor 11 to the control input of a switch 12, which can be a JFET (junction field effect transistor). The current carrying terminals of switch 12 are connected to a constant reference current source 13, which produces a reference current 1PREFERENCE The other current carrying terminal of switch 12 is connected by conductor 14 to the inverting input of an operational amplifier 15. The non-inverting of amplifier 15 is connected to ground conductor 5. Conductor 14 is also connected to a second constant current source 16, through which a constant offset current IOFFSET flows. The output 17 of amplifier 15 is connected to one terminal of charge balance capacitor 18, the other terminal of which is connected to conductor 14.Conductor 17 also is connected to the analog voltage input of sample and hold circuit 22, the output of which is connected to conductor 23, on which an output voltage VOUT is produced. A feedback resistor 21 having a resistance R1 is connected between conductors 14 and 23.

Referring now to Fig. 2, VIN(DCM) waveform 2 is a dutycycle-modulated voltage that represents an analog input signal.

The positive-going edges of VIN(DCM) cause a differentiating circuit or high pass filter including capacitor 3 and resistors 4 and 7 to produce waveform 6 on conductor 6. (A one-shot circuit could be used in place of the circuit 3, 4, 7.) In waveform 6, dotted line 22A designates the sample threshold voltage of sample and hold circuit 22. Demodulation interface circuit 8 responds to the positive-going edges of the positive spikes in waveform 6 to turn switch 12 on, as indicated by node 11. The negativegoing edges of the negative pulses of waveform 6 turn off switch 12. The sample time 24 is determined by the times that the positive-going edges and negative-going edges of the positive pulses of waveform 6 cross the sample threshold voltage 22A.

When the voltage of conductor 6 is above tne tnreshold level 22A, the output voltage VOUT on conductor 23 precisely tracks or follows the voltage produced on conductor 17 by the output of operational amplifier 15. When the voltage on conductor 6 then falls below sample threshold level 22A, the voltage VOUT on conductor 23 then is precisely held at its present value until the voltage of waveform 6 again exceeds sample threshold level 22A. (Various circuits that are commercially available can perform this function, such as a new sample and hold technique shown in Figs. 7 and 8.) The duration of the sample time 24 is determined by the response of the high pass filter circuit 3, 4, 7 to the dutycycle-modulated input VIN(DCM). The feedback loop from conductor 23 to conductor 14 through resistor 21 causes the current through resistor 21 to exactly equal the sum of IOFFSET and the average switched reference current 1PREFERENCE The value of IOFFSET can be varied to adjust VOUT without affecting the transfer function relating VIN(DCM) to VOUT. With the charge balance of capacitor 18 preserved, and with the current through resistor 21 proportional only to VOUT, the accuracy of demodulator 1 is independent of the accuracy of the sample and hold circuit 22, which merely alters the ripple characteristics of waveform 17.

The sample time 24 is determined by the level of the sample threshold voltage 22A and the fall time of the high pass filter 3, 4, 7. The feedback loop including capacitor 18 and resistor 21 maintains conductor 14 at a virtual ground voltage that is equal to the voltage of demodulator ground conductor 5. Waveform 17 is a triangle waveform resulting from the charging and discharging of capacitor 18 with constant currents through resistor 21 and the difference current between 1OFFSET and the switched IREFERENCE current, which depends on the state of switch 12. The value of VOUT shown by waveform 23 ifs the sample value of waveform 17 during the sample time 24 and is held constant at the last value occurring during the previous sample time 24.If droop of VOUT during the whole period is negligible, the ripple is reduced over that of waveform 17 by a factor of 1/[2f.(sample time 24)].

This circuit gives a ripple reduction of as much by a factor of 100 to 1000 over that achievable without the sample and hold circuit 22 connected as shown.

It should be noted that the charge balanced demodulator of Fig. 1 is not unconditionally stable, but it is unconditionally stable for all input frequencies above the critically compensated frequency of l/Rl-Cl, the resistance and capacitance of resistors 21 and 18, respectively. Practical phase modulated carriers usually will have a minimum frequency well above this value.

Referring next to Fig. 3, a basic prior art isolation amplifier is shown. The isolation amplifier includes a voltageto-duty-cycle modulation circuit including a comparator 46 and a precision triangle waveform generator 58 connected between modulator ground conductor 36 and an inverting input of comparator 46. An analog input voltage VIN is applied by conductor 32 to the non-inverting input of comparator 46. The output of comparator 46 is connected to one terminal of an isolation barrier capacitor 133 or other means of signal coupling, the other terminal of which is connected to the input of a switching circuit 54. Switching circuit 54 couples a '2I current sources 43A to a current source 103 that produces a constant current flow I.The circuitry 43A, 54, 103 is referred to as an '1-21 current switch' which, depending upon the state of the current switch 54, causes a positive or negative current I to flow into or out of conductor 164.

An integrating circuit includes resistor 57 connected between conductor 164 and demodulator ground conductor 5, and a capacitor 56 connected between conductor 164 and ground conductor 5. This integrating circuit integrates the duty-cycle-modulated signal that is produced at the output of comparator 46 and transmitted across the isolation barrier capacitor 133. Thus, the I-2I current switch 54 in combination with the integrating circuit 56, 57 forms a duty-cycle-tc-voltage demodulator. The output ripple voltage component of VOUT can be decreased by increasing the capacitance of capacitor 56, but the isolation amplifier bandwidth is correspondingly reduced. The linearity of this isolation amplifier relies directly on the linearity of the triangle waveform of generator 58.

In accordance with the present invention, the duty cycle modulation circuit contained in Fig. 4A includes a feedback loop that connects the output of comparator 46 by means of conductor 47, I-2I current switch 91, 92, 93, and conductor 34 to the inverting input of an operational amplifier 35. The output conductor 37 of operational amplifier 35 is connected by a feedback capacitor 38 to conductor 34. Conductor 34 also is connected by an input resistor 33 having a resistance RIN to input conductor 32, to which the analog voltage VIN is applied, causing an input current IIN equal to VIN/RIN to flow through resistor 33. The modulator ground conductor 36 is connected to the non-inverting input of operational amplifier 35. Amplifier output conductor 37 is connected to the non-inverting input of comparator 46.

This circuit operates by summing either +I or -I with IIN at conductor 34. This causes the integrator including resistor 33, operational amplifier 35, and capacitor 38 to vary the "threshold" voltage applied by conductor 37 to the noninverting input of comparator 46 to thereby vary the threshold of comparator 46 to whatever value is needed to cause the dutycycle-modulated signal V0UT(DcM) on conductor 47 to produce an average value I and -I currents fed back to node 34 to be equal to VIN.The advantage of this mode of operation is that the duty-cycle modulator signal produced on conductor 47 is essentially independent of the linearity of the free-running oscillator circuit 58. The duty-cycle-modulated signal produced on conductor 47 accurately represents the analog input voltage VIN regardless of whether free-running oscillator 58 produces a precise, linear triangular waveform or even, for example, a sinusoidal waveform.

Fig. 4B shows a variation of the circuit shown in Fig.

4A in which the free-running oscillator 58 has been eliminated, and comparator 46 is designed with hysteresis. In this circuit, the inverting input of hysteresis comparator 46 is connected to modulator ground conductor 36. The amount of ripple voltage of the integrator output on conductor 37 and the hysteresis voltage between the triggering levels of the non-inverting input of hysteresis comparator 46 are proportional to the frequency of oscillation.

Referring to Fig. 4C, which shows an isolation amplifier, the duty-cycle-modulated output voltage produced on conductor 47 (by a modulator circuit like the one in Fig. 4B) is connected to one terminal of isolation capacitor 133, the other terminal 131 of which is connected to a duty-cycle-to-voltage converter, thereby producing an isolation amplifier. Operational amplifier 153 has its inverting input connected to conductor 176.

Capacitor 151 and output resistor 158 are connected in parallel between conductors 164 and 176, 8o operational amplifier 153 functions as an integrator. The non-inverting input of operational amplifier 153 is connected to demodulator ground conductor 5. Current switches 91 and 54 are precisely matched.

The ratio of "21' current sources 92 and 43A is precisely matched to the ratio of and "I' current sources 93 and 103. The transfer function of the isolation amplifier of Fig. 4C is indicated in the equation VOUT = (ROUT/RIN)VIN.

The isolation amplifier of Fig. 4C has a ripple voltage equal to VRIPPLE = VHYSTERESIS (ROUT/RIN) (CIN/COt)T), where VHYSTERESIS is the difference between the trip points of hysteresis comparator 46. In order to eliminate most of this ripple voltage, the circuit shown in Fig. 4D is provided, including a sample and hold circuit 152 (as in Fig. 1) in the feedback loop between the output of integrator 153 and the inverting input thereof.

Referring to Fig. 5, isolation amplifier 99 -includes a capacitive isolation barrier including capacitors 133 and 134. A voltage-to-duty-cycle converter circuit 95 similar to the one in Figs. 4B-D produces duty-cycle-modulated output signals which are logical complements on conductors 131 and 132. These logical complement signals are applied to the left-hand terminals of isolation barrier capacitors 133 and 134, respectively.

Reference numeral 96 designates a charge balanced duty-cycle-tovoltage demodulator having its logical complement inputs connected to the right-hand terminals of isolation barrier capacitors 133 and 134, respectively.

The analog input voltage signal VIN is applied to conductor 32. Conductor 32 is connected by means of input resistor 33 to conductor 34, which also is connected to the inverting input of operational amplifier 35, one terminal of feedback capacitor 38, to the drain electrode of P channel JFET 41A, and to constant current source 93. The output of operational amplifier 35 is connected by conductor 37 to the other terminal of capacitor 38, to the drain electrode of P channel JFET 44A, and to the inverting input of hysteresis comparator 46. (Bysteresis comparator 46 can be a conventional comparator with positive feedback, as shown in Fig. 5 by reference numerals 46, 118, and 119.) The output of hysteresis comparator 46 is connected by conductor 47 and feedback resistor 118 to its non-inverting input.The non-inverting input of hysteresis comparator 46 is also connected by resistor 119 either to modulated ground conductor 36, or optionally to a conductor 120 on which a noise synchronization signal VNOISE is applied.

The output of hysteresis comparator 46 is connected to the noninverting input of a differential comparator 130, the inverting input of which is connected to ground conductor 36. Differential comparator 130 produces logical complement duty-cycle encoded signals on conductors 131 and 132 for transmission across the above-mentioned isolation barrier capacitors 133 and 134 to conductors 170 and 172, respectively.

The source electrodes of JFETs 41A and 44A are connected by conductor 42 to "2I" constant reference current source 92. The gate electrode of JFET 41A is connected to the gate electrode of another P channel JFET 107 and to a conductor 101. Conductor 101 is connected to the non-inverted output of a differential comparator 121, the non-inverting input of which is connected by conductor 166 to one terminal of a capacitor 128 and to one terminal of resistor 123. The other terminal of resistor 123 is connected to modulator ground conductor 36.

Differential comparator 121 has an inverting input connected by conductor 167 to one terminal of capacitor 129 and to one terminal of resistor 126, the other terminal of which is connected to modulator ground conductor 36. A feedback resistor 125 is connected between conductor 167 and an inverted output of amplifier 121 by means of conductor 168. Conductor 168 is connected to the gate electrodes of JFET 44A and a P channel JFET 114. The source electrodes of JFETs 107 and 114 are connected by conductor 169 to '21' constant current source 111.

The drain electrode of JFET 107 is connected to resistor 110, the other terminal of which is connected to modulator ground conductor 36.

The drain electrode of JFET 114 is connected by the parallel combination of resistor 115 and capacitor 116 to modulator ground conductor 36.

The right-hand terminal of isolation barrier capacitor 133 is connected by conductor 170 to the non-inverting input of differential comparator 137, to one terminal of resistor 139, and to one terminal of feedback resistor 140. The non-inverted output of differential comparator 137 is connected to the other terminal of resistor 140 and also is connected by conductor 171 to the gate electrode of P channel JFETs 147 and 148. The other terminal of resistor 139 is connected to demodulator ground conductor 5. The right-hand terminal of isolation barrier capacitor 134 is connected by conductor 172 to the inverting input of differential comparator 137, to one terminal of resistor 142, and to one terminal of resistor 141. The other terminal of resistor 141 is connected to demodulator ground conductor 5. The inverted output of differential comparator 137 is connected by conductor 173 to the other terminal of resistor 142 and the gate electrode of P channel JFETs 143 and 144.

The source electrodes of JFETs of 144 and 147 are connected by conductor 175 to 1211 constant current source 43A.

The drain electrode of JFET 144 is connected by conductor 161 to one terminal of capacitor 151 and to the output of operational amplifier 153. Conductor 161 also is connected to the input of a sample and hold circuit 152 (which can be implemented by means of a sample and hold circuit such as one included in a Burr-Brown Sic5320). The sample control input of sample and hold circuit 152 is connected to one terminal of capacitor 149, the other terminal of which is connected to one terminal of resistor 150 and to the drain electrode of JFET 143. The other terminal of resistor 150 is connected to demodulator ground conductor 5.

The drain electrode of JFET 147 is connected to the other terminal of capacitor 151 and to the inverting input of operational amplifier 153. The non-inverting input of operational amplifier 153 is connected to demodulator ground conductor 5. The inverting input of operational amplifier 153 also is connected by conductor 176 to "I" constant current source 103 and to one terminal of resistor 158. The other terminal of resistor 158 is connected to conductor 164, on which an analog output voltage VOUT that is accurately representative of the analog input voltage VIN is produced.

The source electrode of JFETs 143 and 148 are connected to 21' current source 146. The drain electrode of JFET 148 is connected to one terminal of resistor 156, the other terminal of which is connected to demodulator ground 5.

The output of sample and hold circuit 152 is connected by conductor 160 to the non-inverting input of an operational amplifier 178, the output of which is connected by conductor 164 to one terminal of feedback resistor 163. The other terminal of feedback resistor 163 is connected to the inverting input of operational amplifier 178 and to one terminal of resistor 162, the other terminal of which is connected to ground conductor 5.

Fig. 10 shows a circuit which can be used to implement the various "21" and 'I' current sources in Figs. 1, 4A-D, and 5.

Numeral 94 designates a constant reference current, and resistors 196-199 are laser trimmable nichrome resistors that are used to adjust the currents 21 and I.

In operation, the analog input voltage VIN applied to conductor 32 produces the current 11N across input resistor 33 (the resistance of which is RIN), since operational amplifier 35 maintains its inverting input at the voltage of modulator virtual ground 36. The amplitude of I is greater than the amplitude of IIN. IIN is summed with either +I or -I in capacitor 38, depending upon whether the output conductor 37 of operational amplifier is ramping up or ramping down. The output of comparator 46 is produced on conductor 47 and is transmitted to differential input comparator 130, the inverted and non-inverted differential outputs of which are connected to conductors 132 and 131, respectively.The logical complement signals produced on conductors 131 and 132 are applied to inputs of two identical differential cells 190 and 191. Differential cell 190 is included in demodulator 96, and differential cell 191 is included in modulator 95. The complementary duty-cycle-modulated signals on conductors 131 and 132 therefore are precisely reproduced on conductors 101 and 168 in modulator 95, and identical replicas of the signals on conductors 131 and 132 also are produced on conductors 171 and 173 of demodulator 96.

In each of differential cells 190 and 191, the replicas of the duty-cycle-modulated signals on conductors 131 and 132 are utilized to switch in '21" current sources 43A and 92, thereby turning transistor 41A on and 44A off, thereby switching "21" current source 92 into conductor 34 if IIN is to be compared with the feedback current +I (as in Figs. 4B-D) to cause the output of operational amplifier 35 to "ramp down". When the negative threshold of the hysteresis comparator 46 is reached, the voltage on conductor 47 switches, reversing the polarity of the signals on the output conductors 131 and 132 of differential comparator 130, so now IIN is compared with -I, and the output of operational amplifier 35 "ranps up" until the positive threshold of hysteresis comparator 46 is reached.

Start-up circuit 188 simply ensures a DC current flow between conductors 167 and 47 when power is initially applied to modulator 95, thereby ensuring proper start-up thereof.

In the embodiment of the invention shown in Fig. 5, the isolation barrier capacitors 133 and 134, and also capacitors 128 and 129, all are equal to the small value of 1 picofarad. This small capacitance means that the voltage modulator ground 36 and the demodulator ground 5 can move very rapidly relative to each other (for example in response to line voltage pulses produced in response to static discharges) without affecting the transfer function of the isolation amplifier.

Since differential cells 191 and 190 are precisely matched, and since the P channel JFETs 147 and 144 precisely match P channel JFETs 41A and 44A, and the resistance RIN of input resistor 33 and the resistance RoUT of output resistor 158 are precisely matched, the switching operation of "21" current source 43A and "I" current source 103 into node 176 are essentially identical to the switching of "21" current source 92 and "I" current source 93 into node 34. JFETs 148 and 143 and resistor 150 produce a sample signal to sample and hold circuit 152 to cause appropriate sampling, as previously described with respect to Figs. 1 and 2.This synchronizes the sampling period with the duty-cycle-modulated signal on conductors 131 and 132 to reduce the amount of ripple on conductor 160.

Referring now to Fig. 6, VIN is the analog input signal waveform applied to conductor 32. The voltage produced by operational amplifier 35 on conductor 37 is indicated by waveform 37. Waveform 37A is equal to the difference between the voltages on hysteresis comparator inputs 37 and 39. The duty-cyclemodulated signal produced by modulator 95 is indicated by waveform 194, which is the difference between the voltages on isolation barrier input conductors 131 and 132. The input voltages V171 and V173 transmitted across the isolation barrier capacitor to conductors 171 and 173 of demodulator 96 is indicated by waveform 195, which shows the difference between V171 and V173 The output of operational amplifier 153 of demodulator 96 is shown by waveform 161. The resulting value of VOUT produced on conductor 164 is shown by waveform 164. The waveforms of Fig. 6 were generated by simulating the circuit shown in Fig. 5 on the well-known circuit analysis program SPICE.

As indicated in Fig. 5, the lower end of resistor 119 can be connected to a noise synchronization conductor 120 instead of to modulator ground conductor 36. (It is well-known that beat frequencies, that is, sum and difference frequencies, may be created by the presence of noise at frequencies near a modulator carrier. The difference frequency components may 'alias1 back into the signal frequency spectrum.) In accordance with the present invention, and as shown in Fig. 9, modulator section 95 and demodulator section 96 are fabricated on a single semiconductor wafer, and preferably on adjacent chips in an area 97. The various nichrome resistors utilized for RIN and ROUT are precisely laser trimmed.The components of the two 1-21 current switches and certain other components in the modulator and demodulator sections are sufficiently close together that they are precisely matched.

After the laser trimming of the various nichrome resistors, including the current source resistors such as 196-199 of Fig.

10, the area 97 then is separated along dotted line 113 into two chips, one containing modulator 95 and the other containing demodulator 96. The two chips then are placed into a suitable package 98, with the output of modulator 95 and the input of demodulator 96 being connected to an isolation barrier including two capacitors 133 and 134. Alternately, the modulator chip 95 is located far from the demodulator chip 96, and the isolation barrier is a long optical fiber or the like.

In accordance with the present invention, if a known noise source VNOISE in a system is utilized to synchronize the operation of modulator circuit 95 with the noise source, then modulator 96 will not produce a beat frequency. This makes it necessary only to filter out the components of the output signal having a frequency equal to the carrier frequency; such filtering is accomplished by the demodulation. Thus, when there is a dominant noise frequency, such as power line noise, machinery noise, etc. the noise signal will be rejected it the modulator is synchronized to the noise frequency or to a subharmonic thereof.

In the synchronized mode the carrier frequency is fixed and is no longer a function of the input voltage. Rejection of signals at integer multiples of the carrier is accomplished by the system's integration of the input over every cycle of the carrier. This is shown mathematically as follows.

Assume VIN equals Acosine (Wit). Then

where T is equal to 2#/#C' #c being the carrier frequency.

Therefore,

Acosine(wit) = -A[sine(O)-sine(wi/wc-2n)J = A sine (27##i/#c).

Therefore, VOUT equals 0 if wi equals NWc, where N is an integer.

This means that if the input frequency wi is the harmonic of the carrier frequency Uct that is, the modulator carrier is synchronized to a subharmonic of a noise signal. The signal will have an amplitude of zero.

As previously indicated, in many applications noise is generated by well-known external sources. Such noise signals may be larger than the signal level to be passed across tfle isolation barrier of an isolation amplifier. However, such noise can be cancelled through 'cycle integration". The ability to eliminate the resulting signal by synchronizing the modulator carrier frequency with such a noise signal makes it possible to avoid difficult, low frequency filtering which would also interfere with demodulation of the desired signal and reduce bandwidth of the isolation amplifier.

The sample and hold circuit 152 shown in Fig. 5 and also described in detail with reference to Figs. 1 and 2 results in a substantial reduction in ripple voltage if the sample time can be a very small percentage of the sample cycle. In the isolation amplifier of Fig. 5, which is being designed to operate with bandwidth up to approximately 50 kHz, inherent circuit delays require that the sample time 24 in Fig. 2 be approximately one-tenth of the sample cycle. Consequently, the technique of utilizing a single sample and hold circuit 152 and the filter circuit 178 of Fig. 5 result in an unacceptably large amount of ripple. To overcome this, sample and hold circuit 152 and the circuit 178 of Fig. 5 are replaced by a "bucket brigade' sample and hold circuit 152A shown in Fig. 7.Bucket brigade sample and hold circuit 152A includes a first sample and hold circuit that includes operational amplifiers 60 and 66. The inverting input of operational amplifier 60 is connected to conductor 161 of Fig.

5. The non-inverting input of amplifier 60 is connected to conductor 71, which is connected to the output of operational amplifier 66 and to one terminal of capacitor 67. The other input of operational amplifier 66 is connected to the inverting input thereof. The non-inverted output 61 of amplifier 60 is connected to one input of a switching circuit 63 which connects conductor 61 to the inverting input 64 of operational amplifier 66 when the first sample and hold circuit is sampling. Switching circuit 63 can be similar to a DG 183 manufactured by Siliconix, or a conventional diode bridge current steering circuit. The inverted output of amplifier 60 is connected by conductor 62 to an input of switching circuit 63 which couples conductor 62 to the non-inverting input 65 of operational amplifier 66 when the first sample and hold circuit is sampling.Capacitor 68 is connected between demodulator ground 5 and conductor 65. When the first sample and hold circuit is in its hold mode, the outputs of amplifier 60 are disconnected from the inputs of operational amplifier 66.

A second sample and hold circuit included in bucket brigade sample and hold circuit 152A includes amplifier 72 and operational amplifier 81. The inverting input of amplifier 72 is connected to conductor 71. The non-inverting input of amplifier 72 is conrected by conductor 75 to one terminal of resistor 76, which is connected to demodulator ground conductor 5. Conductor 75 also is connected by resistor 77 to the output of operational amplifier 81 by conductor 164. The inverted output 79 of amplifier 72 is connected to one input of switching circuit 63, which switches the signal on conductor 71 to the non-inverting input 82 of operational amplifier 81. Conductor 82 is connected to one terminal of capacitor 84, the other terminal of which is connected to demodulator ground conductor 5. The inverted output of amplifier 72 is connected by conductor 74 to another input of switching circuit 63 which switches the signal on conductor 74 to the inverting input 83 of operational amplifier 81. Capacitor 85 is connected between the output and input of operational amplifier 81. The output of operational amplifier 81 is connected to output conductor 164.

The operation of bucket brigade sample and hold circuit 152A is simply that the logical complement signals on conductors 171 and 173 (i.e., the precise replicas of the complementary uty-cycle-modulated signals transmitted across the isolation barrier capacitors 133 and 134) cause either of the abovementioned sample and hold circuits contained in circuit 152A to be sampling while the other is holding, except during signal transitions. The switches contained in switching circuit 63 are of the type that are referred to as 'break before make' switches.

In other words, in switching circuit 63, switches 18u will break contact to cause the first sample and hold circuit 60, 66 to begin holding the input voltage on conductor 161 before the switches 181 make contact to acquire the value on conductor 71 and produce that value on output conductor 164. Similarly, when switches 181 are closed, so that the voltage on conductor 164 is sampling a voltage being held on conductor 71, switches 181 open before switches 180 close. Therefore, the sampling and holding operations of the two sample and hold circuits 60, 66 and 72, 81 overlap except during signal transitions.

In Fig. 8, waveform 171 designates the voltage on conductor 171, which controls switching circuit 63. Waveforms 71 and 164 designate the waveforms appearing on conductor 71 and VOUT conductor 164, respectively. During pulse 171A of waveform 171, the output of operaHtional amplifier 153 produces a rising slope 161A on conductor 161. The first sampling and hold circuit 60, 66 thereby causes conductor 71 to track precisely with slope 161A, as designated by reference numeral 71A. When waveform 171 undergoes its transition to level 171B, the first sample and hold circuit holds the level of slope 71A, as indicated by 71B.

Meanwhile, the second sample and hold circuit 72, 81, which was holding the previous value during pulse 171A, now samples the level 71B. This continues until the end of downward slope 161B, which is reversed to produce slope 161C when waveform 171 goes from level 171B to 171C. This causes the first sample and hold amplifier 60, 66 to now begin tracking the voltage at the lowest portion of slope 161B. Meanwhile, the second sample and hold circuit 72, 81 continues to hold the level 71B on conductor 164.

During pulse 171C, waveform 71 tracks with slope 161C, producing slope 71C. Thus, the VOUT waveform 164 has essentially no ripple voltage thereon.

The combined isolation amplifier including the circuit of Fig. 5 with sample and hold circuit 152 and filter 178 replaced by bucket brigade sample and hold circuit 152A provides very high performance isolation amplifier that has essentially no ripple voltage, and yet has high bandwidth. The small value (1 picofarad) isolation barrier capacitors are very inexpensive, and allow extremely rapid transitions of the modulated ground 36 and the demodulated ground 5 without affecting the transfer characteristic of the isolation amplifier.

The carrier frequency of the described system can be changed by merely changing the value of the integrator capacitor, which can be a great convenience. The described invention provides an inexpensive system that operates with low 'input offset" errors in the vicinity of the 50% modulation level of the carrier (which represents an analog input voltage VIN equal to zero volts) because the input offset is determined primarily by the digital signal integrity and the precise matching of current sources on opposite sides of the isolation barrier. The e accuracy of the demodulator is relatively independent of inaccuracies in the sample and hold circuit. The accuracy of the modulation is substantially independent on the linearity of any external synchronization source.

Claims (1)

1. A demodulator circuit comprising in combination: (a) first circuit means for receiving a digital input signal that is modulated to represent an analog input signal (VIN) and producing in response thereto a switch control signal (131) including a sequence of pulses; (b) a first current source (43A); (c) switching means (54) for electrically coupling the first current source to a first summing note (176) during the pulses of the switch control signal; (d) integrating circuit means having a first input coupled to the first summing node and an output for integrating a current flowing from the first summing node to the first input; (e) a sample and hold circuit having an input coupled to the output of the integrating circuit means and a output, and a sample control input responsive to the digital input signal; ; (f) a feedback resistor coupled between the output of the sample and hold circuit and the first summing node, the output of the sample and hold circuit means producing an analog output signal (VOUT) that accurately represents the analog input signal, the sample and hold circuit operating to substantially reduce ripple voltage on the analog output signal.