US7522086B2 - Reference circuits for sampled-data circuits - Google Patents
Reference circuits for sampled-data circuits Download PDFInfo
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- US7522086B2 US7522086B2 US11/617,228 US61722806A US7522086B2 US 7522086 B2 US7522086 B2 US 7522086B2 US 61722806 A US61722806 A US 61722806A US 7522086 B2 US7522086 B2 US 7522086B2
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
- H03M1/1245—Details of sampling arrangements or methods
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- the present invention relates generally to reference circuits for sampled-data circuits.
- the circuit consisting of switches S 21 , S 22 , S 23 , S 24 , and a second sampling capacitor C S2 comprise a part of the second switched-capacitor integrator.
- the output voltage, v out , of the first integrator 10 is sampled on the second sampling capacitor C S2 by closing switches S 21 and S 23 .
- FIG. 3 An example of a timing diagram is shown in FIG. 3 .
- the clock signal has two non-overlapping phases ⁇ 1 and ⁇ 2 .
- the phase ⁇ 1 is applied to switches S 11 , S 13 , S 21 , and S 23
- phase ⁇ 2 is applied to switches S 12 , S 14 , S 22 , and S 24 .
- the circuit performs non-inverting discrete integration with full clock delay.
- the waveforms at the output of the integrator, v out , and at the virtual ground node 100 , v 1 are also shown in FIG. 3 . Different clock phasing arrangements yield different responses from the integrator.
- v 1 For an accurate integration of the input signal, v 1 must be driven as close to ground as possible. In order to accomplish this, the operational amplifier must provide sufficient open-loop gain and low noise. In addition, for fast operation, the operational amplifier 10 of FIG. 2 must settle fast.
- the voltage v 1 is shown to settle back to ground after a disturbance when the sampling capacitor C S1 is switched to Node 100 by closing S 12 and S 14 .
- operational amplifiers In addition to high open-loop gain and fast settling time, operational amplifiers must provide large output swing for high dynamic range. As the technology scales, it becomes increasingly difficult to achieve these characteristics from operational amplifiers. The primary factors that make the operational amplifier design difficult are low power supply voltages and low device gain.
- Zero-crossing detectors can be applied in other switched-capacitor circuits such as algorithmic and pipeline analog-to-digital converters, delta-sigma converters, and amplifiers. These applications often require constant voltage sources, referred to as reference voltages.
- zero-crossing detectors in algorithmic analog-to-digital converters, pipeline analog-to-digital converters, delta-sigma converters, and amplifiers which apply voltage sources, such as reference voltages, in zero-crossing detector based circuits in a manner that reduces the power consumption required in such voltage sources without degrading noise performance or speed of zero-crossing based circuits.
- the analog-to-digital converter includes a level-crossing detector to generate a level-crossing detection signal when an input signal crosses a predetermined level; a waveform generator to generate a predetermined waveform; a first switched capacitance circuit; a switched capacitance circuit; a sampling switch, operatively coupled to the level-crossing detector; and a voltage reference circuit operatively coupled to the switched capacitance circuit.
- the sampling switch turns OFF when the level-crossing detection signal indicates the input signal crossed the predetermined level.
- the switched capacitor circuit includes a level-crossing detector to generate a level-crossing detection signal when an input signal crosses a voltage reference level; a waveform generator to generate a predetermined waveform; a switched capacitance circuit operatively connected to the level-crossing detector; a switch operatively coupled to the first level-crossing detector; and a voltage reference circuit operatively coupled to the switched capacitance circuit to provide a voltage reference level.
- the switch turns OFF when the level-crossing detection signal indicates the input signal crossed the voltage reference level.
- the switched capacitor circuit includes a first waveform generator to generate a first predetermined waveform; a first level-crossing detector to generate a first level-crossing detection signal when an input signal crosses a first voltage reference level; a first switch operatively coupled to the first level-crossing detector; a first sampling capacitor operatively connected to the first level-crossing detector; a second waveform generator to generate a second predetermined waveform; a second level-crossing detector to generate a second level-crossing detection signal when a second input signal crosses a second voltage reference level; a second switch operatively coupled to the second level-crossing detector; a second sampling capacitor operatively connected to the first level-crossing detector; and a third level-crossing detector differentially coupled to the first and second sampling capacitors.
- the first switch turns OFF when the first level-crossing detection signal indicates the input signal crossed the first voltage reference level.
- the second switch turns OFF when the second level-crossing detection signal indicates the second input signal crossed the second voltage
- the switched capacitor circuit includes a level-crossing detector to generate a level-crossing detection signal when an input signal crosses a first predetermined level; a waveform generator to generate a first predetermined waveform; a switched capacitance circuit operatively connected to the level-crossing detector; a voltage reference circuit operatively coupled to the switched capacitance circuit to provide a voltage reference level; a switch operatively coupled to the level-crossing detector; and a sampling capacitor operatively connected to the level-crossing detector.
- the switch turns OFF when the level-crossing detection signal indicates the input signal crossed the first predetermined level.
- the reference voltage source includes a level-crossing detector to generate a level-crossing detection signal when an input signal crosses a predetermined level; a waveform generator to generate a first predetermined waveform; a switch operatively coupled to the level-crossing detector; a sampling capacitor operatively connected to the level-crossing detector; a first bias voltage source operatively connected to an input terminal of the level-crossing detector; and a second bias voltage source operatively connected to the input terminal of the level-crossing detector.
- the switch turns OFF when the level-crossing detection signal indicates the input signal crossed the predetermined level.
- the reference voltage source includes a waveform generator to generate a predetermined waveform; a first transistor operatively connected to the waveform generator; a second transistor operatively connected to the waveform generator; a level-crossing detector to generate a level-crossing detection signal when an input signal crosses a predetermined level; a switch operatively coupled to the level-crossing detector; and a sampling capacitor operatively connected to the level-crossing detector.
- the switch turns OFF when the level-crossing detection signal indicates the input signal crossed the predetermined level.
- the reference voltage source includes a waveform generator to generate a predetermined waveform; an amplifier operatively connected to the waveform generator; a first bias voltage source operatively connected to the amplifier; a second bias voltage source operatively connected to the amplifier; and a level-crossing detector to generate a level-crossing- detection signal when an input signal crosses a predetermined level.
- the waveform generator turns OFF when the level-crossing detection signal indicates the input signal crossed a predetermined level.
- FIG. 1 illustrates a zero-crossing detector
- FIG. 2 illustrates a switched-capacitor integrator
- FIG. 3 illustrates a timing diagram for the switched-capacitor integrator of FIG. 2 ;
- FIG. 4 illustrates a non-inverting integrator according to the concepts of the present invention
- FIG. 5 illustrates a timing diagram for the non-inverting integrator of FIG. 4 ;
- FIG. 6 illustrates a non-inverting integrator with a waveform generator being a current source according to the concepts of the present invention
- FIG. 7 illustrates another non-inverting integrator according to the concepts of the present invention.
- FIG. 8 illustrates a timing diagram for the non-inverting integrator of FIG. 7 ;
- FIG. 9 illustrates another non-inverting integrator according to the concepts of the present invention.
- FIG. 10 illustrates another non-inverting integrator according to the concepts of the present invention.
- FIG. 11 illustrates a timing diagram for the non-inverting integrator of FIG. 10 ;
- FIG. 12 illustrates another non-inverting integrator according to the concepts of the present invention.
- FIG. 13 illustrates another non-inverting integrator according to the concepts of the present invention
- FIG. 14 illustrates a timing diagram for the non-inverting integrator of FIG. 13 ;
- FIG. 15 illustrates a pipeline analog-to-digital converter
- FIG. 16 illustrates a sampling phase of the pipeline analog-to-digital converter of FIG. 15 ;
- FIG. 17 illustrates a second phase of the pipeline analog-to-digital converter of FIG. 15 ;
- FIG. 18 illustrates a pipeline analog-to-digital converter based on a zero-crossing detector
- FIG. 19 illustrates a sampling phase of the pipeline analog-to-digital converter of FIG. 18 ;
- FIG. 20 illustrates a second phase of the pipeline analog-to-digital converter of FIG. 18 ;
- FIG. 21 illustrates a delta-sigma analog-to-digital converter
- FIG. 22 illustrates a bandgap reference circuit
- FIG. 23 illustrates a delta-sigma analog-to-digital converter based on a zero-crossing detector
- FIG. 24 illustrates another delta-sigma analog-to-digital converter based on a zero-crossing detector
- FIG. 25 illustrates a fully-differential analog-to-digital converter based on zero-crossing detectors
- FIG. 26 illustrates an analog-to-digital converter based on zero-crossing detectors
- FIG. 27 illustrates an analog-to-digital converter which provides a bandgap based discrete-time reference voltage
- FIG. 28 illustrates an analog-to-digital converter based on a bandgap reference voltage source
- FIG. 29 illustrates an operational amplifier preceded by a low-to-moderate gain preamplifier for a zero-crossing detector sampled-data circuit
- FIG. 30 illustrates an operational transconductance amplifier for a zero-crossing detector sampled-data circuit
- FIG. 31 illustrates another zero-crossing detector sampled-data circuit
- FIG. 32 illustrates another zero-crossing detector sampled-data circuit.
- the earth symbol indicates the system's common-mode voltage.
- the system's common-mode voltage may be at ground.
- the system's common-mode voltage may be at 1.25 V.
- FIG. 4 illustrates a non-inverting integrator according to the concepts of the present invention. More specifically, as an example, a non-inverting integrator with half-clock delay is illustrated in FIG. 4 .
- a clock phase ⁇ 1 is applied to switches S 11 , S 13 , S 22 , and S 24
- another phase ⁇ 2 is applied to switches S 12 , S 14 , and S 21 .
- a zero crossing detector 30 is used to detect the point of time at which Node 100 crosses ground.
- the switch S 23 is controlled by the output of the zero crossing detector 30 .
- the output of the zero crossing detector 30 is used to determine the time point to take the sample of the output voltage v out .
- a waveform generator 20 generates a voltage waveform as the output voltage v out in such way the voltage at Node 100 crosses zero if the charge in capacitors C S1 and C I1 is within a normal operating range.
- the waveform generated by the waveform generator 20 is shown as a ramp.
- v 1 the voltage at Node 100
- crosses zero at time t 1 the output v zc of the zero crossing detector 30 goes low, turning the switch S 23 OFF.
- the output voltage v out is sampled on C S2 .
- the zero crossing detector 30 may optionally have an overflow detection feature that determines when the charge in capacitors C S1 and C I1 is outside the normal range of operation. It can be implemented by a logic circuit that makes the output v zc of the zero-crossing detector 30 to go low when ⁇ 2 goes low. In the event v 1 fails to cross zero, the sample is taken on the falling edge of ⁇ 2 . At the same time, the logic circuit produces a flag indicating overflow.
- a zero crossing detector is utilized in lieu of a comparator.
- a comparator is designed to compare two arbitrary input voltages.
- a comparator may be implemented as cascaded amplifiers, a regenerative latch, or a combination of both.
- a comparator may be used to detect a zero voltage level or a predetermined voltage level crossing.
- the input waveform of the various described embodiments is not arbitrary, but deterministic and repetitive.
- the various described embodiments determine the instant the zero voltage level or the predetermined voltage level is crossed than relative amplitudes of the input signals. For such a deterministic input, a zero crossing detector is more efficient.
- FIG. 1 An example of a zero-crossing detector for the detection of a positive-going input signal is shown in FIG. 1 .
- node 1 and node 2 are precharged to V DD and ground, respectively.
- the ramp input voltage V IN is applied according to the zero crossing circuit.
- node 1 is discharged rapidly, and node 2 is pulled up to V DD .
- the zero crossing detector in FIG. 1 is a dynamic circuit, there is no DC power consumption, allowing extremely low power and fast operation.
- a complementary circuit with a PMOS input transistor can be utilized.
- the non-inverting integrator includes a waveform generator which is a current source 200 .
- a clock phase ⁇ 1 is applied to switches S 11 , S 13 , S 22 , and S 24
- another phase ⁇ 2 is applied to switches S 12 , S 14 , and S 21 .
- a zero crossing detector 30 is used to detect the point of time at which Node 100 crosses ground.
- the switch S 23 is controlled by the output of the zero crossing detector 30 .
- the output of the zero crossing detector 30 is used to determine the time point to take the sample of the output voltage V out .
- the current source 200 charges the capacitors C S2 and the series connected C S1 and C I1 , generating a ramp.
- the output is briefly shorted to a known voltage V NEG , the value of which is chosen to ensure the voltage v 1 at Node 100 crosses zero with signals in the normal operating range.
- the non-inverting integrator includes a waveform generator 20 that produces, preferably, a plurality of segments in the waveform with varying rate of change of the output voltage.
- the first segment may be controlled so as to have the highest rate of change, with subsequent segments having progressively lower rate of change.
- the detection of zero crossing by the zero crossing detector 30 causes the waveform to advance to the next segment.
- An output signal v zc2 of the zero crossing detector 30 remains high until the zero crossing is detected in the last segment of the waveform.
- FIG. 8 One clock cycle of the timing diagram is shown in FIG. 8 .
- the waveform generator 20 produces an up ramp.
- the voltage v 1 is shown to cross zero at time t 1 .
- One output, v zc1 , of the zero crossing detector 30 changes its state after a finite delay t d1 .
- the delay t d1 represents finite delay of a typical zero crossing detector 30 . This change of state advances the waveform to the next segment.
- the voltage v 1 overshoots by a small amount above ground.
- the second segment of the waveform generator is a down ramp to permit another zero crossing at time t 2 .
- the output v zc2 of the zero crossing detector 30 goes low, causing the switch S 23 to turn OFF, locking the sample of the output voltage v out .
- the delay t d2 of the second zero crossing is not necessarily the same as the delay associated with the first zero crossing t d1 .
- the delay t d2 contributes a small overshoot to the sampled output voltage.
- the effect of the overshoot can be shown to be constant offset in the sampled charge. In most sampled-data circuits, such constant offset is of little issue.
- the zero crossing detector 30 preferably becomes more accurate in detecting the zero crossing as the segments of the waveform advances.
- the first detection being a coarse detection, it does not have to be very accurate. Therefore, the detection can be made faster with less accuracy.
- the last zero crossing detection in a given cycle determines the accuracy of the output voltage. For this reason, the last zero crossing detection must be the most accurate.
- the accuracy, speed, and the power consumption can be appropriately traded among progressive zero crossing detections for the optimum overall performance.
- the first detection is made less accurately and noisier but is made faster (shorter delay) and lower power.
- the last detection is made more accurately and quieter while consuming more power or being slower (longer delay).
- FIG. 9 An example of a two-segment waveform generator constructed of two current sources ( 210 and 220 ) is shown in FIG. 9 .
- a clock phase ⁇ 1 is applied to switches S 11 , S 13 , S 22 , and S 24
- another phase ⁇ 2 is applied to switches S 12 , S 14 , and S 21 .
- a zero crossing detector 30 is used to detect the point of time at which Node 100 crosses ground.
- the switch S 23 is controlled by the output of the zero crossing detector 30 .
- the output of the zero crossing detector 30 is used to determine the time point to take the sample of the output voltage v out .
- Current sources 210 and 220 charge the capacitors C S2 and the series connected C S1 and C I1 generating two segments of a ramp waveform.
- the output is briefly shorted to a known voltage V NEG , the value of which is chosen to ensure the voltage v 1 crosses zero with signals in the normal operating range.
- V NEG a known voltage
- the non-inverting integrator includes a level crossing detector 300 having plurality of thresholds.
- a clock phase ⁇ 1 is applied to switches S 11 , S 13 , S 22 , and S 24
- another phase ⁇ 2 is applied to switches S 12 , S 14 , and S 21 .
- a level crossing detector 300 is used to detect the point of time at which Node 100 crosses one of plurality of predetermined levels as discussed below.
- the switch S 23 is controlled by the output of the level crossing detector 300 .
- the output of the level crossing detector 300 is used to determine the time point to take the sample of the output voltage v out .
- the thresholds are predetermined voltage levels.
- the thresholds of the level crossing detector 300 can be adjusted to minimize overshoot.
- the threshold for the first detection may be made negative by a slightly smaller amount than the expected overshoot in the first segment. This minimizes the ramp-down time in the second segment.
- the threshold for the second segment may be made more positive by the amount of the overshoot in the second segment in order to cancel the effect of the overshoot.
- the threshold for the first segment may be made more negative than the expected overshoot during the first segment. This permits the second segment to be a positive ramp rather than a negative ramp as shown in FIG. 11 .
- the accuracy of the detection during the last segment is made higher than during other segments. This can be achieved by making the delay longer or making the power consumption higher during the last segment.
- the non-inverting integrator includes a level crossing detector having two zero-crossing detectors, Zero Crossing Detector 1 ( 310 ) and Zero Crossing Detector 2 ( 320 ).
- a clock phase ⁇ 1 is applied to switches S 11 , S 13 , S 22 , and S 24
- another phase ⁇ 2 is applied to switches S 12 , S 14 , and S 21 .
- Zero Crossing Detector 1 ( 310 ) and Zero Crossing Detector 2 ( 320 ) are used to detect the point of time at which Node 100 crosses one of plurality of predetermined levels as discussed below.
- the switch S 23 is controlled by the output of the Zero Crossing Detector 2 ( 320 ).
- the output of the Zero Crossing Detector 2 ( 320 ) is used to determine the time point to take the sample of the output voltage v out .
- the thresholds of the Zero Crossing Detector 1 ( 310 ) and Zero Crossing Detector 2 ( 320 ) are selected to minimize overshoot.
- the threshold for Zero Crossing Detector 1 ( 310 ) may be made negative by a slightly smaller amount than the expected overshoot in the first segment. This minimizes the ramp-down time in the second segment.
- the threshold for Zero Crossing Detector 2 ( 320 ) may be made more positive by the amount of the overshoot in the second segment in order to cancel the effect of the overshoot.
- the threshold for Zero Crossing Detector 1 ( 310 ) may be made more negative than the expected overshoot during the first segment. This permits Zero Crossing Detector 2 ( 320 ) to be appositive ramp rather than a negative ramp.
- Zero Crossing Detector 1 ( 310 ) makes a coarse detection
- Zero Crossing Detector 2 ( 320 ) makes a fine detection.
- the non-inverting integrator includes a level 5 crossing detector having two zero-crossing detectors, Zero Crossing Detector 1 ( 310 ) and Zero Crossing Detector 2 ( 320 ).
- a clock phase ⁇ 1 is applied to switches S 11 , S 13 , S 22 , and S 24
- another phase ⁇ 2 is applied to switches S 12 , S 14 , and S 21 .
- Zero Crossing Detector 1 ( 310 ) and Zero Crossing Detector 2 ( 320 ) are used to detect the point of time at which Node 100 crosses one of plurality of predetermined levels as discussed below.
- the switch S 23 is controlled by the output of the Zero Crossing Detector 2 ( 320 ).
- the output of the Zero Crossing Detector 2 ( 320 ) is used to determine the time point to take the sample of the output voltage v out .
- the detection thresholds are determined by voltages V tr1 and V tr2 applied to the inputs of Zero Crossing Detector 1 ( 310 ) and Zero Crossing Detector 2 ( 320 ), respectively.
- Zero Crossing Detector 1 ( 310 ) makes a coarse detection
- Zero Crossing Detector 2 ( 320 ) makes a fine detection.
- FIG. 14 illustrates a self-timed operation.
- the end of the phase ⁇ 2 is defined by the output of the detection during the last segment.
- the beginning of the clock phase ⁇ 1 is defined by a short delay, such as logic delays, after the end of ⁇ 2 .
- the short delay is generally necessary to ensure non-overlapping clock phases.
- the end of the clock phase ⁇ 1 is determined by the zero crossing detection of the previous stage or the following stage in the similar manner.
- zero crossing detectors can be applied in other switched-capacitor circuits such as algorithmic and pipeline analog-to-digital converters, delta-sigma converters, and amplifiers.
- FIG. 15 A pipeline analog-to-digital converter is shown in FIG. 15 in which the first two stages of the pipeline are shown. As in the switched-capacitor integrator in FIG. 2 , the pipeline converter operates in two phases as in the switched-capacitor integrator in FIG. 2 .
- first stage capacitors C 11 -C 14 are connected to either ground, V in , V REF , or ⁇ V REF through switches S 11 -S 14 , respectively. It is noted that only first stage capacitor C 11 can be connected to ground.
- Each first stage capacitor (C 11 -C 14 ) is connected to the inverted input of amplifier 410 .
- the output V out ( 1 ) of amplifier 410 is feedback to the inverted input of amplifier 410 through switch S 16 and capacitor C 15 . It is noted that the inverted input of amplifier 410 may also be connected to ground through switch S 15 .
- second stage capacitors C 21 -C 24 are connected to either ground, V out ( 1 ), V REF , or ⁇ V REF through switches S 21 -S 24 , respectively. It is noted that only second stage capacitor C 21 can be connected to ground.
- Each second stage capacitor (C 21 -C 24 ) is connected to the inverted input of amplifier 420 .
- the output V out ( 2 ) of amplifier 420 is feedback to the inverted input of amplifier 420 through switch S 26 and capacitor C 25 . It is noted that the inverted input of amplifier 420 may also be connected to ground through switch S 25 .
- the sampling phase the input voltage is sampled on the first stage capacitors C 11 -C 14 , as shown in FIG. 16 .
- the input voltage is compared with ⁇ 1 ⁇ 2V REF , 0, and 1 ⁇ 2V REF .
- the charge in C 11 -C 14 is transferred to the feedback capacitor C 15 as shown in FIG. 17 .
- the first stage capacitors C 11 -C 13 are connected to either V REF or ⁇ V REF .
- the output voltage of the first stage is also sampled by the second stage capacitors C 21 -C 24 in the second phase, the transfer phase, of the first stage.
- the transfer phase of the first stage coincides with the sampling phase of the second stage.
- the operational amplifier 410 must force the voltage at Node 101 to virtual ground in order for the output voltage to be accurate. As in other sampled-data analog circuits, forcing of virtual ground by an operational amplifier is power intensive.
- a pipeline converter based on zero-crossing detectors can be substantially more efficient in power consumption and area compared with conventional approaches based on operational amplifiers as illustrated in FIGS. 15-17 .
- An embodiment of a pipeline converter based on zero crossing detection provided by the invention is shown in FIG. 18 . Only the first two stages of pipeline are shown for clarity.
- first stage capacitors C 11 -C 14 are connected to either ground, V in , V REF , or ⁇ V REF through switches S 11 -S 14 , respectively. It is noted that only first stage capacitor C 11 can be connected to ground.
- Each first stage capacitor (C 11 -C 14 ) is connected to one input terminal of a zero crossing detector 510 .
- the output V out ( 1 ) of the zero crossing detector 510 controls activation of switch S 25 .
- a ramp generator 610 is connected to the one input terminal of the zero crossing detector 510 through switch S 16 and capacitor C 15 . It is noted that the one input terminal of the zero crossing detector 510 may also be connected to ground through switch S 15 . It is further noted that capacitor C 15 may also be connected to ground through switch S 16 .
- second stage capacitors C 21 -C 24 are connected to either ground, V REF , or ⁇ V REF through switches S 21 -S 24 , respectively. It is noted that only first stage capacitor C 21 can be connected to ground.
- Each second stage capacitor (C 21 -C 24 ) is connected to one input terminal of a second zero crossing detector 520 .
- the ramp generator 610 is connected to the one input terminal of the second zero crossing detector 520 through switch S 26 and capacitor C 25 . It is noted that the one input terminal of the second zero crossing detector 520 may also be connected to ground through switch S 25 . It is further noted that capacitor C 25 may also be connected to ground through switch S 26 .
- the pipeline converter in FIG. 18 operates in two phases.
- the first phase is schematically shown in FIG. 19 .
- switches are omitted, and only the voltages applied through the omitted switches are indicated.
- the operation is performed in two phases.
- the sampling phase the input voltage is sampled on the first stage capacitors C 11 -C 14 , as shown in FIG. 19 .
- the input voltage is compared with ⁇ 1 ⁇ 2V REF , 0, and 1 ⁇ 2V REF .
- the transfer phase the charge in C 11 -C 14 is transferred to the feedback capacitor C 15 as shown in FIG. 20 .
- the first stage capacitors C 11 -C 13 are connected to either V REF or ⁇ V REF .
- the ramp waveform generator 610 sweeps the output voltage V out ( 1 ) up and then down, causing the input voltage of the zero crossing detector 510 to cross the ground potential or the common-mode voltage.
- the output status of the zero crossing detector 510 changes, and the sampling switch S 25 of second stage is turned OFF. This locks the accurate voltage on the second stage capacitors C 21 -C 24 because the sampling switch is turned OFF at the time the input voltage of the zero crossing detector 510 is at or near the virtual ground.
- the reference voltages are generally applied during the transfer phase as explained in the preceding description. Depending on the function implemented, however, the reference voltages may be applied during the sampling phase. For example, many delta-sigma converters may apply the reference voltages during the sampling phase.
- FIG. 21 illustrates an example of a delta-sigma converter.
- a capacitor C S1 is charged by voltage source V in through the operations of switches S 11 -S 14 . Also, a capacitor C REF is charged by voltage source V ref through the operations of switches S 31 -S 34 .
- the input voltage V in is sampled by capacitor C S1 during the sampling phase.
- the reference voltage V REF is sampled by capacitor C ref during the same phase.
- the charge in both capacitors C S1 and C ref is transferred to capacitor C I1 during the transfer phase.
- the reference voltages V REF and ⁇ V REF can be generated from bandgap reference circuits and are driven by operational amplifiers.
- An example bandgap reference circuit is shown in FIG. 22 .
- a first bias voltage, the base-emitter voltage of Q 1 is applied to the input of an operational amplifier 410 .
- a second bias voltage, the base-emitter voltage of Q 2 is also applied to a non-inverting input of the amplifier 410 through a resistor R 2 . It is noted that the output voltage of the amplifier 410 is closely related to the bandgap voltage, which is substantially independent of operating temperature.
- the reference voltages Unless large bypass capacitors are used on the reference voltages, it is generally required that the reference voltage settle to an accurate value within the half clock period. In addition, the reference voltages must present low noise, preferably lower than 1 ⁇ 2 LSB at the intended resolution of the A/D converter.
- the power consumed in the reference voltage circuits can be a substantial portion of overall power consumption A/D converters.
- voltage sources similar to reference voltage sources may be applied for level shifting or other purposes. If similar op-amp based voltage source circuits are employed in zero-crossing detector based circuits, the power consumption of the reference circuit may be overwhelming because the zero-crossing detector based circuits consume little power.
- the invention provides configurations for applying voltage sources, such as reference voltages, in zero-crossing detector based circuits in a manner that reduces the power consumption required in such voltage sources without degrading noise performance or speed of zero-crossing based circuits.
- FIG. 23 An example of a first stage integrator of a zero-crossing detector based delta-sigma converter is illustrated in FIG. 23 .
- the reference voltage is sampled during the sampling phase of switched-capacitor circuits.
- a first zero-crossing detector ZCD 1 controls the sampling instant of the next stage integrator.
- a first waveform generator is shown as a variable current source I charging capacitor C I1 .
- a second zero-crossing detector ZCD 2 controls the sampling of the reference voltage on sampling capacitor C REF .
- the input voltage V in is sampled by capacitor C S1 by turning switches S 11 and S 13 ON, as described with respect to the integrator stage of FIG. 21 .
- a second waveform generator shown as a variable current source I REF charging capacitor C REF , produces a waveform, for example the two-segment ramp Illustrated in FIG. 7 .
- the output voltage V 2 is compared with the reference voltage V REF by second zero-crossing detector ZCD 2 .
- the first time V 2 crosses V REF the second waveform generator advances its output to the next segment by changing the current I REF .
- the second segment is preferably a ramp with a slower rate of change than the first segment.
- second zero-crossing detector ZCD 2 turns S R3 OFF.
- the voltage sampled on capacitor C REF is equal to V REF except a small amount of error caused by the undershoot due to the finite delay of second zero-crossing detector ZCD 2 .
- both the input voltage V in sampled on capacitor C S1 and the reference voltage V REF is sampled on capacitor C REF are transferred to the integrating capacitor C I1 .
- Switches S 12 , S 14 , S R2 , S R4 , S 21 , and S 23 are closed.
- Switch S 15 is briefly turned ON to precharge V out .
- the output voltage V out begins to rise when switch S 15 is turned OFF.
- first zero-crossing detector ZCD 1 turns switch S 23 OFF, then turns switch S 21 OFF. Transferring the charge from capacitor C S1 and capacitor C REF1 to capacitor C I1 and sampling of the output voltage to capacitor C S2 is complete at this point.
- capacitors C REF1 and C REF2 sample the reference voltage.
- Second zero-crossing detector ZCD 2 turns switches S R13 and S R23 OFF to sample the reference voltage in the same manner as in the circuit of FIG. 23 .
- V REF only sees the input capacitance of second zero-crossing detector ZCD 2 , the design of the reference voltage source is greatly simplified.
- the reference source must drive the reference sampling capacitor directly. Therefore, the reference source typically uses an operational amplifier.
- the operational amplifiers can be omitted because the loading on the reference voltage source is very small.
- the reference voltage source is allowed to have much higher noise spectral density compared with prior art reference sampling circuit.
- the small load and higher noise spectral density save substantial power from the reference circuit.
- switched-capacitor circuits are implemented in a fully-differential configuration.
- the various embodiments described above can be implemented in fully-differential configuration.
- a fully-differential version of the first embodiment is shown in FIG. 25 , where only the reference sampling circuit is shown for clarity.
- the input voltages are applied differentially (not shown).
- Two reference voltages V REFP and V REFN are sampled on capacitors C REFP and C REFN , respectively, during the sampling phase.
- the zero-crossing detectors ZCD 2 and ZCD 3 control the sampling of V REFP and V REFN by controlling the state of switches S RP3 and S RN3 .
- switches S RP2 and S RN2 are closed.
- switches S RP5 and S RN5 are closed. If reference addition is desired, on the other hand, switches S RP4 and S RN4 are closed instead.
- the first zero-crossing detector ZCD 1 controls the operation of the first stage integrator and the sampling of its result by the second stage sampling capacitors, as in the first embodiment.
- FIG. 26 A further embodiment of this configuration is shown in FIG. 26 .
- voltage V in is sampled on C S1 during the sampling phase.
- Voltage V REF is sampled on capacitor C REF during the sampling phase also, as follows. First, switches S R1 and S R3 are closed for a short period of time to sample the approximate value of voltage V REF , preferably slightly lower than voltage V REF on capacitor C REF . Since only the approximate value needs to be sampled, the voltage on capacitor C REF does not need to settle to an accurate value.
- switch S R3 is turned OFF. Using a negative value for I REF , the voltage V 2 at Node 2 is ramped down. When voltage V 2 crosses zero, second zero-crossing detector ZCD 2 turns switch S R1 OFF.
- the voltage sampled on capacitor C REF is shown to be voltage V REF plus a small undershoot due to the finite delay of first zero-crossing detector ZCD 1 .
- FIG. 27 provides a bandgap 20 based discrete-time reference voltage.
- the first bias voltage, the base-emitter voltage of transistor Q 2 is sampled on capacitor C 2 by turning switches S 21 and S 23 ON with switch S 12 ON.
- the charge is transferred to the feedback capacitor C FB and the second bias voltage, the base-emitter voltage of transistor Q 1 , is applied by turning switches S 11 , S 21 , and S 24 ON.
- the output voltage sampled by capacitor C REF when the zero crossing is detected by zero-crossing detector ZCD.
- the current I REF is changed in the similar manner as in zero-crossing detector ZCD based sampled-data circuits.
- voltage V out is shown to be a constant multiple of bandgap referenced voltage.
- FIG. 28 A further embodiment is shown in FIG. 28 .
- This circuit is based on the bandgap reference voltage source in FIG. 22 .
- the instant voltage V 1 crosses voltage V 2 is detected by zero-crossing detector ZCD in a similar manner as in zero-crossing detector ZCD based sampled-data circuits.
- the current I REF is changed in the similar manner, for example to produce multiple segments of a ramp waveform, as in zero-crossing detector ZCD based sampled-data circuits.
- the output voltage V out at the time voltage V 1 crosses voltage V 2 is very close to the bandgap reference voltage source in FIG. 22 .
- the zero-crossing detector ZCD turns the sampling switch S R3 OFF locking an accurate voltage on capacitor C REF .
- the reference voltage source In circuits where the reference voltage is applied during the transfer phase, the reference voltage source must provide an accurate voltage at the instant the sampling switch of the next stage is turned OFF. This generally requires the reference voltage source to be an amplifier-driven source such as the one shown in FIG. 22 . When a bandgap reference source is employed in a zero-crossing detector ZCD based sampled-data circuit, the reference source must settle fast, requiring wide bandwidth. But in the embodiment of FIG. 28 , the amplifier in the reference source may be designed differently because the noise bandwidth is not determined by the reference source but by the zero-crossing detector ZCD.
- an operational amplifier 410 is preceded by a low-to-moderate gain preamplifier (M 1 , M 2 , M 3 , and R). In this configuration, the operational amplifier 410 increases bandwidth without significant increase in power consumption.
- an operational transconductance amplifier with gain in the current mirror is employed.
- FIG. 31 shows another embodiment of the present invention based upon the bandgap reference circuit in FIG. 22 , but the function of the operational amplifier 410 is replaced by a zero-crossing detector ZCD.
- a ramp generator consisting of a current source I REF and a capacitor C REF is connected to the zero-crossing detector ZCD.
- the instant voltage V 1 crosses voltage V 2 is detected by zero-crossing detector ZCD in a similar manner as in zero-crossing detector ZCD based sampled-data circuits.
- the current I REF is changed in the similar manner as in zero-crossing detector ZCD based sampled-data circuits.
- the output voltage, V out at the time voltage V 1
- the amplifier 410 can be, for example, a simple source-follower circuit.
- FIG. 32 Another embodiment according to the present invention is shown in FIG. 32 .
- This embodiment is based on the discrete-time bandgap reference circuit of FIG. 27 , but further includes the output holding capability of the circuit in FIG. 31 .
- the base-emitter voltage of transistor Q 2 is sampled on capacitor C 2 by turning switches S 21 and S 23 ON with switch S 12 ON.
- the charge is transferred to the feedback capacitor C FB , by turning switches S 11 , S 21 , and S 24 ON.
- the zero crossing is detected by zero-crossing detector ZCD.
- the current I REF is changed in the similar manner as in zero-crossing detector ZCD based sampled-data circuits.
- voltage V out is shown to be a constant multiple of a bandgap referenced voltage.
- the voltage that is required to produce the desired output voltage V out is held across the capacitor C REF , such that an accurate output voltage is available for an extended period of time.
- the amplifier 410 can be, for example, a simple source-follower circuit.
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US11/617,228 US7522086B2 (en) | 2005-12-29 | 2006-12-28 | Reference circuits for sampled-data circuits |
PCT/US2006/049563 WO2007079216A2 (en) | 2005-12-29 | 2006-12-29 | Reference circuits for sampled-data circuits |
US12/178,044 US7616145B2 (en) | 2005-12-29 | 2008-07-23 | Reference circuits for sampled-data circuits |
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US11/617,228 US7522086B2 (en) | 2005-12-29 | 2006-12-28 | Reference circuits for sampled-data circuits |
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Cited By (3)
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US7671776B1 (en) * | 2007-06-18 | 2010-03-02 | Intersil Americas Inc. | Input sampling network that avoids undesired transient voltages |
US20120025893A1 (en) * | 2010-07-30 | 2012-02-02 | On Semiconductor Trading, Ltd. | Switched capacitor circuit |
US8432192B2 (en) * | 2011-05-20 | 2013-04-30 | Maxim Integrated Products, Inc. | 2-phase threshold detector based circuits |
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JP4970224B2 (en) * | 2007-11-30 | 2012-07-04 | ルネサスエレクトロニクス株式会社 | Semiconductor integrated circuit |
US7936291B2 (en) * | 2008-10-10 | 2011-05-03 | Robert Bosch Gmbh | System and method for removing nonlinearities and cancelling offset errors in comparator based/zero crossing based switched capacitor circuits |
WO2012129163A2 (en) * | 2011-03-18 | 2012-09-27 | The Trustees Of Columbia University In The City Of New York | Systems and methods for providing a pipelined anal og-to-digital converter |
CN115016589B (en) * | 2022-06-01 | 2023-11-10 | 南京英锐创电子科技有限公司 | Band gap reference circuit |
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Also Published As
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US7616145B2 (en) | 2009-11-10 |
WO2007079216A2 (en) | 2007-07-12 |
WO2007079216A3 (en) | 2008-07-10 |
US20080278358A1 (en) | 2008-11-13 |
US20070164889A1 (en) | 2007-07-19 |
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