GB2245464A

GB2245464A - Reducing interference due to processing of teletext signals

Info

Publication number: GB2245464A
Application number: GB9112462A
Authority: GB
Inventors: John Michael Rowe
Original assignee: Ferguson Ltd
Current assignee: Thomson Multimedia Sales UK Ltd
Priority date: 1990-06-15
Filing date: 1991-06-07
Publication date: 1992-01-02
Also published as: KR920001959A; DE69124845T2; ES2100903T3; EP0461551B1; KR0178398B1; GB9013434D0; EP0461551A2; DE69124845D1; EP0461551A3; ATE149771T1; GB9112462D0; JPH05122665A

Abstract

A digital teletext signal is transmitted during part of a vertical blanking period of a television signal. A clock oscillator synchronized by the teletext signal is coupled to a synchronizing input of a logic circuit providing clock and data signals for teletext processing. To prevent high harmonics that are included in the clock and data signals from producing interference within the reproduced picture, the amplitude of an output signal of the clock oscillator is reduced, during vertical trace, when the teletext signal is not transmitted to prevent switching operations in the logic circuit.

Description

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TELEVISION DEVICE WITH PROCESSING OF TELETEXT SIGNALS The present invention relates to television receivers with processing of teletext signals transmitted during a teletext working period of several lines within the vertical blanking period.

Within a television system including additional transmission of teletext signals there is transmitted during one or more of the lines of the vertical flyback period a digital teletext signal which in the receiver is decoded for producing additional control signals for the picture tu>e for teletext display. Such teletext processing circuits include a sine wave clock oscillator synchronized by the teletext signal. Said oscillator produces a substantially sine wave clock signal which is fed to the synchronizing or triggering is input of a logic circuit. Said logic circuit produces one or more clock and data signals used for teletext signal processing.

The output signal of said clock oscillator is substantially a sine wave and has substantially no harmonics. The signal does not cause significant interference within the reproduced picture.

The output signals of the logic circuit, however, are very fast signals especially in connection with miniaturisized circuit elements. That means that these signals include high harmonics of substantial amplitude. Said hiuh harmonics tend to cause interferences within the reproduced picture. If for example the frequency of the clock oscillator is 55 MHz than the 10th harmonic within the clock and data signal,with 550 MHz lies within the UHFband.

It is an object of the present invention to avoid said interferences within the reproduced picture due to high harmonics within the clock and data signal furnished by said logic circuit.

According to the invention means are provided - 2 for reducing the amplitude of the synchronizing signal fed to the logic circuit during the time outside said working period to such an amount that said logic circuit does not work.

The invention bases upon the following consideration. The clock and fast data signal is needed for handling and processing the teletext signal. On the other hand said teletext signal is only present-during one or more lines of the vertical blanking period. That means that said clock and data signal is not needed at any other time, especially during the full vertical forward scan period. Therefore, it is possible to disable said logic circuit outside said working period in order to avoid said interference. On the other hand during is said working period the clock and data signal are needed and therefore cannot produce interferences because during said time no picture is produced because of vertical flyback and blanking. By switching off the said logic circuit outside the said working period, therefore, said interference is avoided in a very simple manner.

There are different methods for ensuring that the said logic circuit does not work outside said working period.

According to one embodiment of the invention a switch is provided between the output of the clock oscillator and the trigger input of the logic circuit. Said switch is closed only during said working period and opened during the other time. Said switch thus disconnects the synchronizing or triggering signal from said logic circuit during vertical forward scan period so that the logic circuit does not work.

In another form of the invention the synchronizing signal is not switched off from the logic circuit but only reduced in amplitude to such an amount I.

that it cannot trigger the logic circuit. This may be achieved by a special circuit attenuating the said substantially sine wave clock signal produced by the clock oscillator. In another form of the invention the clock oscillator is completely stopped, for instance by applying a special gate pulse to an input of the oscillator and is therefore prevented from radiating.

Preferably the on-time of the logic circuit is slightly longer than the said working period during which the teletext signal is available. This is useful for taking into account transients and delays wIthin the signals.

In order that the invention may more readily be understood a description is now given by way of example only, reference being made to the drawing. Within the drawing Figure 1 shows waveforms for illustrating the operation of the invention, Figure 2 shows a block diagram illustrating the relationship between the clock oscillator and the logic circu-Lt, Figure 3 shows a circuit for reducing the amplitude of the output signal of the clock oscillator and Figure 4 shows a diagram for illustrating the operation of the circuit according to Figure 3.

Figure 1 shows the television synchronizing signal S during vertical flyback including the field synchronizing pulses F, the equalizing pulses E and the line sync pulses Z. During one or more lines forming the working period WP a digital teletext signal TS is transmitted. A text window signal W is produced by evaluating field sync pulses F and counting the lines. Said window signal W occurs during a period T being some lines longer than the working period WP. From the window signal W a gate pulse G is derived during 1 - 4 period T. This gate pulse G is used for switching on the clock oscillator producing a clock signal C. Outside period T the gate pulse G switches off the clock oscillator or reduces it's output amplitude so that the logic circuit synchronized thereby cannot work.

In Figure 2 the output of the clock oscillator 1 synchronized by teletext signal TS is connected via switch S to the synchronizing or trigger input of logic circuit 2. Logic circuit 2 produces one or more clock and fast data signals 3,4 having very high harmonics. Switch S is closed by gate pulse G only during period T so that the clock and data signals 3, 4 for processing the teletext signal are produced. Outside the period T, that means especially during the complete vertical scan period switch S is opened. Clock signal C at the output of clock oscillator 1 does not reach the trigger input of logic circuit 2. Therefore, logic circuit 2 cannot work and consequently the clock and data signals 3,4 are not produced so that interferences caused by the said high harmonics cannot arise during the reproduced picture.

Figure 3 shows a circuit external to the oscillator 1 adapted for reducing the amplitude of clock signal C. Window signal W is rectified by diode D1 and capacitor Cl for producing gate pulse G. During high level of gate pulse G transistor Tl and diode D2 are turned on whereas diode D3 is turned off. During this time the circuit effects no attenuation of the oscillator 1 at pins 5,6 so that oscillator oscillates at full amplitude. During low level of gate pulse G transistor Tl and diode D2 are turned off whereas diode D3 is turned on. Now the oscillator is attenuated and the amplitude of reproduced clock signal C is reduced to an amount that logic circuit 2 is no longer triggered.

zt A Figure 4 shows the amplitude of clock signal C during period T and outside said period. Us designates the trigger level of logic circuit 2. During period T the clock signal C can trigger the logic circuit 2.

Outside period T, however, the clock signal C does not reach trigger level Us so that logic circuit 2 is not triggered, and does not produce the clock and data signals 3,4.

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Claims

1. Television device with processing of teletext signals transmitted during a teletext working period of one of more lines within the vertical blanking period, including a clock oscillator synchronizing a logic circuit generating clock and data teletext signals, characterized by means for reducing the amplitude of the synchronizing signal fed to the logic circuit during the time outside said working period to such an amount that said logic circuit does not work.

2. Device according to Claim 1, characterized in that a switch is provided for switching off the synchronizing signal at the input of said logic cir cuit.

3. Device according to Claim 1, characterized in is that the amplitude of the synchronizing signal is re duced to an amount insufficient to trigger said logic circuit.

4. Device according to Claim 1, characterized in that said oscillator is stopped from oscillating outside said working period.

5. Device according to Claim 1, characterized in that the on-time of the logic circuit is by one or more television lines longer than said working period.

6. Device as described within the specification and the drawing.

Published 1991 at The Patent Office. Concept House, Cardiff Road, Newport. Gwent NP9 I RH. Further copies may be obtained from Sales Branch, Unit 6, Nine Mile Point. Cwnifelinfach. Cmss Keys. Newport. NPI. 7HZ. Printed by Multiplex techniques lid, St Mary Cray. Kent.

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