GB2243734A - Multichannel tracking A/D conversion - Google Patents

Abstract

Digital representations of the current values of a plurality of analog voltages applied to respective inputs (71, .... 7N) are maintained in respective digital data storage locations (221, .... 22N) by repeatedly scanning the inputs by means of a multiplexer (1) and addressing the corresponding storage locations in step with the scans. Each time a given input is scanned the difference between the relevant input voltage and the corresponding representation converted to analog form by means of a D/A converter (6) is averaged over a time T by means of a common analog intergrator circuit (2) and the result is converted to digital form by means of a comparator (4) and used to correct (if necessary) the contents of the relevant storage location. <IMAGE>

Description

DESCRIPTION MULTICHANNEL TRACKING AID CONVERSION This invention relates to a method of multichannel tracking analog-to-digital (A/D) conversion, in which digital representations of the current values of a plurality of analog voltages are maintained in respective digital data storage locations, the voltages being repeatedly scanned in a multiplexed manner and the respective representations being updated in accordance with any changes which occur in the corresponding voltages from scan to scan. The invention also relates to a multichannel tracking analog-to-digital conversion arrangement for implementing such a method.

In a known such method, each time each voltage is scanned by means of an input multiplexer the value thereof is converted to digital form and this is then directly substituted for the current contents of the corresponding storage location.

It is often desirable that each of the various analog voltages be subjected to some form of filtering process, for example to reduce the noise bandwidth and suppress interference, prior to it being used to update the contents of the corresponding storage location. This filtering process may take the form of an averaging process performed by means of an analog integrator circuit and, to this end, a respective such integrator circuit may be provided at each input of the input multiplexer. Obviously in such a case the larger the number of input voltages is the larger will be the number of integrator circuits required, which can lead to both high costs and reduced reliability. It is an object of the present invention to alleviate this problem.

According to one aspect the invention provides a method as set forth in the first paragraph which is characterized in that, when each voltage is scanned, any difference between it and the current contents of the corresponding storage location converted to analog form is averaged over a finite time by means of a common analog integrator circuit and the relevant current contents are corrected (if necessary) in accordance with the result of the averaging process converted to digital form.

It has now been recognized that, when the above-described filtering process is required, it is not necessary to provide a respective integrator circuit corresponding to each input voltage; provided that certain steps are taken a single such circuit may be effectively shared between all the input voltages. It is not in general possible to effect such sharing if each input voltage is converted to digital form and this is then directly substituted for the current contents of the corresponding storage location as in the prior art method referred to in the preamble, because if this were the case the integrator circuit output voltage would take a considerable time (several times its RC time constant) to reach the required value each time the next input voltage is scanned.Thus the scan rate would have to take this fact into account, which in many cases, particularly when the number of analog input voltages is large, would result in an impermissibly low scan rate. By averaging the difference between each input voltage and the analog-converted current contents of the corresponding storage location (which quantities will be nearly the same if the input voltages are only slowly varying) and using the results to merely addlsubtract a correction tolfrom the relevant current contents, the number of bits required to represent the integrator circuit output voltage, and hence the resolution required of the integrator output voltage, can be considerably reduced. Indeed in many cases single-bit resolution (indicating merely the sign of the averaged difference) will suffice.Thus in such a case each conversion of the result of the averaging process to digital form may be effected by means of a common digital-to-analog converter in the form of a comparator, the current contents of each storage location being simply incremented or decremented each time in response to the value of the comparator output signal. This incrementationldecrementation will obviously normally be by a unit amount, i.e. by an amount corresponding to a single change in the least significant bit of the digital representation of the value of the corresponding analog voltage.However, if this is always the case the response of the representation to a relatively large change in the corresponding analog voltage may be impermissibly slow in some applications; a large number of scans of the relevant analog voltage may be required before the digital representation becomes an accurate indication of its new value. This problem can be alleviated if for each analog voltage a respective record is kept of the number of immediately preceding scans thereof which have resulted in correction to the contents of the corresponding storage location in the same sense and, if when a said analog voltage is scanned the relevant number has at least a predetermined value and any correction currently required has the relevant sense, the correction made is by an amount greater than unity, any correction made otherwise being by a unit amount.

Preferably each of the aforesaid results is taken after the relevant averaging process has been terminated. This can prevent noise etc. from being present in the integrator circuit output voltage while the conversion process is taking place, which noise might otherwise introduce uncertainty in the quantity being converted.

Preferably the output signal of the integrator circuit is zeroed before each averaging process, i.e. each said finite time, commences. This can substantially reduce or eliminate cross-talk which might otherwise occur between the contents of the various storage locations due to voltages being stored in the integrator circuit from the scanning of one analog voltage to the next.

According to another aspect the invention provides a multichannel tracking analog-to-digital conversion arrangement for implementing a method as set forth hereinbefore, comprising a multiplexer having a respective input for each of the analog voltages and an output, storage means comprising a respective digital data storage location corresponding to each of said inputs, digital-to-analog converter means having an input coupled to a data output of said storage means and an output, an analog integrator circuit having inputs coupled to the multiplexer output and to the output of the converter means respectively, for integrating the difference between analog signals present in operation at these outputs, analog-to-digital converter means having an input coupled to an output of said integrator circuit, and control means for said multiplexer and said storage means for controlling the multiplexer to couple its said inputs successively and repeatedly to its output and selecting the corresponding storage locations in step therewith so that each time a said input of the multiplexer is coupled to its output the integrator circuit will average over a finite time the difference between any analog voltage present at the relevant input and the contents of the corresponding said storage location converted to analog form, the analog-to-digital converter means having an output coupled to said storage means for correcting (if necessary) the contents of each selected storage location in accordance with the result of the relevant averaging process.

Embodiments of the invention will now be described, by way of example, with reference to the accompanying diagrammatic drawings, in which Figure 1 is a block diagram of a first embodiment, Figure 2 is a flow diagram of various operations which may be performed by a microcomputer forming part of the embodiment of Figure 1, and Figure 3 shows a possible alternative to part of the flow diagram of Figure 2.

In Figure 1 a multichannel tracking analog-to-digital (AID) converter arrangement comprises a multiplexer 1, an analog integrator circuit 2, two controllable switches 3 and 9, an analog-to-digital converter in the form of a comparator 4, a programmed micrcomputer 5, and a digital-to-analog (D/A) converter 6. (Analog) multiplexer 1 has N analog voltage inputs 71,72,...7N and a single analog voltage output 8 and is controllable to couple respective ones of its inputs 7 to its output 8 by applying a corresponding digital signal to an input 10. The output 8 is connected to the resistance portion 11 of the integrator circuit 2 via the switch 9. Both the switch 3 and the input of the comparator 4 are connected in parallel with the capacitance portion 12 of the integrator circuit 2.The output of comparator 4 is connected to an input 13 of microcomputer 5.

Parallel output ports 14 and 15 of microcomputer 5 are connected to the control input 10 of multiplexer 1 and to the input 16 of D/A converter 6 respectively, the output 17 of converter 6 being connected to the opposite end of integrator capacitance 12 to that which is connected to the integrator resistance 11. Further outputs 18 and 19 of microcomputer 5 are connected to control inputs 20 and 21 of switches 3 and 9 respectively. Microcomputer 5 includes, inter alia, N digital data storage locations 221,222,...22N and a further digital data storage location 23.

The microcomputer 5 is programmed to perform the sequence of operations illustrated in Figure 2, in which the various blocks have the following significances.

24 - Start 25 - Initialise. Open switch 9 by writing an appropriate control signal to output 19.

26 - Set contents n of location 23 to 1. (n:=l).

27 - Close switch 3 by writing an appropriate control signal to output 18.

28 - Control multiplexer 8 to connect input 7n to its output 8 by writing the value n to output 14.

29 - Write the contents of location 22n to output 15 (and hence to D/A converter 6).

30 - Open switch 3 by writing an appropriate control signal to output 18.

31 - Close switch 9 by writing an appropriate control signal to output 19.

32 - Wait for time T.

33 - Open switch 9 by writing an appropriate control signal to output 19.

34 - Is output signal of comparator 4, i.e. the signal at input 13, logic 1? 35 - Decrement contents of storage location 22n 36 - Increment contents of storage location 22n 37 - Is the contents of location 23 equal to N? (n=N?) 38 - Increment the contents of location 23. (n:=n+l).

Thus initially integrator circuit 2 is isolated from all the analog voltage inputs 7 by the open switch 9. Any charge in the integrator capacitance 12 is then short-circuited, i.e. the voltage on capacitor 12 is zeroed, by the closure of switch 3 (step 27) and the multiplexer is set to supply the analog voltage presented to its first input 71 to its output 8 (step 28). The contents of the first storage location 221 are then supplied to D/A converter 6 by means of step 29, these contents converted to analog form in consequence being supplied to the lower electrode of integrator capacitor 12. Switch 3 is then opened (step 30) and switch 9 is closed (step 31), the latter causing the analog voltage presented to input 71 and present at multiplexer output 8 to be connected to the left-hand end of integrator resistor 11.This situation is maintained for a time T (step 32) so that the voltage across integrator capacitor 12 becomes equal to the difference between the analog voltage applied to input 71 and the contents of location 221 converted to analogue form, as averaged over the time T. If after termination of the time T by means of step 33 this voltage is positive (result of test 34 being yes (Y)) indicating that, on average, the voltage at input 71 has been greater than the analog-converted contents of location 221, the contents of location 221 are incremented (step 36). Otherwise the contents of location 221 are decremented (step 35). The value of n is then incremented (step 38) so that the sequence of steps is repeated for the next input 72 together with the next storage location 222, and thereafter for the remaining inputs 7 together with their respective storage locations 22.When input 7N together with storage location 22N has been processed the result of test 37 becomes yes (Y) and the sequence of operations starts again from step 26.

It will be evident that after several such sequences have been performed the contents of locations 221....22N will become accurately representative of the analog voltages applied to the respective inputs 71....7N filtered or averaged by the analog integrator circuit 2, and will thereafter follow any changes in the averaged respective voltages. The speed of response to a change in such a voltage, i.e. the time taken for the contents of the relevant storage location 22 to become accurately representative of the new value, will of course depend on the size of the change and also on the resolution (number of bits) with which it is represented in the relevant location 22.If this resolution is high, for example to twelve or sixteen bits, this response speed might be quite low, -because in the arrangement described so far the representation in the relevant location 22 can only be incremented or decremented by a unit amount, i.e. an amount equivalent to a single change in the least significant bit, each time the relevant input is scanned.If the response speed is in consequence too low for a given application the single-bit AID converter constituted by the comparator 4 of Figure 1 may be replaced by an AID converter having a higher, i.e. plural-bit, resolution the output of which is coupled to an input port of microcomputer 5, steps 34-36 in the flow diagram of Figure 2 then being replaced by the addition of the (appropriately signed) output signal of this A/D converter to the contents of storage location 22n Alternatively the simple comparator 4 may be maintained and the program described with reference to Figure 2 be elaborated to make the amount by which the contents of location 22n are incremented or decremented depend on the immediate past history of such incrementations or decrementations. More particularly the program may be elaborated so that, if all the immediately preceding m processing operations on the contents of a given location 22n have resulted in incrementation of these contents, and the current processing operation of these contents also requires incrementation, this incrementation is by an amount p greater than unity and, if all the immediately preceding m processing operations on the contents of location 22n have resulted in decrementation of these contents, and the current processing operation of these contents also requires decrementation, this decrementation is by an amount p greater than unity.This can be achieved by providing in microcomputer 5 a further pair of storage locations (not shown) corresponding to each location 22, the members of each pair corresponding to incrementation and decrementation respectively of the contents of the relevant location 22. The steps 35 and 36 of Figure 2 may then each be replaced by the sequence of steps illustrated in Figure 3, where the various blocks have the following significances: for the replacement for step 35 40 - reset contents of "increment" location of the relevant pair to zero.

41 - are the contents of the "decrement" location of the relevant pair greater than or equal to m? 42 - decrement contents of location 22n by unity.

43 - decrement contents of location 22n by a given amount p greater than unity.

44 - increment contents of "decrement" location of the relevant pair by unity.

and for the replacement for step 36 40 - reset contents of "decrement" location of the relevant pair to zero.

41 - are the contents of the "increment" location of the relevant pair greater than or equal to m? 42 - increment contents of location 22n by unity.

43 - increment contents of location 22n by a given amount p greater than unity.

44 - increment contents of "increment" location of the relevant pair by unity.

Obviously this technique may be refined still further if desired, to increase the amount by which the contents of the location 22n are decremented or incremented in step 43 still further for even higher values of the current contents of the "decrement" or "increment" location respectively of the relevant pair.

It will be appreciated that, if the analog voltage applied to a given input 7n of the arrangement of Figure 1 is stationary, the contents of the relevant location 22n will be alternately incremented and decremented on successive scans of the relevant input. This can be avoided, if desired, by modifying the microcomputer program of Figure 2 so that the amount by which the contents of location 22n are decremented or incremented in steps 35 and 36 is determined by both the current output signal of comparator 4 and the output signal of comparator 4 when the relevant input 7n was scanned the immediately preceding time, more particularly so that if these signals are 0 and 1, or 1 and 0, respectively no change is made to the contents of location 22n or half the usual change is made and contents are then maintained at the resulting value so long as the alternating is and Os persist.

The multichannel tracking analog-to-digital converter arrangement described may, for example, form part of a servo system. Thus, for example, the analog voltages applied to the inputs 7n may be the output voltages of respective temperature-sensing transducers, e.g. thermocouples, in a furnace, the microcomputer 5 being arranged to control various heating elements of the furnace in a suitable way in accordance with the current contents of the various locations 22n It will be evident that various modifications may be made to the arrangement described, within the scope of the invention defined by the claims.For example the arrangement does not necessarily include a microcomputer; the storage locations 221....22N may be constituted by respective counters which are incremented or decremented at the relevant times in accordance with the output signal of comparator 4 under the control of a suitable hard-wired clock and control -pulse generator which also controls the multiplexer 1 and the switches 3 and 9 (and the D/A converter 6 if required).On the other hand if the microcomputer 5 is provided it will be evident that the various locations 221....22N need not be constituted by fixed addresses in a data memory; all that is required is that the microcomputer explicitly or implicitly maintains a record of where each item of data is currently stored so that it can be recalled for updating and D/A conversion each time this is required, and be written back to any storage location address which may then be available. As another example the various inputs 71-7N together with the corresponding locations 221....22N may be scanned in some way other than cyclically and successively. They may, for example, be scanned in a pseudo-random order, or it may be arranged that some are scanned more frequently than others.As yet another example the output 17 of D/A converter 6 need not be connected directly to one electrode of the integrator circuit capacitance 12; it may be connected instead to the subtrahend input of a subtractor (not shown) which may be included in the signal path from the multiplexer output 8 to the integrator resistance 11. This resistance itself need not be constituted by a discrete resistor but may be constituted, for example, by the transresistance of a transresistance amplifier. The integrator capacitance 12 similarly need not be constituted by a simple discrete capacitor but may, for example, be constituted by a so-called active capacitor, i.e. a high-gain inverting amplifier having a capacitor connected between its output and its input, the comparator 4 then being connected to the amplifier output and the switch 3 being connected in parallel with the capacitor.

From reading the present disclosure, other modifications will be apparent to persons skilled in the art. Such modifications may involve other features which are already known in the design, manufacture and use of AID conversion arrangements and component parts thereof and which may be used instead of or in addition to featuresalready described herein. Although claims have been formulated in this application to particular combinations of features, it should be understood that the scope of the disclosure of the present application also includes any novel feature or any novel combination of features disclosed herein either explicitly or implicitly or any generalisation thereof, whether or not it relates to the same invention as presently claimed in any claim and whether or not it mitigates any or all of the same technical problems as does the present invention. The applicants hereby give notice that new claims may be formulated to such features andlor combinations of such features during the prosecution of the present application or of any further application derived therefrom.

Claims (9)

CLAIM(S)

1. A method of multichannel tracking analog-to-digital conversion in which digital representations of the current values of a plurality of analog voltages are maintained in respective digital data storage locations, the voltages being repeatedly scanned in a multiplexed manner and the respective representations being updated in accordance with any changes which occur in the corresponding voltages from scan to scan, characterized in that, when each voltage is scanned, any difference between it and the current contents of the corresponding storage location converted to analog form is averaged over a finite time by means of a common analog integrator circuit and the relevant current contents are corrected (if necessary) in accordance with the result of the averaging process converted to digital form.

2. A method as claimed in Claim 1, wherein each said result is taken after the relevant averaging process has been terminated.

3. A method as claimed in Claim 1 or Claim 2, wherein the output signal of the integrator circuit is zeroed before each said finite time commences.

4. A method as claimed in any preceding claim, wherein each conversion of a said difference to analog form is effected by means of a common analog-to-digital converter and each conversion of a said result to digital form is effected by means of a common digital-to-analog converter.

5. A method as claimed in Claim 4, wherein the common analog-to-digital converter is constituted by a comparator.

6. A method as claimed in Claim 5, wherein for each analog voltage a respective record is kept of the number of immediately preceding scans thereof which have resulted in corrections to the contents of the corresponding storage location in the same sense and, if when a said analog voltage is scanned the relevant number has at least a predetermined value and any correction currently required has the relevant sense, the correction made is by an amount greater than unity, any correction made otherwise being by a unit amount.

7. A multichannel tracking analog-to-digital conversion arrangement for implementing a method as claimed in any preceding claim, comprising a multiplexer having a respective input for each of the analog voltages and an output, storage means comprising a respective digital data storage location corresponding to each of said inputs, digital-to-analog converter means having an input coupled to a data output of said storage means and an output, an analog integrator circuit having inputs coupled to the multiplexer output and to the output of the converter means respectively, for integrating the difference between analog signals present in operation at these outputs, analog-to-digital converter means having an input coupled to an output of said integrator circuit, and control means for said multiplexer and said storage means for controlling the multiplexer to couple its said inputs successively and repeatedly to its output and selecting the corresponding storage locations in step therewith so that each time a said input of the multiplexer is coupled to its output the integrator circuit will average over a finite time the difference between any analog voltage present at the relevant input and the contents of the corresponding said storage location converted to analog form, the analog-to-digital converter means having an output coupled to said storage means for correcting (if necessary) the contents of each selected storage location in accordance with the result of the relevant averaging process.

8. A multichannel tracking analog-to-digital conversion arrangement substantially as described herein with reference to the drawings.

9. A method of multichannel tracking analog-to-digital conversion substantially as described herein with reference to the drawings.