GB2242297A - Transforming patterns of characters/graphics - Google Patents

Abstract

Transition buffers (11, 12) receive from a computer a digital representation of the pattern of a character/graphic according to a first sequence or its reverse respectively, to feed shift registers (21-28), further transition buffers (31, 32) being provided for receiving the serial output of each of the shift registers according to a second sequence or its reverse respectively. A control counter (40) controls information flow. Thus, the pattern is rotated 90 degrees clockwise or counter-clockwise. with or without reflection. <IMAGE>

Description

APPARATUS FOR TRANSFORMING PATTERNS OF CHARACTERS/GRAPHICS This invention relates to a computer hardware device, more particularly to a computer hardware device for transforming the patterns of characters/graphics.

A computer outputs readable alphanumeric text or graphics on a peripheral unit such as a display screen or a printer/plotter. However, there are some functions which the computer has difficulty in doing. An example is shown in Figures 1A, 1B. In these figures, a character A is represented by an 8 x 8 matrix and it is desired to print this character sideways, i.e.f the character A of Figure 1A is to be rotated by 90 degrees counterclockwise, as shown in Figure 1B. The usual procedure to achieve this function is to use a computer software which will first read the digital representation of the pattern of the character, then shift the digital representation in a predetermined number of positions before sending the shifted data to the printer/plotter.This procedure is complicated, uses up a large amount of the memory capacity of the computer and is relatively slow.

Therefore, an object of this invention is to provide a hardware device which achieves the function of shifting the digital representation of the pattern of a character for transforming the pattern of the character Another object of this invention is to provide a hardware device which achieves the above-mentioned funcclon at a faster pace and a lower memory requirement than that of a computer software performing the same function.

Accordingly, the hardware device of this invention is to be incorporated in the computer hardware and comprises a first group of bit transition buffers for receiving the digital representation of the pattern of a character/graphic; a plurality of shift registers for receiving data coming from the first group of bit transition buffers; a second group of bit transition buffers for receiving the contents of the shift registers; and a control counter for controlling the distribution of incoming data to the shift registers and the flow of data shifting out from the shift registers to the second group of bit transition buffers The output of the second group of bit transition buffers is the digital representation of the pattern of the character/graphic in either of the following forms: the character rotated 90 degrees clockwise, the character rotated 90 degrees counterclockwise, or the mirror image along an imaginary Y-axis of the previous two forms.

Other features and advantages of this invention wilt become apparent from the following detailed description of the preferred embodiment with reference to the accompanying drawings, in which: Figures lA, 1B illustrate the functioning of prior art; Figure 2 is a circuit diagram of the preferred embodiment according to this invention; Figures 3A, 4A show a character pattern represented by an 8 x 8 matrix; Figure 3B shows the character pattern of Figure 3A rotated 90 degrees counterclockwise; Figure 3C is a mirror image along an imaginary Yaxis of the character pattern in Figure 3B; Figure 4B shows the character pattern of Figure 4A rotated 90 degrees clockwise; and Figure 4C is a mirror image along an imaginary Yaxis of the character pattern in Figure 4B.

Referring to Figure 2, a circuit diagram of the preferred embodiment of a transformation apparatus according to the present invention comprises a first group of bit transition buffers 10, a plurality of shift registers 20, a second group of bit transition buffers 30 and a control counter 40.

The first group of bit transition buffers 10 comprises a first bit transition buffer 11 and a second bit transition buffer 12. The first bit transition buffer 11 receives the bits of the digital representation of the pattern of a character from a computer, while the second bit transition buffer 12 receives the reverse order of the same.

Each of the shift registers 21, 22, 23, 24, 25, 26, 27, 28 of the plurality of shift registers 20 sequentialLy receives data coming from either the first bit transition buffer 11 or the second bit transition buffer 12 and temporarily stores this information.

The second group of bit transition buffers 30 comprises a third bit transition buffer 31 and a fourth bit transition buffer 32. The third bit transition buffer 31 receives bit by bit the contents of each of the plurality of shift registers 20, while the fourth bit transition buffer 32 receives the reverse order of the same.

The control counter 40 is electrically connected to the first group of bit transition buffers 10, the second group of bit transition buffers 30, and the plurality of shift registers 20. The control counter 40 controls the distribution of incoming data to the shift registers 20, and the flow of data comprising all bits shifted out by the shift registers 20 at a particular time to the second group of bit transition buffers 30.

Referring to Figure 3A, a character pattern represented by an 8 x 8 matrix is shown. Each square in the matrix is either a blank space (0) or a shaded space (1). Each row is represented by an 8-bit byte as follows: Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 Row 1: 0 0 0 1 1 0 0 0 Row 2: 0 0 1 0 0 1 0 0 Row 3: 0 0 1 0 0 1 0 0 Row 4: 0 0 1 0 0 1 0 0 Row 5: 0 1 1 1 1 1 1 0 Row 6: 0 1 0 0 0 0 1 0 Row 7: 0 1 0 0 0 0 0 0 0 Row 8: 1 1 0 0 0 0 0 0 When the character pattern in Figure 3A is to be rotated 90 degrees counterclockwise as shown in Figure 3B, the control counter 40 controls the second bit transition buffer 12 to fill in each of the shift registers 20 one at a time.The contents of each shift register 20 shift registers 21 to 28) are as follows: (21) (22) (23) (24) (25) (26) (27) (28) 0 0 0 0 0 o 0 0 H (I7) 0 0 0 0 1 1 0 0 G (I6) 0 1 1 1 1 0 0 0 F (I5) 1 0 0 0 1 0 0 0 E (I4) 1 0 0 0 1 0 0 0 D (I3) 0 1 1 1 1 0 0 0 C (12) 0 0 0 0 1 1 1 1 B (I1) 0 0 0 0 0 0 0 1 A (I0) After each of the shift registers 20 has received data coming from the second bit transition buffer 12, the control counter 40 controls the shift registers 2C to serially output the bits (17) to the fourth bit transition buffer 32, forming a first byte output H.

The first byte output H is received by the computer and the shift registers 20, then outputs the bits (I6) forming a second byte G and so on. The eight byte outputs now represent a character pattern as shown in Figure 3B. The eight 8-bit byte outputs are as follows: Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 Row 1: 0 0 0 0 0 0 0 0 Row 2: 0 0 0 0 1 1 0 0 Row 3: 0 1 1 1 1 0 0 0 Row 4: 1 0 0 0 1 0 0 0 Row 5: 1 0 0 0 1 0 0 0 Row 6: 0 1 1 1 1- 0 0 0 Row 7: 0 0 0 0 1 1 1 1 Row 8: 0 0 0 0 0 0 0 1 If the control counter 40 controls the shift registers 20 to serially output its contents to the third bit transition buffer 31, the order of the information received by the third bit transition buffer 31 being the reverse of the information received by the fourth bit transition buffer 32, the character produced, as shown in Figure 3C, is a mirror image along an imaginary Y-axis of the character in Figure 3B.The character pattern in Figure 3C is represented by the following 8-bit bytes: Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 Row 1: 0 0 0 0 0 0 0 Row 2: 0 0 1 1 0 0 0 0- Row 3: 0 0 0 1 1 1 1 0 Row 4: 0 0 0 1 0 0 0 1 Row 5: 0 0 0 1 0 0 0 1 Row 6: 0 0 0 1 1 1 1 0 Row 7: 1 1 1 1 0 0 0 0 Row 8: 1 0 0 0 0 0 0 0 When the character pattern in Figure 4A is to be rotated 90 degrees clockwise as shown in Figure 4B, the control counter 40 controls the first bit transition buffer 11 to fill in each of the shift registers 20 one at a time.The contents of the shift register 20 are as follows: (21) (22) (23) (24) (25) (26) (27) (28) o 0 0 0 0 0 0 1 H (I7) 0 0 0 0 1 1 1 1 G (I6) 0 1 1 1 1 0 0 0 F (I5) 1 0 0 0 1 0 0 0 E (I4) 1 0 0 0 1 0 0 0 D (I3) 0 1 1 1 1 0 0 0 C (I2) 0 0 0 0 1 1 0 0 B (I1) 0 0 0 0 0 0 0 0 A (I0) The control counter 40 controls the plurality of shift registers 20 to serially output the bits (I7) to the third bit transition buffer 31, forming a first byte H. The first byte output H is received by the computer and the plurality of shift registers 20 then outputs the bits (I6) forming a second byte G and so on. The eight byte outputs form a character pattern as shown in Figure 4B.The eight byte outputs are as follows: Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 Row 1: 1 0 0 0 0 0 0 0 Row 2: 1 1 1 1 0 0 0 0 Row 3: 0 0 0 1 1 1 1 0 Row 4: 0 0 0 1 0 0 0 1 Row 5: 0 0 0 1 0 0 0 1 Row 6: 0 0 0 1 1 1 1 0 Row 7: 0 0 1 1 0 0 0 0 Row 8: 0 0 0 0 0 0 0 0 If the control counter 40 controls the plurality of shift registers 20 to serially output its contents to the fourth bit transition buffer 32, the character pattern produced by the byte outputs, as shown in Figure 4C, is a mirror image along an imaginary Y-axis of the character pattern in Figure 4B. The character pattern of Figure 4C is represented by the following bytes: Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 Row 1: 0 0 0 0 0 0 0 1 Row 2: 0 0 0 0 1 1 1 1 Row 3: 0 1 1 1 1 0 0 0 Row 4: 1 0 0 0 1 0 0 0 Row 5: 1 0 0 0 1 0 0 0 Row 6: 0 1 1 1 1 0 0 0 Row 7: 0 0 0 0 1 1 0 0 Row 8: 0 0 0 0 0 0 0 0

Claims (6)

1. I CLAIM: 1. An apparatus for transforming patterns of characters/graphics to be used in a computer, comprising: a first means for receiving from the computer a digital data representing the pattern of a character -according to a first sequence and outputting said digital data according to a second sequence; a plurality of second means, each receiving said digital output data from said first means one at a time and temporarily storing said data before serially outputting said data; a third means for receiving said serial digital data from each of said plurality of second means according to a third sequence and outputting to the computer said serial digital data according to a fourth sequence; and a control means for controlling information flow formed by the exchange of digital data between said first means and said plurality of second means, said control means similarly controlling information flow between said plurality of second means and said third means.
2. 2. An apparatus as claimed in Claim 1, wherein said second sequence is one in a same order of said first sequence.
3. 3. An apparatus as claimed in Claim 1, wherein said second sequence is one in a reverse order of said first sequence.
4. 4. An apparatus as claimed in Claim 1, wherein said first means and said third means are bit transition buffer means.
5. 5. An apparatus as claimed in Claim 1, wherein said plurality of second means is a plurality of shift register means.
6. 6. An apparatus as substantially described hereinbefore with reference to the accompanying drawings.