GB2240003A - Image reading device - Google Patents

Abstract

An image reading device for a digital copier, facsimile transceiver or similar equipment and having a plurality of line sensors arranged in a zig-zag configuration. The analogue signals from the sensors are passed to an A/D converter to produce digital multilevel signals which are then fed to a delaying means 13 which compensates for the deviation in the positions of the line sensors. Data bit converting means 18, 19 is provided at each of the input side and the output side respectively of delaying means. Data are inputted to and outputted from the delaying means after being subjected to data bit conversion executed by the individual data converting means. <IMAGE>

Description

a f -I- IMAGE READING DEVICE

BACKGROUND OF THE INVENTION

The present invention relates to an image reading device for a digital copier, facsimile transceiver or similar equipment and having a plurality of line sensors.

A current trend with the above-described type of image reading device is toward the use of a 1: 1 magnification line sensor which has various merits such as the capability of miniaturizing and simplifying optics. Since the length of a 1: 1 line sensor chip is limited for technical reasons, a plurality of sensors are used to read one line of a document of ordinary size. Usually, a plurality of sensors are arranged in a zig- 2ag configuration since arranging them on the same line would fail to read a document between nearby chips (see, for example, Japanese Patent Laid-Open Publication Nos. 16760/1985, 134167/1986, and 290073/1988). Regarding a color image, it is technically difficult to implement a great number of light-sensitive elements adapted for red (R), green (G) and blue (B) with a single color line sensor. It has been customary, therefore, to arrange a plurality of color line sensors in the subscanning direction.

In any case, when a plurality of line sensors are located at different positions in the subscanning direction, they read a document at different timings from one another. The deviation in the reading positions of the line sensors is usually compensated for by delaying means such as an 8-bit static RAM or an 8-bit line memory, as disclosed in above-mentioned Laid-Open Publications. The bit construction of such a memory is identical with that of an 8-bit analog- to- digital (AD) converter which transforms data read from a document into digital multi-level signals.

Since a static RAM or a line memory usable as the delaying means and having a large capacity is expensive, use is generally made of a memory capable of accommodating one line of data.

However, assuming that the scanning speed (subscanning speed) is changed in matching relation to a magnification change ratio, the delaying means has to execute more than ten lines of delay and, therefore, needs a corresponding number of memories.

This increases the cost, circuit scale, and substrate space. A a dynamic RAM which is comparatively low in cost per memory capacity and has a large capacity may be used to reduce the required number of memories as well as the space. However, the problem with the dynamic RAM is that its bit construction is different from that the 6- to 8-bit construction of an AD converter for use in a high tone reading device or a color image reading device. To eliminate this problem, the output of the AD i converter may be divided and written to a plurality of RAMs. Such a multiple RAM scheme brings about another problem that the efficient use of the individual RAMs is obstructed and the number of RAMs is increased, resulting in the increase in cost.

SUMMARY OF THE INVENTION

It is therefore an object of the present invention to provide an image reading device which reduces the number of memories constituting delaying means and thereby saves space and cost.

It is another object to provide a generally improved image reading device.

An image reading device of the present invention comprises a plurality of line sensors arranged on different lines in a subscanning direction, a processing section for processing analog signals each being outputtedby a respective one of the plurality of line sensors, an AD converting section for converting outputs of the processing section into digital multi-level signals, a delaying section having thesame bit construction as the AD converting section for delaying a part of outputs of the AD converting section, and data bit converting sections each being provided at respective one of the input side and the output side of the delaying section.

By way of example, the nature of the present invention will become more apparent from the following detailed description taken with the accompanying drawings in which:

Fig. 1 is a block diagram schematically showing delay processing means representative of a first embodiment of the present invention; Fig. 2 is a timing chart showing various signals appearing in the embodiment; Fig. 3 is a view showing a basic construction of a 1: 1 magnification color sensor; Fig. 4 is a view showing a basic construction of a CCD sensor; Fig. 5 is a view showing a basic construction of a 1: 1 color sensor having a zig-zag configuration; Fig. 6 is a block diagram schematically showing the internal construction of a CCD; Fig. 7 is a block diagram showing a color image reading device; Fig. 8 is a block diagram showing a specific construction of a digital processing section; Fig. 9 is a timing chart showing various signals adapted for memory operation control; Fig. 10 is a block diagram showing a second embodiment of the present invention; Fig. 11 is a timing chart demonstrating the operation of the second embodiment; Fig. 12 shows a sensor construction representative of a third embodiment of the present invention; and Fig. 13 is a block diagram showing the third embodiment schematically.

1 -6 DESCRIPTION OF THE PREFERRED EMBODIMEN TIS

Preferred embodiments of the image reading device in accordance with the present invention will be described with reference to the accompanying drawings.

First Embodiment Referring to Figs. I to 9, a first embodiment of the present inention applied to a color image reading device is shown.

To begin with, a method in which an image sensor for photoelectrically reading a color image is implemented as a 1: 1 magnificaton color sensor will be described. This type of method is advantageous in that a device for practising it is miniature due to the simple optics, and in that it is free from color deviations in the main scanning direction because the sensor itself performs color separation. As shown in Fig. 3, a 1:1 color sensor 3 has a resolution of sixteen pixels per millimeter and has each pixel divided into segments of different colors, e.g. red (R), green (G), and blud (B). Filters of different colors each is fitted on respective one of the segments.

To to read a document of size A3 in the widthwise direction (297 millimeters), the sensor 3 needs 4, 752 pixels, i. e. 14, 256 segments. In practice, however, implementing such a great number of light-sensitive elements with single color line sensor is difficult for technical reasons. Usually, therefore, they are constituted by a plurality of color line sensors which are arranged in an array in the subscanning direction. As shown in 1 Fig. 4, a CCD (Charge Coupled Device) sensor 4 usable as a color line sensor is not sensitive to light at a leading end portion thereof (dummy pixels). An array of CCD sensors 4 would fail to read & document at the joints therof. In the light of this, as shown in Fig. 5, there has been proposed a 1:1 color sensor 5 having the CCD sensors 4 arranged in two arrays in a zig-zag configuration and such that nearby sensors 4 overlap each other.

The specific color sensor 5 shown in Fig. 5 is made up of five CCD sensors 4 each receiving a drive signal and producing an output signal independently of the others. Since the positions where the odd CCD sensors 4 and the even CCD sensors 4 read a document are deviated from each other in the subscanning direction, seven stages of line memories (line shift gates) are built in to compensate for the deviation. As a result, the sensor produces five parallel video signals each being associated with respective one of five divisions of a document and in the order of G, B and R.

Fig. 6 shows the internal arrangement of the CCD sensor 5.

In the figure, there are shown the first phase clock 1A, the second phase clock 2A, the second phase, last stage clock 02B line shift gates OV1 to OV7, a shift gate SH, a reset RS, a power source OD, a signal output OS, and a substrate (ground) SS.

Referring to Fig. 7, a color image reading device with which the present invention is practicable, particularly the flow of image data, is shown. As shown, an analog processing section (processing means) 6, an analogto- digital (AD) converter (AD converting means) 7 and a digital processing section 8 are sequentially connected to the output side of the color sensor 5. The output of the color image reading device is fed out via an interface 9. A controller 10 is provided for controlling the operation timings of the various sections 5 to 9. In operation, video output signals CCD1 to CCD5 of the color sensor 5 are fed to the analog processing section 6 to be sampled and held, amplified, and then subjected to dark current correction, while level correction, and shading correction on a CCD signal basis. The AD converter 7 quantizes the individual output signals of the analog processing section 6 to convert them into 8-bit 15 multi-level digital signals CCD1 to CCD5. When a whiteshading plate is read prior to a document, the AD converter 7 writes shading data SHD1 to SHD5 to a shading correction memory which is incorporated in the analog processing section 6. While a document is read, the AD converter 7 delivers the 8-bit 20 digital signals CCD1 to CCD5 to the digital processing section 8. The digital processing section 8 is constituted by delay means for synchronizing the reading positions of the signals outputted by the CCD sensor 5, and store means for completing one line color by color. The outputsof the digital processing section 8, i. e. , 25 8-bit G, B and R signals are fed out in synchronism with a line 1 -gsynchronizing signal and a pixel clock which are fed from a host or generated in the reading device itself. The timing controller generates timing signals meant for the individual blocks 5 to 9.

Fig. 8 shows a specific construction of the digital processing section 8. The digital processing section 8 is shown as comprising delay processing means 11 and I-line storing means 12. Due to the inherent structlire of the color sensor 5, the CCDs 2 and 4 read a portion of a document which precedes. a portion which the CCDs 1, 3 and 5 read. Hence, the line memories built in the CCD sensor 4 and the delay processing means 11 set up synchronization so that the five signals may be written to the 1-line storing means 12 as signals of the same line and of the same pixels. In the illustrative embodiment, the delay processing means has delay memories (DM) l3a and 13b associated with the even CCI)s 2 and 4 which precede CCDs 1, 3 and 5 in the subscanning direction. The delayrnemries 13a and 13b each has a capacity capable of delaying N lines where N is dependent on the magnification change range. For example, assuming that the magnification change range is 25 % to 400 Yo, then the subscanning speed is four times to one-fourth of the subscanning speed particular to 1:1 magnification, resultingin the need for sixteen stages of delay in total. When the sixteen stages of delay are assigned to the delay memories 13a and 13b, N will be "16". When seven stages of delay are effected by the line memories of the sensor 4, N will be "9". To change the number of delay lines in matching relation to the magnification change ratio, the amounts of data which the delay memories 13a and 13b store are controlled by the timing signals fed from the timing controller 10. Since the inputs to the 1-line storing means 12 are of the same.line and of the same pixels, as stated earlier, the colors G, B and R are also the same throughout the five different signal lines.

The 1-line storing means 12 has memories 14a to l4e, 15a to l5e and 16a to He arranged in this order and assigned to G data, B data., and R data., respectively. These memories 14, 15 and 16 each is implemented as a FIFO (First-In First-Out) memory having independent input and output ports, not needing address inputs, and using a write memory area. and a read memory area in a toggle fashion in the same line period. Data area read out of the memories 14, 15 and 16 in the order of a to e each, so that the individual 1-line color data (G, B and R) are fed to the interface 9 in synchronism.

Fig. 1 shows a specific construction of the delay memory 13 (13a or 13b) which is a characteristic feature of the illustrative embodiment. As shown, input signals DIO to D17 and output signals DOO to D07 each has eight bits, while a memory 17 which is the major component of the delay memory 13 and serves as delay means has four bits. 4-bit gates 18a and l8b assigned to lower four bits DIO to D13 and upper four bits D14 to D17, respectively, are connected to the input of the memory 17 in parallel. The gates 18a and l8b constitute data bit converting means on the input side. A latch 19 and a direct output line 20 are connected to the output of the memory 17 and assigned respectively to four lower bits DOO and D03 and four upper bits D04 to D07 of the output of the memory 17. The latch 19 and direct output line 20 constitute data bit converting means on the output side. The memory 17 is inplerrented as an asynchronous input/output FIFO field memory using the cells of dyn&mic RAM, and each memory has a capacity greater than the amount of data corresponding to the maximum number of delay lines. For example, to delay by sixteen lines, a capacity of 16 (lines) X 2, 928 (pixels) X 8 (bits) = 37, 4784 (bits) are needed, but a capacity of 1 megabits (= 256k X 4) suffices.

The operation of the delay memory 13 having the above construction will be described with reference to Fig. 2. A signal VCLK and a. signal VCLK are applied to gate terminals G1 and G2 of the gates 18a alid 18b, respectively. When the signal VCLK is in a high level or "H", the gate I B& is opened to deliver the lower four bits DIO to DI3 to the memory 17. When the sinal VCLK is in a low level or "L", the gate l8b is opened to feed the upper four bits D14 to D17 to the memory 17. When the inputs to the gate terminals G1 and G2 both are "H", the outputs of the gates 18a and l8b have high impedance with the result that four lower bits of data and four upper bits of data are applied to the memory 17 alternately with each other. A write clock WCLK fed to the memory 17 has a period which is one half of the period of the signal VCLK, and data are written to the memory 17 at the positive-going edges of the clock WCLK. A read clock RCLK is also applied to the memory 17 and is the same signal as the write clock WCLK. Data are read out of the memory 17 in synchornism with the positive-going edges of the read clock RCLK. Due to the FIFO operation, the lower four bits DOO to D03 and the upper four bits D04 to D07 are 10 sequentially read out in this order. In Fig. 2, data. without hatching and data. with hatching are representative of the data. DOO to D03 and the data. D04 to D07, respectively. The latch 19 latches data at the positive-going edge of the VCLK and, therefore, thelower four bits DOO to DO3. As a result, the lower 15 four bits of data from the latch 19 and the four upper bits of data from the memory 17, i. e., eight bits of data in total are applied to the 1-line storing means 12. If the 1-line storing means 12 stores data at the negative- going edges of the signal VCLK (as indicated by & mark t in Fig. 2), it will be capable of 20 storing the lower and upper data of the same pixel accurately and with a margin with respect to time.

Fig. 9 shows a read enable signal RE, a write enable signal WE, a read reset signal RSTR, a write reset sigal RSTW, and a line synchronizing signal LSYNC. When the signals RSTR and RSTW become "U'level, the read address and the write address X are reset and returned to the leading addresses. It follows that the number of lines occurring during the interval between the sucessive "L" levels of the signals RSTR and RSTW is the number of lines delayed by the memory 17. In the specific timings shown in Fig. 9, two lines of period exists between the "L" levels of the signals RSTR and RSTW, so that the memory 17 delays two lines. By so controlling the timings of the signals RSTR and RSTW it is possible to control the number of delay lines in matching relation to the magnification change ratio and thereby eliminating the deviations of the reading positions of the CCD sensors 4 with accuracy.

Second Embodiment An alternative embodiment of the present invention is shown in Figs. 10 and 11. While the first embodiment needs two memories 17 due to the two delay memories incorporated in the delay processing means, the alternative en-bodimnt which will be described is implemented with a single memory 21. Specifically, in this particular embodment, data bit converting means comprises gates 22a and 22b assigned respectively to the lower bour bits and the upper four bits of the CCD2 signal line, and gates 22c and 22d assigned respectively to the lower four bits and the upper four bits of the CCD4 signal line. The gates 22a to 22d are connected to the input side of the memory 21 in parallel. Connected to the output side of the memory 21 are laches 23a. and 23b assigned respectively to the lower four bits and the upper four bits of the CCD2 signal line, and a latch 23c and a direct output line 24 assigned respectively to the lower four bits and the upper four bits of the CCD4 signal line. The latches 23a to 23c and the direct ouput line 24 also constitute data bit converting means. The memory 21 has twice greater capcity than in the circuitry of Fig. 1 so that it will need 374, 784 X 2 = 749, 568 (bits) in the case of sixteen lines of delay, but 1 megabit suffices.

The operation of the illustrative embodiment is as follows.

As shown in Fig. 11, one pixel data output period is divided into four periods. As signals GCK1 to GCK4 become "L" sequentially, the gates 22a to 22d are opened and closed sequentially with the result that data. each having four bits are sequentially applied to the memory 21. A write clock WCLK and a read clock RCLK applied to the memory 21 each has aperiod which is one-quarter of a pixel period. Thedataare written to the memory 21 at the positive-going edges of the write clock WCLK. Assume that the lower four bit data of the CCD2 signal line is "2L", the upper four bit data of the CCD2 signal lin6 is "2H", the lower four bit data.

of the CCD4 signal line is "4L", and the upper four bit data of the CCD4 signal line is "4H". Then, the data "2L", "2H", "4L" and "4H" are sequentially written in this order and, at the positive-going edges of the read clock RCLK, read out in the same order. The latches 23a to 23clatch respectively the data "2L", "2H" and "41," at the positive-going edges of the signals 1 -is- GCKI to GCK3. The outputs of the latches 23a and 23b and the outputs of the latch 23c and direct output line 24 each is fed as 8-bit data tothe 1-line storing means 12, Fig. 8. Then, the 1-line storing means 12 will store the input data at the timings indicated by a mark t in Fig. 11. The number of delay lines will be controlled in matching relation to the magnification change ratio in the same manner as in the cicuitry of Fig. 1, i. e., by cntrolling the timings of the write reset signal RSTW and read reset signal RSTR.

Third Embodiment Referring to Fgis. 12 and 13, another alternative embodiment of the present invention is shown which is applicable to a 1: 1 color sensor 26 having R, G and B CCD sensors 25R, 25G and 25B arranged in parallel in the subscanning direction. As shown, the sensors 25R, 25G and 25B are positioned at equal distances I in the subscanning direction, and the sensors 25R and 25B are spaced &part by a distance of 21. The sensors 25R, 25G and 25B each has 5, 000 pixels and reads a'docunent of size A3 with& resolution of 16 pixels per millimeter in the widthwise direction.

As shown in Fig. 13, the outputs of the sensors 15R, 15G and 15B are processed independently of one another.

Specifically, the outputs of the sensors 25R, 25G and 25B are respectively amplified by amplifiers 27R, 27G and 27B and then converted into digital signals by AD converters 28R, 28G and 28B. Thereafter, the R signal line output from the sensor 25R is delayed by an amount corresponding to the distance 21 by delay processing means 29R, the G signal line output from the sensor 25G is delayed by an amount corresponding to the distance I by delay processing means 29G, and the B signal line ouput from the sensor 25B is not delayed at all. The resultant ouptuts 0 the delay processing means 29R, 29G and 29B are delivered to a digital processing section 30 which then produces 8-bit R, G and B data undergone correction as to the deviations of reading positions.

The delay processing means 29R and 29G may each be implemented with the specific construction shown in Fig. 1.

Since the delay processing means 29R needs twice greater delay than the delay processing mens 29G, a. twice longer interval between the successive "L" levels of the write reset and read reset signals RSTW and RSTR will be assigned to the delay processing means 29R.

In summary, in accordance with the present invention, delaying means for compensating for the positional deviations among a plurality of line sensors is preceded and succeeded by data bit converting means. Therefore, even when relatively inexpensive delaying means different in bit construction from AD converting means is used, the memory capacity of the delaying means is effectively used. Thisis successful in reducing the number of memories constituting the delaying means and thereby i the space and cost.

Various modifications will become possible for those skilled in the art after receiving the teachings of the present disclosure without departing from the scope therof.

Claims (6)

1 1 - An image reading device comprising:

a plurality of line sensors arranged on different lines in a subscanning direction; processing means for processing analog signals each being outputted by a respective one of said plurality of line sensors; analog to- digital (AD) converting means for converting outputs of said processing means into digital multi-level signals; delaying means having thesame bit construction as said AD converting means for delaying a part of outputs of said AD converting means; and data bit converting means provided at each of an input side and an output side of said delaying means.

2. A device as claimed in claim 1, wherein said AD converting means has an 8-bit output bit construction.

3. A device as claimed in claim 1 or 2, wherein said delaying means comprises a 4-bit delay memory.

4. A device as claized in claim 1,2 or 3, wherein said data bit converting means provided at the input side of said delaying means comprises gate means connected to said input side of said delay means, said data bit converting means provided at the output side of said delaying means comprising latch means connected said output side of said delaying means an a direct output line.

5. An image reading device substantially as hereinbefore described with reference to and as illustrated in the acccnpanying drawings.

Published 1991 atThe Patent Oflice. State House.66/71 High Holborn. LDndonWClR4TP. Further copies maybe obtained from Sales Branch. Unit

6. N:ne Mile Point Cwnifelinfach. Cross Keys. Newport. NPI 7HZ. Printed by Multiplex techniques lid, St Mary Cray. Kent.

1