GB2239126A - Polycrystalline semiconductor thin film transistors - Google Patents
Polycrystalline semiconductor thin film transistors Download PDFInfo
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- GB2239126A GB2239126A GB8926789A GB8926789A GB2239126A GB 2239126 A GB2239126 A GB 2239126A GB 8926789 A GB8926789 A GB 8926789A GB 8926789 A GB8926789 A GB 8926789A GB 2239126 A GB2239126 A GB 2239126A
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- 239000010409 thin film Substances 0.000 title claims abstract description 23
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- 238000000034 method Methods 0.000 claims abstract description 32
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- 230000008901 benefit Effects 0.000 abstract description 8
- 239000011521 glass Substances 0.000 abstract description 5
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- 125000006850 spacer group Chemical group 0.000 description 8
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- 238000001953 recrystallisation Methods 0.000 description 4
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66666—Vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78642—Vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78672—Polycrystalline or microcrystalline silicon transistor
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Thin Film Transistor (AREA)
- Liquid Crystal (AREA)
Abstract
A vertical configuration thin film transistor carried on an insulative substrate (12) comprise a unitary polycrystalline semiconductor layer (10) having a columnar structure with grain boundaries extending generally perpendicularly of the substrate surface, formed conveniently for example by a LPCVD process using polysilicon, and two parallel, vertically- spaced, surfaces 14 and 16, at which respective main electrodes (22, 24) are provided by doping, with a vertical step (18) therebetween determining a channel region (20) over which an insulating layer (26) and a control electrode (32) are provided. The structure provides high mobility. This is used to advantage in an active matrix display device in which the TFTs are formed on a glass substrate and used as switches for display elements and/or components of integrated drive circuitry. <IMAGE>
Description
POLYCRYSTALLINE SEMICONDUCTOR THIN FILM TRANSISTORS,
DISPLAY DEVICES INCORPORATING SUCH TRANSISTORS,
AND METHODS FOR THEIR FABRICATION
This invention relates to polycrystalline semiconductor thin film transistors, display devices utilising such transistors and methods of fabricating such transistors.
One use of polycrystalline semiconductor thin film transistors, particularly polycrystalline silicon thin film transistors (hereinafter referred to as polysilicon TFTs), is as switching elements active matrix addressed display devices, especially liquid crystal display devices. For such purposes, polysilicon TFTs offer advantages over the more commonly used amorphous silicon TFTs because they have higher field effect mobilities.This higher mobility renders them suitable for use in the drive circuitry of such display devices and enables at least part of the drive circuit, namely the row driver circuit, providing periodic gating signals, to be integrated with the display elements on a common substrate, the TFTs acting as active switching elements of the display elements and the TFTs of the row driver circuit being formed simultaneously on the common substrate using large scale integration techniques. This greatly simplifies manufacture of the device.
Initially, high temperature (around 1000 degrees centigrade) processing was needed to fabricate the TFTs which required the use of expensive quartz substrates capable of withstanding such processing temperatures. However, recent developments in polysilicon TFT fabrication technology have lead to low temperature processing techniques, less than 650 degrees centigrade and typically 620 degrees centigrade or lower, enabling high temperature glasses to be used for the substrate.
Examples of a low temperature polysilicon TFT fabrication technique, and an active matrix liquid crystal display device using polysilicon TFTs for switching elements and for components of an integrated row driver circuit are described in the paper by
P. Migliorato entitled "Progress in Active Matrix Addressing of
LCDs" published in the Proceedings of Eurodisplay 1987 at pages 44 to 54.
While polysilicon TFTs are capable of being used in the row driver circuit, which basically comprises a shift register circuit providing gating signals to each row of picture elements on a row by row basis, their use in a column driver circuit, comprising sample and hold circuits providing data, for example, video signals, to all columns of picture elements simultaneously, is considered to be much more difficult to achieve in practice because of the frequencies at which the TFTs would be required to operate, particularly for a TV display. For a colour TV display, for example, the column drivers may be required to operate at a frequency of 10 to 40 MHz. This demands a comparatively high carrier mobility in the TFTs which generally has been difficult to achieve other than by using a high temperature fabrication process on a quartz substrate.
It is an object of the present invention to provide improved performance polycrystalline semiconductor TFTs which can be fabricated using a low temperature process.
It is another object of the present invention to provide polycrystalline semiconductor TFTs, and particularly polysilicon
TFTs, which offer improved mobility characteristics and which are suited for use in the driver circuits of active matrix addressed display devices.
According to one aspect of the present invention there is provided a thin film transistor formed on a planar insulative surface and comprising a polycrystalline semiconductor layer, first and second spaced main electrodes separated by a portion of the semiconductor layer and a control electrode overlying said portion and separated therefrom by insulating material, which is characterised in that the polycrystalline semiconductor layer is a unitarily-formed layer having a columnar structure with grain boundaries extending generally normal to the insulative surface and comprises two surfaces which are substantially parallel to, and spaced from one another normally of, the insulative surface with a step extending therebetween, and at which the first and second main electrodes are respectively provided, and in that the control electrode extends adjacent the step and is spaced therefrom by insulating material.
Such a TFT therefore has a vertical configuration with its channel region being constituted by the portion of the semiconductor layer adjacent to, and defining, the step and whose length is determined by the height of this step. This compares with conventional, lateral type, forms of polycrystalline semiconductor TFTs, for example the polysilicon TFTs described in the aforementioned Migliorato paper, in which the semiconductor layer is a constant thickness layer extending parallel to the substrate surface with the main, source and drain, electrode regions being provided spaced laterally from one another with respect to the substrate surface and in which the portion of the semiconductor layer between the source and drain regions forms a channel region extending parallel to the substrate surface.
The vertical TFT according to the invention exhibits a significantly higher carrier mobility than the conventional lateral TFT. This improvement stems from a recognition that the orientation of the micro-structure of the semiconductor layer plays an important role and by appropriately configuring the
TFT's structure in relation to this orientation the micro-structure can be utilised to advantage in providing improved mobility. As is known, polycrystalline silicon material, particularly when deposited using an LPCVD (low pressure chemical vapour deposition) technique as is most widely used, consists of grains composed of crystallites. The grains are generally elongate, having a major axis, and grow from nucleaction sites adjacent the substrate interface away from the interface generally perpendicularly.When deposited on a planar surface therefore the polysilicon layer has a columnar structure in which the grains, constituting columns, extend perpendicular to the planar surface. For a lateral type TFT it will be appreciated that the channel extends transversely of the columnar structure and hence comprises a high density of grain boundaries. In contrast the channel region of a TFT according to the invention extends substantially perpendicularly of the substrate surface and so the grain boundary density is lower with the average size of the grains being larger in the channel direction. As mobility is determined by the boundary densities and grain size the vertical TFT according to the invention consequently exhibits a much higher mobility than a lateral type
TFT.
The provision of the main electrodes at the two, parallel, surfaces of the semiconductor layer defined by the intermediate step results in further important benefits which enhance performance advantages. In using the two surface regions, or plateaus, as source and drain regions, it will be understood that the source, drain and channel regions are all integral portions of a common, unitarily-formed semiconductor layer. As such there are no interfaces present between these portions and accordingly the possibility of operational impairments associated with interfaces, for example, interfacial defects contributing to leakage effects, is avoided.
The invention is particularly beneficial for TFTs in which the polycrystalline semiconductor material comprises polysilicon. However it is envisaged that the invention is applicable also to TFTs utilising other polycrystalline semiconductor materials exhibiting a similar columnar grain structure.
With regard to an embodiment of a TFT according to the invention in which the semiconductor layer comprises polysilicon material, the thickness of the semiconductor layer portion defining the lower of the two parallel surfaces at which the main electrodes are provided preferably is at least around O.1#im. The minimum thickness is selected having regard to the micro-structure of the semiconductor layer which can normally be expected immediately adjacent the substrate surface. At this interface, the structure of the layer is more irregular and consists of relatively small-size grains formed at nucleation sites. Following formation of these small grains, which it is thought may extend to around 0.05/fin in height from the substrate surface, the larger grains defining the columnar structure are grown.In using a thickness for this portion which is greater than the anticipated thickness of the smaller grains a source, or drain, as well as the channel region can be created in the portion which comprises polycrystalline material composed of the larger grains. This ensures that satisfactory and reliable contact can be achieved at this region, for example between an electrode deposited on the surface of the layer portion if such an electrode is desired, as well as between this region and the channel region at the step. More importantly though, the poorer quality, fine grained polycrystalline material is positioned away from the channel and junction regions.
In addition to high mobility being obtained, the TFT according to the invention offers the further advantages of, firstly, requiring only a single semiconductor layer which simplifies fabrication, and, secondly, comprising standard materials which can be deposited and defined by conventional processes.
Previous proposals for producing higher mobilities in polysilicon TFTs have entailed using in lateral TFT configurations polysilicon layers formed by special techniques.
These techniques involve a recrystallisation process. For example, amorphous silicon films formed by a LPCVD process at around 550 degrees centigrade can be recrystallised by annealing at around 600 degrees centigrade, and hydrogenated amorphous silicon films can be treated by similar furnace annealing or by laser recrystallisation. Another proposed technique consists of amorphising a LPCVD polysilicon film with silicon implantation and then recrystallising at around 600 degrees centigrade. These recrystallisation processes all produce an increased grain size resulting in higher mobility. In practice, mobilities between about 30 to 100 cm2iV-s have been achieved in this way compared with a mobility of around 6cm2/V-s for a lateral type polysilicon
TFT using a conventional polysilicon film fabricated by a standard 620 degrees centigrade LPCVD process.Mobilities at least of the same order attainable from vertical configuration
TFTs according to the invention employing a columnar polysilicon layer and utilising to full advantage this structure.
Significantly, a columnar structure is obtained by using a standard LPCVD process and thus high mobility TFTs can be produced which avoid the need for any expensive and complicated recrystallisation process.
Preferably the semiconductor layer is doped at the regions of the two surfaces adjacent the step. Respective metal contacts may, if desired, be provided on the two doped surface regions to complete the main electrodes.
According to another aspect of the present invention, a method of fabricating a polycrystalline semiconductor TFT comprises the steps of forming on planar insulative surface a unitary layer of polycrystalline semiconductor material having a columnar structure with grain boundaries extending generally normal to the insulative surface with first and second surfaces substantially parallel to the insulative surface and spaced from one another normally of the insulative surface with a step extending therebetween, forming respective main electrodes at the two surfaces of the semiconductor layer and providing a control electrode overlying and spaced from the step by insulating material.
Preferably, for convenience and simplicity, the semiconductor layer is formed by a low pressure chemical vapour deposition process.
The step of forming the main electrodes may comprise doping the regions of the semiconductor layer at the first and second surfaces of the semiconductor layer adjacent the step. This step may further comprise depositing metal contacts on those surfaces. The two surface regions may be doped simultaneously or in respective, separate, operations. Preferably, prior to doping the surface regions of the semiconductor layer, a protective layer, for example of silicon oxide, is provided over the step and a part of the lower of the two surfaces immediately adjacent the step. This protective layer prevents dopant from reaching the semiconductor material adjacent the step laterally of the lowermost surface region and serves also as a spacer such that upon doping of the lowermost surface region one end of that region is substantially aligned with the step.Without this spacer lateral drift of dopant would result in the doped region extending beyond the step. Following doping of the first and second surface regions, the protective layer is removed and thereafter a gate insulator layer deposited over the step, prior to deposition of the control electrode.
According to a further aspect of the present invention there is provided an array of TFTs each according to the one aspect wherein said insulative surface is provided by a substrate common to all TFTs of the array.
According to a another aspect of the present invention, there is provided an active matrix addressed display device, for example a liquid crystal display device, incorporating a plurality of TFTs according to the one aspect of the present invention. The plurality of TFTs may be arranged in a matrix array with said insulative surface being provided by a substrate common to all TFTs in the array and wherein the TFTs of the array comprise switching elements associated with display elements of the display device for switching display signals to said display elements. The display device may alternatively or additionally include TFTs in accordance with the one aspect of the present invention serving as elements of the driving circuit for driving the display elements of the device, for example a shift register circuit for sequentially scanning rows of display elements and a sample and hold circuit for supplying data signals to the display elements. The TFTs according to the invention are particularly attractive for such purposes in a display device in view of their high speed and high frequency capability.
Whilst the TFTs are especially suitable for use in active matrix addressed display devices, they may, of course be used for other purposes.
Polycrystalline semiconductor TFTs, methods for their fabrication, and display devices incorporating such TFTs, in accordance with the invention, will now be described, by way of example, with reference to the accompanying drawings, in which:
Figure 1 is a schematic vertical section, not to scale, through an embodiment of a vertical configuration TFT according to the invention;
Figures 2a to 2e schematically illustrate various stages in the fabrication of the TFT of Figure 1;
Figure 3 is similar to Figure 2(e) but illustrates schematically an alternative processing step in the TFT fabrication;
Figure 4 is a plan schematic view of an active matrix addressed display device incorporating a plurality of transistors according to the invention used as pixel switching elements and as components of integrated drive circuits; and
Figures 5 and 6 show respectively a cross-sectional schematic view of another embodiment of TFT according to the invention which may be used as a pixel switching element in the display device of Figure 4 and a plan view of part of a pixel of the device of Figure 4 together with its associated TFT of Figure 4 and address conductors.
Referring to Figure 1, the vertical configuration TFT comprises a defined, unitary layer 10 of polysilicon material carried directly on the planar surface 11 of an insulative substrate 12, for example of glass. The polysilicon layer 10 is grown on the substrate surface by an LPCVD process and has a columnar structure, as indicated by the lines in Figure 1, with the grains of the material being generally elongate and rod-like with their principal axes, i.e. their largest dimension, extending generally normal to the substrate surface. The lines in the layer 10 in Figure 1 can be regarded as representing grain boundaries, these boundaries extending away from the substrate surface.
The polysilicon layer 10 is stepped to define two surfaces, or plateaus, 14 and 16 substantially parallel to the substrate surface. These surfaces 14 and 16 are offset with respect to each other laterally of the substrate surface and also vertically of the substrate surface with an edge of the layer extending between the two surfaces and forming a planar step 18 extending substantially perpendicular to the substrate surface. The polysilicon material immediately adjacent the step 18 provides the TFTs channel region 20, the length of the channel thus being determined by the height of the step 18.
Portions of the polysilicon layer 10 adjacent the surfaces 14 and 16 are doped to form n+ type surface regions 22 and 24 which constitute the main electrodes, that is source and drain electrodes, of the TFT. The doped regions 22 and 24 both extend up to the step 18, the one edge of the region 22 being aligned with the step 18.
A constant thickness insulator layer 26 of silicon oxide, or alternatively silicon nitride, extends continuously over the surfaces 14 and 16 and the intervening vertical step 18 and has windows therein overlying the surface regions 22 and 24 through which conductive layers 28 and 30, for example of metal such as aluminium, extend and contact the regions 22 and 24 to provide source and drain contact terminals. A metal gate electrode 32 is provided on the insulator layer 26 overlying the step 18 adjacent the channel 20 and extending parallel therewith.
In operation, with a gating voltage applied to the gate 32, current flow occurs between the source and drain electrodes 22 and 24 through the channel 20, the flow being represented by arrows in Figure 1. This current flow is mainly confined to the region of the channel closest to the step 18 whose depth, that is distance from the step, is equivalent to the thickness of perhaps one or two adjacent columns of grains as shown, although some current could also flow in grain columns further away from the step. In any event it will be appreciated that the number of grain boundaries transversed by the current through the channel region is considerably smaller than the number of boundaries which would be encountered if the channel region were to be oriented parallel to the substrate surface, as would be the case with a lateral type TFT.Because the grain boundary density is lower in the vertical direction than in the lateral direction, and the average grain size is larger in the vertical direction, a high carrier mobility is obtained, typically around ten times that normally obtained from a lateral type polysilicon device.
Since the source and drain doped surface regions 22 and 24 are formed integrally with the channel, that is, they comprise portions of a unitary layer formed by a single deposition, the possibility of operational deficiencies through interfacial defects between the channel and the source and drain, and particularly between the source doped region 22 and the channel 20, is avoided.
By way of illustration, the channel length may be around 1 Hm or less, and the thickness of the layer 10 at the source and drain regions, that is, the height of the surfaces 16 and 14 from the substrate surface, may be around 1 to 2ym and 0.1 to 0.2#lin respectively. The depth of the doped regions 22 and 24 may be around 0.05 to 0.151urn, the thickness of the region 22 being dependent on the thickness of the layer 10 at this area. The average grain size may be around 0.5 to lym in length and 0.1 to 0.2#im in width or diameter.
The structure of the layer 10 immediately adjacent the substrate surface 11 can normally be expected to differ from the remainder of the structure in that it consists of comparatively small size grains determined by nucleation sites when the layer is grown. The larger size grains are grown subsequently over these small grains. It is thought that this initial, small grain, region could extend around 0.054m from the substrate surface. The existence of this region is taken into account when selecting the thickness of the layer 10 at the source region.
This thickness is chosen to such that the proportion which is doped to form the source region comprises essentially a large grain structure. This avoids problems which might otherwise be expected when establishing contact if this region were composed of small grains.
Fabrication of the TFT will now be described with reference to Figures 2a-e. Polysilicon material is deposited on the glass substrate 12 by LPCVD at a deposition temperature of approximately 620 degrees centigrade using silane at a pressure of 140mtorr and a growth rate of approximately 1OOA/min. The layer thus formed has a columnar structure with < 110 > texture and, except for the initial very thin sub-layer of small grains produced immediately adjacent the substrate surface at nucleation sites, a mean grain size of around 7ooh.
A portion of the polysilicon material is subjected to an anisotropic etching operation using a mask to define the surface 14 substantially parallel with the remaining, original, surface 16, and the sharp vertical step 18, as shown in Figure 2a. The polysilicon material is then defined by etching to leave a rectangular island, 10.
A layer of silicon oxide 40 is deposited over the polysilicon material, Figure 2b, and an anisotropic etch process performed by which the oxide is removed apart from a generally wedge-shape spacer portion, 42, covering the step 18 and extending from the edge 18 over a part of the surface 14.
The structure is subjected to on-axis ion implantation, perpendicular to the substrate surface as indicated by the arrows in Figure 2c, using phosphorus dopant and then annealed at a temperature of around 600 degrees centigrade to produce the n+ type doped surface regions 22 and 24 to the required thickness.
The dopant has a tendency to spread laterally during implantation and creeps under the lower edge of the spacer portion 42 so that the inner edge of the doped region 22 is aligned as closely as possible with the step 18, the width of the spacer portion at its lower edge to this end being selected accordingly. Thereafter the oxide portion 42, which served also to protect the polysilicon material adjacent the step 18 from contamination during this doping operation, is then removed.
A fresh, low temperature, silicon oxide, or alternatively silicon nitride, layer 26 is then deposited completely over the exposed surface of the layer 10 and adjacent surface areas of the substrate 12 to a required thickness as determined by the requirement of the part of this layer overlying the step 18 to serve as the gate insulator. Two windows are opened in this layer 26 overlying respectively the regions 22 and 24, Figure 2d, after which a metal, for example aluminium, layer 43, Figure 2e, is deposited over the exposed surfaces of the structure. This layer 43 is selectively etched so as to leave source and drain terminals 28 and 30 in contact with the doped regions 22 and 24 and a gate electrode 32 overlying the step 18.These metal terminals 28, 30 and 32 are provided with integral extensions during definition which extend away from the layer 10 over the substrate surface to facilitate electrical connections to the source, drain and gate electrodes.
Finally, the TFT is subjected to a plasma hydrogenation operation for passivating grain boundaries.
It will be appreciated that various modifications are possible to the above-described TFT and its method of fabrication as will be apparent to persons skilled in the art. For example, the material of the gate electrode and source and drain contact terminals may be varied. Moreover, instead of using the metal contact 28 for the source an integral extension of polysilicon material may be formed at the source region integrally with the layer 10 during definition which extension is similarly doped, and in addition possibly metallised, to provide electrical connection with the source.
Figure 3 illustrates an alternative fabrication step in which the gate electrode is formed using a different technique to ensure that the ends of this electrode are spaced as far as possible from the source and drain electrodes, and hence that the possibility of capacitive coupling between the gate electrode and the source or drain electrode is minimised. In this method conductive material, for example aluminium, is deposited as layer 44 over the insulating layer 26 as previously. A layer of photoresist 46 is then deposited over the conductive layer 44 and subjected to highly directional illumination orthogonal to the substrate surface, as represented by the arrows in Figure 3.
Exposed photoresist material is then removed to leave a portion 47 overlying the step which, because of the highly directional nature of the illumination remained unexposed. The aluminium layer 44 is then etched to leave a gate electrode 32 whose one end is aligned closely with the upper surface of the insulating layer 26 and whose other end terminates closely to the corner between the step 18 and surface 14. Thereafter the portion 47 of photoresist is removed.
A plurality of the described TFTs may be formed simultaneously in any array using a common substrate 12 using a large scale integration technique. The TFTs can be arranged in any desired array, for example a matrix array consisting of rows and columns of TFTs as would be required for use as pixel switching elements in an active matrix addressed display device such as a liquid crystal, electrochromic or electroluminescent display device. The required interconnection between TFTs of the array and other components can conveniently be established during deposition of metal layers.For example, the source electrodes of all the TFTs in one column of a column and row matrix array may be interconnected via integral extensions formed simultaneously with the metal layer 43 or by using doped polysilicon material defined simultaneously with the layers 10 of the TFTs which is subsequently metallised. Likewise, the gate electrodes of all TFTs in one row of the matrix array can be interconnected via integrally-formed extensions of the electrodes 32. The pixel electrodes may be formed simultaneously with, and connected to respective ones of, the drain electrodes 30, which to this end may be formed of transparent conductive material such as ITO.
Figure 4 illustrates diagrammatically a typical example of a display device, utilising TFTs according to the invention. Such active matrix addressed display devices are generally well known and have been widely documented. For this.. reason it is felt unnecessary to provide a detailed description here. Briefly, however, and as shown in Figure 4, the TFTs, here designated by the reference numeral 54, share a common substrate 12 and are arranged in rows (l-m) and columns (l-n) with the source electrodes of the TFTs of each column and the gate electrodes of the TFTs of each row respectively being interconnected in column and row lines. The drain electrodes of the TFTs are connected to respective picture element electrodes 55 carried on the substrate adjacent to, and laterally spaced from the TFTs.These picture element electrodes 55 together with respective corresponding regions of a common electrode carried on a further glass substrate spaced from the substrate 12 carrying the TFTs, (the substrate 12 serving in this case as one substrate of the device), and display medium therebetween constitute picture elements. The actual display area of the device is indicated by dotted line 53 in Figure 4. The display medium may in this example comprise liquid crystal material. In operation, the rows of TFTs are repetitively and sequentially addressed. A scanning signal is applied to a row line to turn the TFTs in that row "on". When turned on, the TFTs form conductive paths between their source lines (columns) and their associated picture element electrodes. Simultaneously with each row being turned on, video information signals are applied to the appropriate columns which are passed through the TFTs of the "on" row and charge up the associated picture elements. When the row of TFTs is turned "off" upon cessation of gate line voltage, the video information voltages are maintained across the picture element until the next time that row is addressed, this being every field period.
Vertical polysilicon TFT as described previously are used in this embodiment for the pixel switching elements and in integrated driving circuits 56 and 57. These circuits are of conventional form in terms of their operation and accordingly, will not be described here in detail. Briefly, they comprise respectively a shift register circuit for sequentially addressing the gates of the TFTs of rows of the matrix array and video signal analogue shift registers/sample and hold circuits for providing line at a time serial to parallel conversion for addressing the columns of source-interconnected TFTs. Such addressing circuitry is incorporated on the substrate 12 with the
TFTs thereof being fabricated simultaneously with the pixel element switching TFTs.The TFTs of the addressing circuitry need to be fast and capable of high frequency operation more so than the picture element TFTs, and thus the vertical type TFT of the present invention is particularly beneficial for this purpose in view of their high mobility.
Figure 5 schematically illustrates, not to scale, a cross-section through another embodiment of TFT according to the invention which is intended for use particularly as a pixel switching element in the liquid crystal display device of Figure 4. Figure 6 is a schematic plan view of part a small, representiative, part of the liquid crystal display device showing the TFT of Figure 5 together with its associated pixel electrode and row and column address conductors.
Referring to Figures 5 and 6, this embodiment of TFT and its method of fabrication differ from that previously described as regards particularly the nature of the source, drain and gate electrodes by virtue of these electrodes being integrally formed respectively with the column address conductor, the row address conductor and the pixel electrode.
The TFT is fabricated by firstly depositing polysilicon material and defining the material to form an island 10, as described previously but with integral extensions 60 constituting a column address conductor. The island is then subjected to a doping operation using phosphorus to provide a doped, n+ type, surface region, part of which, adjacent the surface 16, constitutes the doped region 24. A layer of ITO is then deposited and defined to provide a drain contact 62 overlying the doped region 24, the pixel electrode 54 and an integral bridge portion 63. Thereafter, a portion of the island is anisotropically etched to define the surface 14, parallel with the surface 16 of the doped region 24, and the vertical step 18.
An oxide layer is then deposited and defined to form a side wall spacer, of similar form and function to that shown at 42 in
Figure 2b, alongside the step 18. A further doping operation is then performed to form the n+ type doped surface region 22 at the semiconductor region below the surface 14, the integral extension 60 being simultaneously doped at the same time. As a result of lateral spreading during implantation, the doped region 22 extends beneath the spacer and terminates in substantial alignment with the step 18. The spacer is then stripped away.
This is followed by the deposition of a low temperature oxide or nitride layer 66 and subsequent definition of this layer. The layer 66 is not shown in Figure 5 for the sake of clarity.
A layer of aluminium is then deposited over the oxide layer and defined by etching to provide a row address conductor 68, a portion of which extending adjacent the step 18 serves as the gate electrode 32. The row address conductor extends from the
TFT over the ITO bridge portion 63. Portions of this aluminium layer are used also to metallise the polysilicon extensions 60 constituting the column address conductor.
Although TFTs using polysilicon semiconductor material in particular have been described above, it is envisaged that other polycrystalline semiconductor materials formed having a columnar structure may be employed to similar advantage.
Claims (19)
1. A thin film transistor formed on a planar insulative surface and comprising a polycrystalline semiconductor layer, first and second spaced main electrodes separated by a portion of the semiconductor layer and a control electrode overlying said portion and separated therefrom by insulating material, which is characterised in that the polycrystalline semiconductor layer is a unitarily-formed layer having a columnar structure with grain boundaries extending generally normal to the insulative surface and comprises two surfaces which are substantially parallel to, and spaced from one another normally of, the insulative surface with a step extending therebetween, and at which the first and second main electrodes are respectively provided, and in that the control electrode extends adjacent the step and is spaced therefrom by insulating material.
2. A thin film transistor according to Claim 1, characterised in that the polycrystalline semiconductor layer comprises polycrystalline silicon material.
3. A thin film transistor according to Claim 2, characterised in that the thickness of the semiconductor layer portion defining the lower of the two parallel surfaces is at least around O.ljirn.
4. A thin film transistor according to any one of the preceding claims, characterised in that the semiconductor layer is doped at the regions of the two surfaces adjacent the step.
5. A thin film transistor according to Claim 4, characterised in that one end of the lower of the two doped surface regions is substantially aligned with the step.
6. A thin film transistor according to Claim 4 or Claim 5, characterised in that respective metal contacts are provided on the two doped surface regions.
7. A method of fabricating a polycrystalline semiconductor thin film transistor comprising the steps of forming on planar insulative surface a unitary layer of polycrystalline semiconductor material having a columnar structure with grain boundaries extending generally normal to the insulative surface and with first and second surfaces substantially parallel to the insulative surface and spaced from one another normally of the insulative surface with a step extending therebetween, forming respective main electrodes at the two surfaces of the semiconductor layer and providing a control electrode overlying and spaced from the step by insulating material.
8. A method according to Claim 7, characterised in that the semiconductor layer comprises polycrystalline silicon material.
9. A method according to Claim 7 or Claim 8, characterised in that the step of forming the unitary layer of semiconductor material comprises a low pressure chemical vapour deposition process.
10. A method according to any one of Claims 7 to 9, characterised in that the step of forming the main electrodes comprises doping regions of the semiconductor layer at the first and second surfaces adjacent the step.
11. A method according to Claim 10, characterised in that prior to doping the surface regions a protective layer is provided over the step and a part of the lower of the two surfaces immediately adjacent the step.
12. A method according to any one of Claims 7 to 11, characterised in that the control electrode is provided by the steps of depositing a metal layer on the insulating material which extends as a layer over the step, depositing photoresist material over the metal layer, subjecting the photoresist material to directional illumination substantially perpendicular to the substrate surface such that a portion of the photoresist material which extends parallel to the step remains unexposed, removing the exposed photoresist material, etching the metal layer and thereafter removing the portion of photoresist material.
13. An array of thin film transistors each according to any one of Claims 1 to 6, or as fabricated according to any one of
Claims 7 to 12, characterised in that the insulative surface is provided by a substrate common to all thin film transistors of the array.
14. An active matrix addressed display device comprising an array of display elements, and a plurality of thin film transistors, characterised in that the thin film transistors each comprise a transistor according to any one of Claims 1 to 6 or as fabricated according to any one of Claims 7 to 12, and in that the insulative surface is provided by a substrate common to the plurality of the thin film transistors.
15. An active matrix addressed display device according to
Claim 14, characterised in that at least some of the thin film transistors are associated with respective display elements of the device and are connected between the display elements and driving circuitry of the device.
16. An active matrix addressed display device according to
Claim 14 or Claim 15, characterised in that at least some of the thin film transistors comprises elements of the driving circuitry.
17. A thin film transistor substantially as hereinbefore described with reference to, and as shown in, the accompanying drawings.
18. A method of fabricating a thin film transistor substantially as hereinbefore described with reference to, and as shown in, the accompanying drawings.
19. An active matrix addressed display device substantially as hereinbefore described with reference to, and as shown in, the accompanying drawings.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB8926789A GB2239126A (en) | 1989-11-27 | 1989-11-27 | Polycrystalline semiconductor thin film transistors |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB8926789A GB2239126A (en) | 1989-11-27 | 1989-11-27 | Polycrystalline semiconductor thin film transistors |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB8926789D0 GB8926789D0 (en) | 1990-01-17 |
| GB2239126A true GB2239126A (en) | 1991-06-19 |
Family
ID=10666986
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB8926789A Withdrawn GB2239126A (en) | 1989-11-27 | 1989-11-27 | Polycrystalline semiconductor thin film transistors |
Country Status (1)
| Country | Link |
|---|---|
| GB (1) | GB2239126A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5693549A (en) * | 1994-09-13 | 1997-12-02 | Lg Semicon Co., Ltd. | Method of fabricating thin film transistor with supplementary gates |
| US5696388A (en) * | 1993-08-10 | 1997-12-09 | Semiconductor Energy Laboratory Co., Ltd. | Thin film transistors for the peripheral circuit portion and the pixel portion |
| US6670638B2 (en) * | 2000-09-25 | 2003-12-30 | Hitachi, Ltd. | Liquid crystal display element and method of manufacturing the same |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2139812A (en) * | 1983-05-12 | 1984-11-14 | Seiko Instr & Electronics | Thin film transistors with vertical channel |
| US4633284A (en) * | 1983-11-08 | 1986-12-30 | Energy Conversion Devices, Inc. | Thin film transistor having an annealed gate oxide and method of making same |
| EP0280370A2 (en) * | 1987-02-27 | 1988-08-31 | Philips Electronics Uk Limited | Thin film transistors, display devices incorporting such transistors, and methods for their fabrication |
-
1989
- 1989-11-27 GB GB8926789A patent/GB2239126A/en not_active Withdrawn
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2139812A (en) * | 1983-05-12 | 1984-11-14 | Seiko Instr & Electronics | Thin film transistors with vertical channel |
| US4633284A (en) * | 1983-11-08 | 1986-12-30 | Energy Conversion Devices, Inc. | Thin film transistor having an annealed gate oxide and method of making same |
| EP0280370A2 (en) * | 1987-02-27 | 1988-08-31 | Philips Electronics Uk Limited | Thin film transistors, display devices incorporting such transistors, and methods for their fabrication |
| GB2201544A (en) * | 1987-02-27 | 1988-09-01 | Philips Electronic Associated | Vertical thin film transistor |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5696388A (en) * | 1993-08-10 | 1997-12-09 | Semiconductor Energy Laboratory Co., Ltd. | Thin film transistors for the peripheral circuit portion and the pixel portion |
| US5693549A (en) * | 1994-09-13 | 1997-12-02 | Lg Semicon Co., Ltd. | Method of fabricating thin film transistor with supplementary gates |
| US6670638B2 (en) * | 2000-09-25 | 2003-12-30 | Hitachi, Ltd. | Liquid crystal display element and method of manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| GB8926789D0 (en) | 1990-01-17 |
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| WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |