GB2234375A

GB2234375A - Switching board for cutting off a dedicated processor from a communication bus

Info

Publication number: GB2234375A
Application number: GB9014069A
Authority: GB
Inventors: Giovanni Repetto; Mauro Nardini
Original assignee: Ansaldo SpA
Current assignee: Ansaldo SpA
Priority date: 1989-06-23
Filing date: 1990-06-25
Publication date: 1991-01-30
Anticipated expiration: 2010-06-25
Also published as: FR2648930B1; GB2234375B; IT8912533A0; GB9014069D0; IT1232649B; DE4019674A1; FR2648930A1

Abstract

A board SWI is inserted between an inter-processor communication bus MB and a processor SC, and is equipped with: - means for controlling the power supplies to the processor. - means for substantially cutting off a power supply to the processor, to enable its removal if its operation is found by a module SW DELTA to be defective, - means for resetting communications on the bus during the phases of insertion, removal and power supply cut-off, - means for storing initialisation information of the processor, and - means for transmitting this information once the processor has been reinserted.

Description

1 1 1 1 Switching board for use with a dedicated processor from the

communication bus of a computerised system comprising a plurality_of dedicated_processors The sub-ject-matter of this invention consists of a switching board of a dedicated processor from the communication bus of a computerised system comprising a plurality of dedicated processors.

Computerised systems consisting of a number of dedicated computers connected to one another in parallel by a communication bus are now widespread. Figure 1 shows a diagram of a system of this type which includes, generally, a communication bus (PSB) communicating with a series of dedicated processors (SC), which in turn are used for the management of single portions of a distributed-intelligence industrial plant through serial communication lines (bit-buses). In the case illustrated, the communication bus is of the type known commercial under Intel's name of Parallel System Bus.

A structure of this type, with independent processors, allows the functions to be split up while guaranteeing at the same time coordination towards the upper structure.of the hierarchy. The single processors (SC), for F P i 2 example, may be dedicated to several functional subassemblies of the plant, as stated above. The abbreviation 01 indicates equipment for communicating with the operator.

An arrangement of this type is undoubtedly interesting from the point of view of reliability, since the failure of one.module (SC) entails only the loss of a limited portion of the plant, which might not be vital, without compromising the operation of the remaining portions. Unfortunately, however, the functional independence stated above does not correspond to a true independence of an electrical nature.

This is because the single compressors (SC) are generally not designed to be physically disconnected from the communication bus (PSB) when this is live, and moreover this calls for a centralised power supply for the modules coming under its control.

In addition, in some cases these modules, if they are not insulated from the communication bus, may compromise its operativeness. This causes a considerable limitation of the actual availability of the communication system, and thus of the whole system, since:

i i 3 - with a single failed module the whole communication bus (PSB) can be rendered inoperative; - in order to remove and replace the failed module it is necessary to cut off the power supply to the whole communiation bus (PSB), and it is therefore necessary to repeat the whole system initialisation procedure.

According to the present invention, there is provided a switching board according to the appended claims, to which reference is directed.

In order to overcome said limitation to the availability of thh communication bus, according to the invention it is necessary for each dedicated processor (SC) to be connected to a communication bus, suitably modified and indicated hereinafter by the abbreviation (MB), by means of a switching board indicated hereinafter by the abbreviation (SWI).

Said switching board allows the power supply to be cut off from a single processor (SC), and consequently its removal from the modified communication bus (MB) without losing the functions controlled by the remaining dedicated processors (SC), with the solve interruption of parallel communication between the deactivated processor and those still connected. At the time of disconnecting the dedicated processor (SC), the switching bo,ard (SWI) remains powered, of course, and above all, it still retains the information needed to re- i 4 initialise the dedicated processor (SC) when this is reconnected.

Furthermore, for the whole period during which said processor remains connected but is out of order, said switching board continues to reset the output signals towards the communication bus, through the reset hardware of the processor by means of a so-called "kill board" signal.

Proper operation of the switching board requires the use of an auxiliary module, hereinafter called the switching module (SW), which has the purpose of detecting the fault in the processor (SC), communicating with the switching board, checking the power supplies and providing a physical support for the front-panel instructions and signals for the failed processor insert/remove logic. This is because the switching board preferably has no front panel, so that it uses that of said switching module as an external interface.

The switching module could as such be combined with the switching board if it were limited to the function described above. Actually, however, said switching module has other functions in addition to those just described, and is the subject matter of a parallel patent application by the same applicant, to which reference might be made.

The scope and advantages of the invention are indicated in the following description referred to forms of embodiment chosen by way of example with specific reference to the attached drawings, in which: - figure 1 shows a diagram of a computerised system to which an embodiment of the invention could be applied to advantage; - figure 2 shows a similar diagram to figure 1, but altered by the presence of a switching board.

Figure 1 has already been illustrated in the introductory part of the description.

in figure 2, a modified communication bus (MB) is shown instead of the communication bus (PSB). The modified communication bus (MB) is connected in parallel to (n) processors (SC1, SC2,..., SCn). Between each processor (SC) and the communication bus (MB) there is a corresponding switching board (SW11, SW12,..., SWIn). Between each processor (SC) and its corresponding switching board (SW) there is a also inserted a switching module (SWA1, SWA2,..., SWAn).

6 The typology of the signals between the communication bus, the switching boards, the processors and the switching module is described below, of course schematically:

(A) Signal used for the parallel dialogue between the communication bus (MB) and the processor (SC) to exchange data during normal operation of the processor (SC), (B) Signal used for the parallel dialogue between the communication bus (MB) and the switching board (SWI) for automatic initialisation of the processor (SC) after it is inserted. It should be remembered, in this respect, that the switching board is never removed from the communication bus (MB), and is therefore fed continuously for storage of the processor (SC) initialisation data, and for resetting the communications on the.bus during the stages of insertion, removal and power supplies cut off, by meaps of a dedicated signal (long-term bus error).

(C) Power supply from the communication bus (MB) and directed towards the processor (SC) through the switching board (SWI), so that it may be cut off by the 1 7 latter.

(D) Portion of the power line to the processor (SC) comprised between the processor (SC) and the switching board (SWI) which, if necessary, can cut it off.

(E) Transmission line for the initialisation signals, contained.in the switching board (SWI), to the processor (SC).

(F) Communication line between the switching board (SWI) and the processor (SC) for the transmission of a signal significant of the physical presence of the processor (SC) and for the transmission of the processor reset signal (kill board) in the event of defective operation.

(G) Communication line between the switching module (SWA) and the processor (SC) for diagnostic purposes, so as to evaluate when the switching board should step in (WATCHDOG, STOP, STOP EFFECTED, MASTER SC, INTERRUPT, functions the meanings of which are well known).

(H) Communication line between the switching module (SWA) and the switching board (SWI) to perform the lo- 8 gic functions associated with the operations for insertion and removal of the processor (SWITCHING PRESENT SWAPPING PRESENT - INSERTIREMOVE - PERMISSIVE) as well as those associated with the switching operations (KILL BOARD - POWER CORRECT EXCESS CURRENT - SC PRESENT).

The function of the switching module is therefore to: - detect.any upset of the processor (SC); - communicate with the switching board (SWI) to reset the processor (SC) and monitor the power supplies); - physically house the front-panel controls and signalling for the INSERT/REMOVE since the switching board will preferably have no front panel.

As already mentioned, the switching module has other functions, described in greater detail in a parallel application by the same applicant, to which reference might be made. As far as concerns the switching board (SWI), it is used for:

- resetting the processor (SC) detected as failed by the switching module (SWA) and controlling the power supplies; - cutting off the processor power supplies when this is detected as failed, in order to allow removal of the processor; i 1 9 - cutting off and reinstating the power supplies in order to allow reinsertion of the processor; - storing the processor (SC) initialisation information, so as to transmit it, after reinsertion of the processor so as to return it to an operational status; - generating the reset signal for communications on the bus (long-term bus error) during the remove/insert and power down/power up phases.

The foregoing embodiments of the present invention are described by way of example only and are not intended to limit the scope of the invention.

( h 1 Cl ai ms: 1) A switching board for use with a dedicated processor for cutting off said processor from a communication bus of a computerised system comprising a plurality of dedicated processors; characterised in that it comprises: (i) means for monitoring power supplies to the processors; (ii) means for detecting any defective operation of the processor; (iii) means for substantially cutting off power supplies to the processor, so as to enable removal of the processor when it has been detected as faulty; (iv) means for substantially resetting the processor during insert, remove, and no-power phases of operation; (v) means for storing at least a part of the processor's initialisation information; and (vi) means for transmitting said initialisation after the resertion of the processor.

2) A switching board for use with a dedicated processor for cutting off said processor from a communication bus of a computerised system consisting of several dedicated processors according to the foregoing claims; further characterised in that said switching board is associated with a switching module inserted between the processor and the switching board; in which said switching module is equipped with:

1 (i) means for detecting any defective operation of the processor; (ii) means for communicating with the switching board to send a reset signal to the processor when inserting and removing the latter; and (iii) means for communicating with the switching board to send a power supply contol signal.

3) A switching board for use with a dedicated processor for cuttIng off said processor from a communication bus of a computerised system consisting of several dedicated processors according to any preceding claim, further characterised in that: (i) said communication bus is linked to the processor by a line (A) for transferring information between the bus and the processor during normal operation of the processor; (ii) said communication bus is linked to the switching board by a line (B) for transmitting a signal used for automatic initialisation of the processor (SC) for reset- A 3 12 ting the communications on the bus during the insert, remove and power supply cut off phaseR of operation by means of a dedicated signal (long- term bus error), and a line (C) for transmitting a processor (SC) power supply; (iii) said switching board is linked to the processor by:

a line (D) for supplying power to the processor (SC) ' - a line (E) for transmitting to the processor (SC) initialisation signals, contained in the abovementioned storage means of the switching booard (SWI), a line (F) for transmitting a signal significant of the physical presence of the processor (SC) and for transmitting the signal (kill board) for resetting a defective processor, (iv) said processor is linked to the switching module by.

a line (G) for diagnostic purposes so as to determi ne when the switching board must step in; (v) said switching module is linked to the switching board by:

a line (H) for performing logic functions asso ciated with processor insertion and removal opera tions.

i i i 1 A a ( 1 13' 4. A switching board for use with a dedicated processor substantially as described herein and with reference to the accompanying drawings.

Published 1991 at Ibe Patent Oillce. State HOuse.66/71 High Holborn, London WCIR4TP. Further copies may be obtained from Sales Branch, Unit 6. Nine Mile Point. Cwmfelinfach, Cross Keys, Newport, NPI 7HZ. Printed by Multiplex techniques ltd. St Mary Cray, Kent.