GB2226445A - Silicon integrated circuit - Google Patents

Abstract

An integrated circuit including active areas (9) isolated by means of infilled trenches (15), is adapted by the provision of additional trenches (17). These latter trenches (17) extend down into the body of the substrate (11) and subdivide surface and near surface areas of highly doped or other conductive material (13) to reduce both radiative absorption and parasitic capacitance. The trenches (17) may be aligned parallel or orthogonal to interconnect metal or other metal track. Alternatively the trenches (17) may have a criss-cross or hexagonal pattern. Typically the trenches (17) may be of order 1 micron wide and spaced on a pitch of between 2 and 10 micron. <IMAGE>

Description

SILICON in INTEGRATED CIRCUIT The present invention concerns improvements in and relating to silicon integrated circuits, particularly, but not exclusively, circuits for microwave and other high frequency applications.

At high frequencies, circuit performance is limited, inter alia, by parasitic capacitance. Hitherto, gallium arsenide material technology has been advocated, for this material has excellent insulating properties and is therefore less prone to such parasitics.

In silicon technology this problem is more pronounced.

Most silicon integrated circuit processes leave a moderately or highly conductive layer at or near the surface of the silicon chip after processing. Means are provided for isolating this from the active circuit for direct current flow, but there remains the possibility of reactive current flow, i.e. capacitive parasitic 5. NIoreover, in some applications - e.g. in receivers, a radio frequency signal may be applied to the chip, from either the front or rear face. In this case any conductive layer within the silicon can represent a serious loss mechanism. This is especially pronounced in the case of rearward illumination.

A major source of loss is found in the "buried layer" that is commonly associated with the collectors of the circuit transistors.

This layer exhibits a "sheet" resistivity that can range between 0.1 ohm-cm and 1000 ohm-cm, and in practice 25 ohm-cm is becoming as E a standard. On the most modern processes, both bipolar and CMOS the buried layer is distributed non-selectively, and is pattern#ed to tbe transistor active array by a series of isolating "trenches" cut in the silicon substrate by etching techniques. Such a trench consists of an approximately vertical slot, usually cut by plasma etching, which is refilled by a thin layer of oxide on the trench walls and has an infill of high resistivity polysilicon.

Alternatively, oxide infill could be used. In some processes, a surface layer of epitaxial silicon is retained. This also is of relatively high conductivity and can contribute significantly to losses.

Losses are incurred both in microwave circuits and in conventional circuits due to parasitic capacitances of metal interconnect layers relative to the silicon substrate. Although both mechanisms are described as loss, they are essentially different; microwave losses are due to the presence of lossy conductive material in the microwave path, while lossy lines on the silicon suffer the parasitic to substrate. There will be a range of frequencies for a given set of process parameters where metal interconnect tracks act as waveguide, and hence loss will be a composite of these two mechanisms.

The present invention is intended as a remedy to the problems aforesaid. It serves to reduce radio frequency losses in silicon integrated circuits. Primarily it has application to circuits designed for operation at millimetre wave frequencies, but in. general, the principle and practice of the invention are applicable to circuits operable at much lower frequency.

In accordance with the invention thus there is provided a silicon integrated circuit comprising: a silicon substrate including a laterally extended region of heavily doped material at or near the surface thereof; a plurality of active areas defined in this silicon substrate, each isolated by means of a surrounding infilled trench, which trench extends downwards from the surface of this silicon substrate into the body thereof; wherein the silicon substrate is adapted by the provision of a multiplicity of laterally extending infilled trenches, which latter trenches are disposed between the surrounding infilled trenches aforesaid, and extend downwards from the surface of the silicon substrate into the body thereof to subdivide the laterally extended region of heavily doped material.

In the silicon integrated circuit above defined, the laterally extending infilled trenches serve to provide discontinuity between subdivided regions of the heavily doped, and thus lossy, material.

The effect thus is that this material exhibits a behaviour more akin to that of a dielectric medium than that of a conducting medium.

Absorptive and capacitative losses therefore can be effectively reduced by this provision.

The extending infilled trenches aforesaid may be arranged to extend in parallel and may be aligned to extend in the directions of interconnect conductors, or even orthogonal to these directions.

Various other configurations are possible, for example these trenches may be arranged in criss-cross manner or may be disposed in an hexagonal pattern. The latter pattern is advantageous in that it has a tendency to minimise the propagation of any defects generated during trench definition processing.

In the drawings accompanying this specification: Figure S in a cross-section views of a bipolar transistor of a typical design Figure 2 is a cross-section view of part of an integrated circuit showing trenches provided in accord with this invention; Figure 3 is a plan view showing an arrangement of interconnect track and extending infilled trenches; Figure 4 is a plan view showing an alternative arrangement to that of figure 3 above in which the extending infilled trenches are ordered in a criss-cross pattern; Figure 5 is a plan view of part of an integrated circuit showing the arrangement of trenches of figure 4 above in relation to an active area of the integrated circuit; and, Figure 6 is a schematic plan view showing an alternative arrangement of active areas and extending infilled trenches, the latter being arranged in an hexagonal pattern.

So that this invention may be better understood, embodiments thereof will now be described and reference will be made to the drawings aforesaid. The description that follows is intended by way of example, only.

A conventional bipolar transistor structure, part of a silicon integrated circuit is shown in figure 1. A transistor 1 comprising regions defining an emitter 3, base 5 and collector 7 is defined in the active area 9 of a silicon substrate 11. This substrate 11 is of p-type and underlies an extended layer 13 of epitaxially grown dopant enriched n-type material (n+). An infilled trench 15, which extends downwards from the surface into the body of the silicon substrate 11, is provided. This trench surrounds the transistor 1 and isolates the active area 9 of the circuit from adjacent areas of the chip. It will be noted that the layer 13 of dopant enriched material is not confined to just the active area 9 but is extensive across the whole silicon chip. It thus serves as a source of loss, both by radiative absorption and by providing capacitative structure.

Figure 2, 3 and 4 illustrate means for overcoming capacitative and absorbtive losses. Figure 2 illustrates an area on a chip remote from active transistor 1. A pattern of trenches 17, best seen on figures 3 and 4, separate subdivided regions of lossy material, so that material 13 acts more in the manner of a dielectric rather than a conductor. For microwave application, the trenches 17 are spaced at convenient intervals across the chip; with 1 micron wide trenches 17, spacings are from 2 microns pitch, limited by the process, up to 10 microns pitch, where loss again starts to rise. The trenches 17 may extend under metal conductors 19 or may terminate there (as shown). In the case of a lower frequency conductor, the trenches 17 are best located under and around conducting tracks 19 to reduce capacitance to substrate 11. Since much of this capacitance on narrow tracks 19 is caused by "fringing fields", it is important that the trenches 17 extend well outside of the track area 19.

The configuration of the trenches 17 may take several forms.

Thus parallel patterns, such as figure 3, may be used. Alternatively, a pattern orthogonal to the track 19 could be employed (not shown) or a "criss-cross" pattern (fig. 4) used. This latter is considered to be the best form from the aspect of loss, but may be problematic in terms of defects introduced into the silicon. Since defects tend to originate from straight tracks, a pattern of hexagonal trenches (fig.

6) could be defined, avoiding straight track runs but providing loss reduction similar to that of fig. 4.

To summarise, extensive patterns of "trench" isolation on a semiconductor chip may be used for the purpose of reducing signal losses in semiconductor material, either in buried layers or surface layers, at microwave and lower frequencies. Calculations have shown that this will be almost as effective as complete removal of the layers in those regions of the chip outside of the active areas 9. The advantage of this provision, however, is that standard processing techniques can be adopted.

Claims (6)

1. What I/We claim is:1. A silicon integrated circuit comprising:a silicon substrate including a laterally extended region of heavily doped material at or near the surface thereof; a plurality of active areas defined in this silicon substrate, each isolated by means of a surrounding infilled trench, which trench extends downwards from the surface of this silicon substrate into the body thereof; wherein, the silicon substrate is adapted by the provision of a multiplicity of laterally extending infilled trenches, which latter trenches are disposed between the surrounding infilled trenches aforesaid, and extend downwards from the surface of the silicon substrate into the body thereof to subdivide the laterally extended region of heavily doped material.
2. 2. A silicon integrated circuit, as claimed in claim 1, wherein adjacent active areas are connected by overlying metal track, and wherein the laterally extending infilled trenches are arranged parallel to said track.
3. 3. A silicon integrated circuit, as claimed in claim 2, including further laterally extending infilled trenches arranged orthogonal to those first mentioned.
4. 4. A s,')#con integrated circuit, as claimed in either of claims 2 or 3, wherein said laterally extending infilled trenches are on the order of 1 micron wide and are spaced with a pitch of between 2 and 10 microns.
5. 5. A silicon integrated circuit, as claimed in claim 1, wherein said laterally extending infilled trenches are configured in an hexagonal pattern.
6. 6. A silicon integrated circuit constructed adapted and arranged to perform substantially as hereinbefore described with reference to and as shown in any one of figures 2 to 6 of the accompanying drawings.