GB2223354A - Mounting semiconductor devices - Google Patents

Mounting semiconductor devices Download PDF

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Publication number
GB2223354A
GB2223354A GB8822962A GB8822962A GB2223354A GB 2223354 A GB2223354 A GB 2223354A GB 8822962 A GB8822962 A GB 8822962A GB 8822962 A GB8822962 A GB 8822962A GB 2223354 A GB2223354 A GB 2223354A
Authority
GB
United Kingdom
Prior art keywords
sheet
sheets
holes
semiconductor element
cavities
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB8822962A
Other versions
GB2223354B (en
GB8822962D0 (en
Inventor
Robert James Foulger
Simon Robinson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Marconi Electronic Devices Ltd
Original Assignee
Marconi Electronic Devices Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Marconi Electronic Devices Ltd filed Critical Marconi Electronic Devices Ltd
Priority to GB8822962A priority Critical patent/GB2223354B/en
Publication of GB8822962D0 publication Critical patent/GB8822962D0/en
Priority to DE3931996A priority patent/DE3931996A1/en
Priority to JP1253684A priority patent/JPH02244659A/en
Priority to FR8912738A priority patent/FR2637417A1/en
Publication of GB2223354A publication Critical patent/GB2223354A/en
Application granted granted Critical
Publication of GB2223354B publication Critical patent/GB2223354B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/1016—Shape being a cuboid
    • H01L2924/10162—Shape being a cuboid with a square active surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structure Of Printed Boards (AREA)
  • Wire Bonding (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Devices For Post-Treatments, Processing, Supply, Discharge, And Other Processes (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

An apertured sheet of ceramic is bonded to a base sheet of ceramic to form an array of open cavities, in each of which a semiconductor element (10) is mounted. The base sheet carries a pattern of electrically conductive tracks (5, 6, 7) to which the semiconductor element is connected and the tracks are connected to plated-through holes (41, 42, 43) extending through the thickness of the base sheet. The elements are then tested, and the cavities sealed with a common lid. The sheets are diced to form a plurality of separate devices, the sheets being cut along the center lines of the plated-through holes, so that the conductive surfaces thereby exposed can be used to mount the devices on printed circuit boards. <IMAGE>

Description

2r,2-5-554 I- Semiconductor Devices
This invention relates to semiconductor devices and in particular to a method of making them. For some applications, especially those which require a high performance specification to be met, a semiconductor element is mounted in a hermetically sealed package. Such packages are more complex and expensive than a conventional non-hermetic package, and have hitherto not been adopted on a wide scale. Moreover the nature of the hermetic packages previously used has not lent them to large scale production techniques.
The present invention seeks to provide an improved method of making a semiconductor device.
According to this invention a method of manufacturing a semiconductor device includes the steps of: forming a pattern of conductive tracks on a first sheet of green state ceramic; forming a plurality of apertures in a second sheet of inert insulating material; bonding the two sheets together by firing at a high temperature to form an array of cavities; and mounting a semiconductor element in each cavity of the array, such that the bonded sheets can subsequently be divided into portions each of which includes a cavity containing a semiconductor element.
In practice the two sheets could be of the same thickness, typically a sheet thickness is about 0.5mm so that the package eventually formed can be very thin. Preferably the second sheet is also green state ceramic. By mounting semiconductor elements, such as diodes in the array of cavities in a common sheet, the corresponding array of semiconductor elements can be automatically tested quickly and reliably without the need to individually position an elememnt with respect to a test probe. Furthermore, as the elements are tested in situ in their package, the integrity of the electrical connections to the contact portions of the package can be simultaneously tested.
After testing, a lid can be applied to seal each cavity so as to create a hermetically sealed enclosure. The lid may be a further layer of ceramic, or it may be, for example, a thin metal plate. The array is subsequently divided (or 'diced') into a large number of separate devices each of which comprise a package having a semiconductor element electrically and mechanically mounted within it.
Preferably external electrical contacts are formed on the outer edges of the first sheet of each device, in such a manner as to make electrical connections to conductive tracks present within each cavity. So that these contacts can be made before the array is diced, they are formed within small apertures extending through the first sheet, with each aperture being divided into two portions when the array is diced. This has the advantage that the electrical contacts are within the overall package outline, and so do not increase its size.
Such a process allows high reliability semiconductor packages to be processed effectively and economically in large quantities.
The invention is further described by way of example with reference to the accompanying drawings in which:
Figure 1 is a plan view of a semiconductor device, and Figure 2 is a schematic perspective view.
One example of a semiconductor device which is in accordance with the invention comprises a semiconductor element such as a diode or transistor which is mounted on an insulating substrate so as to be located within a cavity which can be subsequently sealed by means of a lid to form a hermitically sealed chamber.
Referring to the drawings the device consists of a base substrate sheet 1 of ceramic material, carrying a second sheet 2 of ceramic material having a regular array of rectangular apertures 3 formed therein. Both sheets 1 and 2 have a pattern of small holes 4 associated with each aperture 3. The base substrate sheet 1 is provided with a pattern of metallisation, in particular conducting regions 5,6,7, which are linked to holes 41,42, 43 having conductive side walls.
The method of making such a device is as follows. A large sheet 1 of green state glass ceramic, having a thickness of about 0.5mm is laser cut or punched to form a pattern of small holes 4. These holes 4 are not exactly circular, but are slightly eliptical having a cross-sectional dimension of about 0.6mm. Onto this layer 1, a conductive coating is formed, e.g. by screen printing of a thick film ink, so as to produce the required pattern having conductive regions 5,6 and 7.
A similar pattern of holes 4 is formed in the second sheet 2, which is also a sheet of green state glass ceramic having a thickness of about 0. 5mm. In addition the regular array of rectangular apertures 3 is formed in the sheet 2. These two layers 1 and 2 are aligned, and fired at a temperature of between 800'C and 900'C whilst pressure is applied so as to cure the green state ceramic and fuse the two layers to form a strong bond between them. The second sheet 2 forms a hermetic bond with the conductive ink as well as with the sheet 1. In principle the second sheet 2 could be formed of a glass preform or the like instead of a ceramic material. It will be seen that certain of the holes 4 are linked to the regions 5,6,7, and all of the holes 4, e.g. holes 41,42,43 are coated with such as nickel/gold or solder 9, a vacuum process being typically used to draw solder into the holes from a reservoir of molten solder.
Subsequently, a semiconductor component or element 10 is mounted within each cavity 3, the element 10 being typically bonded to the central conductive region 6. Additional electrical connections are made to the conuctive regions 5 and 7 by means of short gold leads 11 or the like which are bonded to the semiconductor element 10 and the regions 5 and 7.
The height of the semiconductor element is typically about 200 m (0.2mm) and so it is easily contained within the thickness of the sheet 2.
When a semiconductor element 10 is mounted within each cavity 3, the semiconductor devices so formed can be readily and reliably tested using the plated-through holes 41,42,43 as the means of making electrical connection for test purposes. At this stage any deflective semiconductor elements can be marked, and discarded at a later stage. As the cavities are formed in a large regular array, the testing of large numbers of devices is greatly expedited, as an automatic stepping tester can be used.
After testing, a lid 8 is laid over the sheet 2, and is sealed hermetically to the sheet 2 so as to form thereby an array of individually sealed cavities. The lid 8 can be ceramic, metal or glass, and a low temperature bond, i.e. well below 350' is used to bond it, as a high temperature process could risk damage to the semiconductor elements. In practice the lid 8 is likely to be a metal plate which is soldered on a pre-formed metallised rim surrounding each cavity. The attachment of the lid is done in an inert atmosphere which fills the cavities.
The array of semiconductor devices is divided into individual elements., i.e. diced, by means of a laser or diamond saw cutting through all three layers along the centre lines of the holes 4. The concave conductive surfaces of the holes are thereby exposed and these are used as the means of making electrical connection to a printed circuit board or the like on which such a semiconductor device can be surface mounted.
1

Claims (13)

1. A method of manufacturing a semiconductor device including the steps of: forming a pattern of conductive tracks on a first sheet of green state ceramic; forming a plurality of apertures in a second sheet of inert insulating material; bonding the two sheets together by firing at a high temperature to form an array of cavities; and mounting a semiconductor element in each cavity of the array, such that the bonded sheets can subsequently be divided into portions each of which includes a cavity containing a semiconductor element.
2. A method as claimed in Claim 1 and wherein said second sheet is also green state ceramic.
3. A method as claimed in Claim 1 or 2 and wherein the two sheets are of the same thickness.
4. A method as claimed in Claim 1, 2 or 3 and wherein said second sheet is provided with a pattern of holes surrounding each aperture.
5. A method as claimed in Claim 4 and wherein said first sheet is provided with a corresponding pattern of holes which aligns with the holes in the second sheet when the two sheets are bonded together.
6. A method as claimed in Claim 5 and wherein the holes in said first sheet are coated with a conductive material.
7. A method as claimed in Claim 6 and wherein the conductive material is solder.
8. A method as claimed in any of the preceding claims and wherein said conductive tracks are formed of a conductive ink.
9. A method as claimed in any of the preceding claims and wherein the semiconductor element is bonded to a said conductive track.
10. A method as claimed in Claim 9 and wherein the height of the semiconductor element is substantially less than that of the thickness of said second sheet.
11. A method as claimed in any of the preceding claims and wherein the semiconductor elements are electrically tested after they have been mounted in their respective cavities as an array.
-6
12. A method as claimed in Claim 11, and wherein subsequent to electrical testing, all cavities are closed by means of a common lid which is bonded to said second sheet so as to form closed hermetically sealed cavities.
13. A method as claimed in Claim 12 and wherein subsequent to the attachment of the lid, the sheets are diced to form a plurality of separate electrical devices.
Published 1990 atThe Patent Offtce, State House, 68171 Hip Holborn, London WC1R 4TP.Further Copies maybe obtained from The Patent OfficeSales Branch, St Mary Cray, Orpington. Kent BR5 310. Printed by Multiplex techniques ltd, St Mary Cray. Kent, Con. 1/87
GB8822962A 1988-09-30 1988-09-30 Semiconductor devices Expired - Fee Related GB2223354B (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
GB8822962A GB2223354B (en) 1988-09-30 1988-09-30 Semiconductor devices
DE3931996A DE3931996A1 (en) 1988-09-30 1989-09-26 SEMICONDUCTOR DEVICE AND METHOD FOR THE PRODUCTION THEREOF
JP1253684A JPH02244659A (en) 1988-09-30 1989-09-28 Manufacture of semiconductor device
FR8912738A FR2637417A1 (en) 1988-09-30 1989-09-29 PROCESS FOR THE INDUSTRIAL MANUFACTURE OF COMPOSITE DEVICES WITH CAVITY FORMATION, EACH OF WHICH CONTAINS A SEMICONDUCTOR ELEMENT

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB8822962A GB2223354B (en) 1988-09-30 1988-09-30 Semiconductor devices

Publications (3)

Publication Number Publication Date
GB8822962D0 GB8822962D0 (en) 1988-11-09
GB2223354A true GB2223354A (en) 1990-04-04
GB2223354B GB2223354B (en) 1992-10-14

Family

ID=10644513

Family Applications (1)

Application Number Title Priority Date Filing Date
GB8822962A Expired - Fee Related GB2223354B (en) 1988-09-30 1988-09-30 Semiconductor devices

Country Status (4)

Country Link
JP (1) JPH02244659A (en)
DE (1) DE3931996A1 (en)
FR (1) FR2637417A1 (en)
GB (1) GB2223354B (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4319944C2 (en) * 1993-06-03 1998-07-23 Schulz Harder Juergen Multiple substrate and process for its manufacture
JP3541491B2 (en) * 1994-06-22 2004-07-14 セイコーエプソン株式会社 Electronic components
US5832600A (en) * 1995-06-06 1998-11-10 Seiko Epson Corporation Method of mounting electronic parts
US5880011A (en) * 1996-06-19 1999-03-09 Pacific Trinetics Corporation Method and apparatus for manufacturing pre-terminated chips

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB997019A (en) * 1960-11-10 1965-06-30 Rca Corp Circuit microelement
US4568796A (en) * 1982-12-30 1986-02-04 Lcc.Cice-Compagnie Europenne De Composants Electroniques Housing carrier for integrated circuit
US4661181A (en) * 1984-05-25 1987-04-28 Thomson-Csf Method of assembly of at least two components of ceramic material each having at least one flat surface

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3926746A (en) * 1973-10-04 1975-12-16 Minnesota Mining & Mfg Electrical interconnection for metallized ceramic arrays
US4021839A (en) * 1975-10-16 1977-05-03 Rca Corporation Diode package
JPS5835367B2 (en) * 1978-07-18 1983-08-02 ミツミ電機株式会社 Circuit element board and its manufacturing method
JPS5980946A (en) * 1982-10-30 1984-05-10 Ngk Insulators Ltd Ceramic leadless package and its manufacture
IL78192A (en) * 1985-04-12 1992-03-29 Hughes Aircraft Co Mini chip carrier slotted array
US4790894A (en) * 1987-02-19 1988-12-13 Hitachi Condenser Co., Ltd. Process for producing printed wiring board

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB997019A (en) * 1960-11-10 1965-06-30 Rca Corp Circuit microelement
US4568796A (en) * 1982-12-30 1986-02-04 Lcc.Cice-Compagnie Europenne De Composants Electroniques Housing carrier for integrated circuit
US4661181A (en) * 1984-05-25 1987-04-28 Thomson-Csf Method of assembly of at least two components of ceramic material each having at least one flat surface

Also Published As

Publication number Publication date
GB2223354B (en) 1992-10-14
GB8822962D0 (en) 1988-11-09
FR2637417A1 (en) 1990-04-06
DE3931996A1 (en) 1990-04-05
JPH02244659A (en) 1990-09-28

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Legal Events

Date Code Title Description
732 Registration of transactions, instruments or events in the register (sect. 32/1977)
PCNP Patent ceased through non-payment of renewal fee

Effective date: 19930930