GB2222416A - Producing tungsten disilicide layers using disilane - Google Patents
Producing tungsten disilicide layers using disilane Download PDFInfo
- Publication number
- GB2222416A GB2222416A GB8919291A GB8919291A GB2222416A GB 2222416 A GB2222416 A GB 2222416A GB 8919291 A GB8919291 A GB 8919291A GB 8919291 A GB8919291 A GB 8919291A GB 2222416 A GB2222416 A GB 2222416A
- Authority
- GB
- United Kingdom
- Prior art keywords
- silicon
- layer
- tungsten silicide
- disilane
- layers
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 title claims description 38
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 title claims description 28
- 229910052710 silicon Inorganic materials 0.000 claims description 60
- 239000010703 silicon Substances 0.000 claims description 60
- 229910021342 tungsten silicide Inorganic materials 0.000 claims description 37
- 238000000034 method Methods 0.000 claims description 27
- 239000004065 semiconductor Substances 0.000 claims description 20
- 238000010926 purge Methods 0.000 claims description 11
- NXHILIPIEUBEPD-UHFFFAOYSA-H tungsten hexafluoride Chemical compound F[W](F)(F)(F)(F)F NXHILIPIEUBEPD-UHFFFAOYSA-H 0.000 claims description 9
- 238000000576 coating method Methods 0.000 claims description 8
- 239000011248 coating agent Substances 0.000 claims description 7
- 238000005229 chemical vapour deposition Methods 0.000 claims description 5
- 238000000197 pyrolysis Methods 0.000 claims description 5
- 238000011109 contamination Methods 0.000 claims description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 4
- 229910052721 tungsten Inorganic materials 0.000 claims description 4
- 239000010937 tungsten Substances 0.000 claims description 4
- 238000004320 controlled atmosphere Methods 0.000 claims description 2
- 238000005234 chemical deposition Methods 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 54
- 235000012431 wafers Nutrition 0.000 description 14
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 12
- 238000000151 deposition Methods 0.000 description 9
- 230000008021 deposition Effects 0.000 description 9
- 239000000758 substrate Substances 0.000 description 8
- 239000000463 material Substances 0.000 description 6
- 239000000126 substance Substances 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 239000011800 void material Substances 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000011261 inert gas Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 238000000137 annealing Methods 0.000 description 1
- 239000006227 byproduct Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- NTQGILPNLZZOJH-UHFFFAOYSA-N disilicon Chemical compound [Si]#[Si] NTQGILPNLZZOJH-UHFFFAOYSA-N 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 150000003377 silicon compounds Chemical class 0.000 description 1
- WNUPENMBHHEARK-UHFFFAOYSA-N silicon tungsten Chemical compound [Si].[W] WNUPENMBHHEARK-UHFFFAOYSA-N 0.000 description 1
- 238000013022 venting Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
- C23C16/54—Apparatus specially adapted for continuous coating
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
- C23C16/24—Deposition of silicon only
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
- C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
- C23C16/42—Silicides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32051—Deposition of metallic or metal-silicide layers
- H01L21/32053—Deposition of metallic or metal-silicide layers of metal-silicide layers
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- Chemical & Material Sciences (AREA)
- Engineering & Computer Science (AREA)
- Organic Chemistry (AREA)
- General Physics & Mathematics (AREA)
- General Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Mechanical Engineering (AREA)
- Metallurgy (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Inorganic Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Chemical Vapour Deposition (AREA)
- Electrodes Of Semiconductors (AREA)
Description
- 1 PROCESSES USING DISILANE 21_) f) i- L 24 '16 This invention relates to
processes using disilane to form layers of materials including silicon, tungsten silicide, and polycide.
Monosilane SiH 4 has been commonly used as a source of silicon in the production of films of silicon, silicon dioxide, and other silicon compounds used in the semiconductor industry, particularly with_chemical vapour deposition (CVD) equipment.
For production of silicon films, disilane Si2H 6 has been investigated as an alternative to monosilane. Recently, because of increased interest in the development of silicon solar cells, commercial quantities of disilane have become available because it was thought tht disilane would substantially increase the deposition rates for plasma-deposited silicon films used in solar cells. While this has not fully materialised, disilane was extensively studied as a possible candidate for production of atmospheric-pressure hydrogenated amorphous silicon.
Typical prior art applications for silicon films formed from disilane are on surfaces which are relatively flat, such as in solar-cell applications and such as in formation of epitaxial silicon layers on the surface of silicon wafers used in bipolar and CMOS semiconductor technologies.
Monosilane reacts with tungsten hexafluoride at a relatively low temperature to form tungsten silicide. Tungsten silicide can be combined with a top layer and a bottom layer of silicon to enclose a middle layer of tungsten silicide -to make a so-called polycide structure. These threelayer polycide sandwiches of silicon, tungsten silicide, and silicon are commonly used as conductive elements for semiconductor integrated circuits.
While tungsten silicide films can be formed with monosilane at relatively low temperatures, it has been found that such films- have inadequate step coverage and stress characteristics when a film must cover an integrated circuit having a complex topology with sharp external and re-entrant corners as well as steep gradients.
According to the invention there is provided a process for forming a tungsten silicide layer, comprising the step of reacting tungsten hexafluoride with disilane to produce a tungsten silicide layer.
Also according to the invention there is provided a process for forming a tungsten polycide sandwich on a semiconductor integrated circuit, comprising the steps of forming a first layer of silicon on said circuit; forming a layer of tungsten silicide over said first layer of silicon, said layer of tungsten silicide being formed by reacting tungsten hexafluoride with disilane; and forming a second layer of silicon over said layer of tungsten silicide.
The invention provides a process for forming silicon films having improved step coverage, smoother surfaces, and lower internal stress.
The invention also provides a process for -forming tungsten silicide films having improved step coverage, smoothness, and lower internal stress.
The invention also provides a process for forming polycide which is formed from silicon, tungsten silicide, and silicon, and which also has improved step coverage, smoothness, and lower internal stress.
The process of the invention uses disilane to form improved layers, or films, of silicon-containing material on sharply profiled surfaces. The silicon-containing materials can be silicon or tungsten silicide. Because of the improved characteristics of the layers provided by the process of the invention, the process is particularly applicable to forming layers of silicon or tungsten silicide on, for example, semiconductor integrated circuits. Layers, or films, produced with the process of the invention show improved step coverage. smoothness, and less internal stress than such layers produced by conventional processes using monosilane as a source of silicon.
Silicon layers formed on sharply profiled surfaces can be produced by pyrolysis of disilane on the sharply profiled surface, preferably at atmosheric pressue in a chemical vapour deposition system (APCVD). Tungsten silicide layers can be formed on sharply profiled surfaces by reacting disilane with tungsten hexafluoride at atmospheric pressure in a chemical vapour deposition system.
Tungsten polycide can be formed on a semiconductor integrated circuit by pyrolysis of disilane to produce the outer layers of the polycide. The inner layer of tungsten silicide is formed by reacting disilane with tungsten hexafluoride, preferably at atmospheric pressure in a chemical vapour deposition system. The semiconductor integrated circuit can be passed through a heated tunnel having adjacent coating chambers in which the layers are sequentially formed. To prevent contamination the semiconductor integrated circuit is passed through purging and exhaust regions located between the coating chambers. These regions have controlled atmospheres to prevent contamination of said layers. For example, this system prevents trace oxygen from forming native oxide on the silicon layers as a semiconductor integrated circuit is moved between coating chambers.
The invention will now be described by way of example with reference to the drawings, in which:- Fig. 1 is a cross-sectional view of a prior art semiconductor device showing a layer of silicon produced from monosilane;
Fig. 2 is a cross-sectional view of a semiconductor device showing a silicon-tungsten silicide-silicon polycide having silicon layers produced from disilane by a process according to the invention, but having a defective tungsten silicide layer produced from monosilane; Fig. 4 is a schematic diagram of a multistage conveyor system for an atmospheric-pressure chemical vapour deposition system for use in carrying out a process according to the invention; Fig. 5 is a cross-sectional view of a semiconductor device showing a silicon layer formed by a process according to the invention; and Fig. 6 is a cross-sectional view of a semiconductor device showing a polycide having one silicon layer and a tungsten silicide layer formed by a process according to the invention.
Fig. 1 shows a portion of a semiconductor device 10 including a substrate 12 on which is formed a circuit feature 14 having a sharply profiled surface with nearly vertical sides 15, 16 and sharply defined external corners 18, 20 and internal corners 22, 24. Overlying the substrate 12 and circuit feature 14 is a layer of silicon 26 formed from monosilane. As the silicon layer is formed the layer thickness varies as a function of position. In particular the internal corners produce angled, re- entrant portions 28, 29 in the silicon layer 26.
Fig. 2 is a cross-sectional view of a semiconductor device showing a portion of a polycide conductor 30 formed on a silicon substrate 32. A first silicon layer 34 is formed on the surface of the substrate 32 over a circuit feature 36 elevated above the surface of the substrate 32. Circuit features such as 36 require that a portion 38 of the silicon layer be able to be formed over sharply profiled surfaces, in this case, the step in the surface contour produced by the circuit feature 36. Pyrolysis of disilane in an atmospheric- pressure chemical vapour deposition APCVD system (described hereinbelow) produces silicon layers having good step coverage, as shown, as well as a smooth surf ace and less internal stress in comparison to silicon layers produced using monosilane as the_source material.
Fig. 2 also shows a prior art layer of tungsten silicide produced by APCVD from monosilane and tungsten hexaf luoride. Examples of equipment for conducting APCVD processes are discussed hereinbelow in connection with Figures 3 and 4. Note that the tungsten silicide layer has two parts 41a, 41b with a large void therebetween. The void appears to occur at a re-entrant corner of the layer, apparently caused by the inability of the silicon vapour produced from monosilane to coat such areas of sharply profiled surfaces combined with a tendency for stress induced cracks to form in this same area.
A top layer 44 of silicon is also produced from disilane in an APCVD system. This layer 44 smoothly covers the silicide layer 41a, b. In particular, the void betwen layers 41a and 41b is filled in, indicating that silicon vapours can effectively coat structures having recessed topologies.
Fig. 3 shows a conveyor APCVD system for forming films, or layers, using a process according to the invention. The system includes a furnace tunnel, or muffle, 54, which includes one or more deposition chambers 56, one of which is shown in Fig. 3. A conveyor belt 57 carries a semiconductor wafer 58 or device having one or more integrated circuits 58 formed there- upon into the tunnel 54 past flapper doors 59. An entry purge chamber 61a and an exist purge chamber 61b each have inert gases flowing outwardly past the flapper doors to essentially seal the interior of the tunnel 54 from the atmosphere. The conveyor belt 57 _carries a wafer to the deposition chamber 56 which is preceded by flapper doors 62 and a purge chamber 63a for confining the materials in the deposition chamber 56. Similarly, another purge chamber 63b with flapper doors follows the deposition chamber to confine materials to the deposition chamber 56. An indirect heating system includes electrical heating elements, typically shown as 66, for heating wafers to a desired temperature for a particular vapour deposition reaction. Chemicals flow into the chamber 56 and impinge on the surface of a wafer where they react and deposit an appropriate film, or layer. A precision bubble of chemical vapour is maintained within the chamber 56. Chemicals continuously feed the bubble and the purge flows isolate and confine those chemicals to the chamber 56. Reaction byproducts are removed by precision control of the venting of gases from the chamber 56 and the purge chambers.
Fig. 4 schematically shows a multi-stage conveyor APCVD sysem 70 which is set up for forming tungsten polycide by a process according to the invention. This system has been designed so that each coating chamber is independent-so that adjacent chambers do not interfere with or disturb each other because very small changes in pressure or flow within a chamber might cause variations in coating formation. This system also is designed to keep traces of atmospheric oxygen out of the system so that coatings of silicon or tungsten silicide can be formed without oxygen contamination. A silicon wafer is fed on a conveyor belt 74 into a furnace tunnel 76 adjacent to which are positioned a number of heater elements, typically shown as 78, for heating wafers to an appropriate temperature at each stage of the system. An entry purge stage 80 and an exit purge stage 82 each have inert gases flowing outwardly past appropriate baffles or flapper doors (not shown) to essentially seal the interior of the tunnel from the atmosphere.
An oxide-etching chamber 84 has appropriate chemicals flowing into it to perform a native oxide etch on the wafer surfacei This stage is followed by another purge/isolation stage 86. A precision bubble of chemicals at precisely controlled temperature, pressure, and flow rate is maintained in the chamber 84 and other chambers to be subsequently identified. The next stage is a silicon deposition chamber 88 in which a wafer is heated to approximately 500 degrees C and in which disilane is pyrolized to form a silicon layer on the wafer as it passes through the chamber. Another isolation stage 90 is followed by a tungsten-silicide chamber 92 in which disilane and tungsten hexafluoride react on a wafer heated to 360 degrees C to form a tungsten silicide layer over the layer of silicon deposited in chamber 88. After passage through another isolation stage 94, the wafer passes into a second silicon deposition chamber 96 in which the wafer is heated to 500 degrees C and in which disilane is pyrolized to form a silicon layer overlying the tungsten silicide layer. The wafer then passes through another isolation stage 98 and into an annealing chamber_before existing the furnace.
Fig. 5 shows an example of a layer of amorphous silicon 110 formed over a sharply profiled silicon dioxide layer 112 having 5 micron deep trenches 'formed therein. The silicon is deposited by pyrolsis of disilane and deposited over the steep stages formed by the trenches.
Fig. 6 is an example of a polycide formed on a silicon substrate 120 having a circuit feature 122 formed thereupon. A first silicon layer 124 is formed over the circuit feature 122 and on the silicon surface of the substrate 120. The substrate has had any residual native oxide removed, for example, in an oxide etching chamber such as chamber 84 shown in Fig. 4. The silicon layer 134 is formed by pyrolysis of disilane and forms a film having good step coverage over the sharply profiled circuit feature 122 as well as having a smooth surface and having low internal stress. A tungsten silicide layer 126 is 1 formed over the silicon layer 124 by reaction of disilane and tungsten silicide in an APM system such as shown in Fig. 4. This tungsten silicide layer 126, produced using disilane shows good step coverage and also has a smooth surface with low internal stress. This is in contrast. to the prior art tungsten silicide layer produced from monosilane as shown in Fig. 2, which had a large void at a re-entrant corner indicating stress cracking and poor step coverage characteristics. At this time it is not precisely understood why disilane produces superior silicon and tungsten silicide layers in comparison to layers produced from mofiosilane, particularly when formed in an APM system.
- 1 1 -
Claims (7)
- A process for forming a tungsten silicide layer, comprising the step of reacting tungsten hexafluoride with disilane to produce a tungsten silicide layer.
- 2. A process as claimed in Claim 1, wherein said reacting step is performed at atmospheric pressure in a chemical vapour deposition system.
- 3. A process as claimed in Claim 1 or Claim 2, wherein said tungsten silicide layer is formed on a semiconductor integrated circuit.
- 4. A process for forming a tungsten polycide sandwich on a semiconductor integrated circuit, comprising the steps of forming a first layer of silicon on said circuit; forming a layer of tungsten silicide over said first layer of silicon, said layer of tungsten silicide being formed by reacting tungsten hexafluoride with disilane; and forming a second layer of silicon over said layer of tungsten silicide.
- 5. A process as claimed in Claim 4, wherein said first and said second layers of silicon are each formed by pyrolysis of disilane.12 -
- 6. A process as claimed in Claim 4 or Claim 5, wherein said first and said second layers of silicon and said tungsten silicide layer are formed at atmospheric pressure by a chemical deposition process.
- 7. A process as claimed in Claim 6, including the steps of passing said semiconductor integrated circuit through a heated tunnel having respective coating chambers in which said layers are formed; and passing said semiconductor integrated circuit through purging and exhaust regions between said coating chambers and which have controlled atmospheres to prevent contamination of said layers.Published 1990 &tThe Patent Office. State House-66,71!Ti9hHc3burn. LondonWC1R 4TP. Further copies mWbe ob-Inedfrom The Patent Office. 1311e8 21an0h. St Mary Cray. Orpington. Kznt BR5 3RD. Printed by Multiplex tecliniques itd, St Mary Cray, Kent, COM V87
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US23882688A | 1988-08-31 | 1988-08-31 |
Publications (3)
Publication Number | Publication Date |
---|---|
GB8919291D0 GB8919291D0 (en) | 1989-10-04 |
GB2222416A true GB2222416A (en) | 1990-03-07 |
GB2222416B GB2222416B (en) | 1993-03-03 |
Family
ID=22899487
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB8919291A Expired - Fee Related GB2222416B (en) | 1988-08-31 | 1989-08-24 | Processes using disilane |
Country Status (4)
Country | Link |
---|---|
JP (1) | JPH02125875A (en) |
KR (1) | KR900003970A (en) |
DE (1) | DE3928765A1 (en) |
GB (1) | GB2222416B (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0648859A1 (en) * | 1993-10-14 | 1995-04-19 | Applied Materials, Inc. | Processes for the deposition of adherent tungsten silicide films |
DE19742972A1 (en) * | 1997-09-29 | 1999-04-08 | Siemens Ag | Method for forming a low-resistance interconnect area on a semiconductor substrate |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2674682B2 (en) * | 1994-07-15 | 1997-11-12 | キヤノン販売株式会社 | Film forming method and film forming apparatus |
JP2000294775A (en) * | 1999-04-07 | 2000-10-20 | Sony Corp | Manufacture of semiconductor device |
CN113061877A (en) * | 2021-04-02 | 2021-07-02 | 杭州中欣晶圆半导体股份有限公司 | High-cleanliness APCVD film forming equipment and film forming method thereof |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
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US4128670A (en) * | 1977-11-11 | 1978-12-05 | International Business Machines Corporation | Fabrication method for integrated circuits with polysilicon lines having low sheet resistance |
EP0071029A2 (en) * | 1981-07-30 | 1983-02-09 | International Business Machines Corporation | Method for fabricating self-passivated composite silicon-silicide conductive electrodes |
EP0183995A1 (en) * | 1984-11-02 | 1986-06-11 | Hitachi, Ltd. | Semiconductor device having a polycrystalline silicon interconnection layer and method for its manufacture |
EP0256337A1 (en) * | 1986-08-11 | 1988-02-24 | International Business Machines Corporation | Low pressure chemical vapor deposition method fpr forming tungsten silicide |
EP0295367A1 (en) * | 1987-05-22 | 1988-12-21 | International Business Machines Corporation | Gate structure in semiconductor devices |
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1989
- 1989-08-24 GB GB8919291A patent/GB2222416B/en not_active Expired - Fee Related
- 1989-08-30 DE DE3928765A patent/DE3928765A1/en not_active Withdrawn
- 1989-08-31 KR KR1019890012472A patent/KR900003970A/en not_active Application Discontinuation
- 1989-08-31 JP JP1226366A patent/JPH02125875A/en active Pending
Patent Citations (5)
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
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EP0648859A1 (en) * | 1993-10-14 | 1995-04-19 | Applied Materials, Inc. | Processes for the deposition of adherent tungsten silicide films |
DE19742972A1 (en) * | 1997-09-29 | 1999-04-08 | Siemens Ag | Method for forming a low-resistance interconnect area on a semiconductor substrate |
Also Published As
Publication number | Publication date |
---|---|
DE3928765A1 (en) | 1990-03-01 |
GB8919291D0 (en) | 1989-10-04 |
GB2222416B (en) | 1993-03-03 |
KR900003970A (en) | 1990-03-27 |
JPH02125875A (en) | 1990-05-14 |
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732E | Amendments to the register in respect of changes of name or changes affecting rights (sect. 32/1977) | ||
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PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 20000824 |