GB2218230A

GB2218230A - Programmable frequency divider

Info

Publication number: GB2218230A
Application number: GB8810571A
Authority: GB
Inventors: Thomas David Stephe Mcclelland; Nicholas Paul Cowley
Original assignee: Plessey Co Ltd
Current assignee: Plessey Co Ltd
Priority date: 1988-05-05
Filing date: 1988-05-05
Publication date: 1989-11-08
Also published as: GB8810571D0

Abstract

A fully programmable frequency divider for implementation in ECL comprises a plurality of D-type flip flops A-D each of which is clocked by the output of the preceding flip flop. Each flip flop has a transfer input for re-setting at the end of the cycle and two other inputs enabling the output (on re-setting) to be 1 or 0. The outputs of the flip flops are fed to a NOR gate. <IMAGE>

Description

PROGRAMMABLE ECL DIVIDER This invention relates to programmable Emitter Coupled Logic (ECL) dividers. Such dividers are known and are arranged to operate synchronously, each element of the divider chain of elements is clocked simultaneously by the clock input i.e. the frequency to be divided.

Each element of the chain of this type of divider is a D-type flip flop with extra inputs which allow the output to be set to "1" or reset to "0" when a transfer input is taken high. At the end of each cycle, a transfer pulse enables the set and reset inputs of each flip flop to program the outputs thereof to the desired levels for the start of a new cycle. Figure 1 of the accompanying drawings illustrates a known programmable synchronous divider, each element of the chain having set, reset and transfer inputs enabling the element to be programmed. The Q outputs of the elements are "NORRED" to provide the output of the divider which also supplies the transfer pulse.

Such a divider has the following disadvantage: (i) Each element of the chain must be capable of clocking at the maximum input frequency; (ii) If n elements are employed, the maximum division ratio is 2n: and, (iii) The programming sequence is not incremental.

The present invention is directed to fully programmable asynchronous dividers. Dividers of this kind have been used for some time in low frequency applications but have been based on MOS (Metal Oxide Silicon) and IIL (Integrated Injection Logic) technologies, where the gates are edge triggered.

It is an object of the present invention to provide a high frequency divider wherein the aforesaid disadvantages are overcome.

According to the present invention, there is provided an emitter coupled logic divider comprising a plurality of similar elements each in the form of a D-type divide-by-two flip flop, each element except the first, being clocked by the output of the previous element, and the outputs of the elements being gated to provide an output of the divider, each element having a set and a reset input and a transfer input arranged so that the set and reset inputs operate normally in one state of the transfer input and operate to program the output of the element in a second opposite state of the transfer input.

The invention will be described further, by way of example with reference to the accompanying drawings, in which Figure 2 is a block diagram of a four element fully programmable, asynchronous ECL divider in accordance with the present invention; and Figure 3 is a circuit diagram of each element of the divider of Figure 2.

As shown in Figures 2 and 3, a divider according to the present invention comprises four identical elements A, B, C, and D each in the form of a D-type flip flop. The flip flops are preferably of the master-slave type and have clock inputs CK (and also (not shown) anti-phase clock inputs CK). Similarly, the flip flops each have a transfer input TR (and, again, (not shown) an input TR). Each element A, B, C, and D also has a set input S and a reset input R. A Q output of each flip flop provides an input to the CK input of the next element of the chain and the Q outputs are also fed to a NOR gate 10.

The output of the NOR gate 10 provides an output pulse of the divider and also a transfer pulse at the end of each cycle to the transfer inputs TR.

Thus, each element A, B, C and D is a divide by two element and the four element divider has a maximum division ratio of 2n i.e. 24 =16.

At the start of each cycle, depending upon the inputs to the S and R inputs of each element, the Q outputs of each element can be set and hence any division ratio between 1 and 16 programmed into the divider.

Referring particularly to Figure 3, a circuit diagram is shown of each of the elements A, B, C, or D of the divider of Figure 2.

The circuit is based on ECL technology using npn transistors and, with associated diodes and resistors, can readily be fabricated on a silicon chip.

A D-type, divide-by-two master (M)/slave (S) flip flop is provided by transistors T1 to T14, diodes T15 and T16 resistors R1 to R4 and current sources I1 to 14. Clock inputs CK and CK would normally transfer input pulses to an output Q at half input frequency.

Set and Reset inputs are provided. However, instead of such inputs acting directly on the master flip flop M and the slave flip flop S, additional transistors As to A8 are provided arranged as differential pairs As, A6 and A7, A8 to which the Set and Reset inputs are differentially applied. Similarly, transistors A1 to A4 are provided to which transfer pulses TR and TR (provided by the output of the divider at the end of each cycle) are differentially applied.

-When TR is taken high with respect to TR, the circuit of Figure 3 operates as a normal divide by 2 D-type flip flop and the output at Q is at half the frequency of the input at CK. However, when TR is taken high relative to TR, the Set and Reset inputs are enabled.

Depending on the input levels applied thereto, the outputs of the master M and slave S can be programmed as desired (high or lox).

Thus, irrespective of the output of a proceeding stage, the latches of the master M and slave S can ue preset, each cycle, and miscounting can be prevented.

A fully programmable ECL divider as described in relation to Figures 2 and 3 is advantageous in that only the first element is clocked at the maximum frequency whereby the power consumption is greatly reduced. It will be seen also that a much greater division ratio is obtainable, 2n as compared with 2n. Moreover, the programming sequence is fully incremental, the outputs of the chain elements represent a true binary code of the division ratio used.

The invention is not confined to the precise details of the foregoing example and variations may be made thereto. For example, any desired number of elements can be provided to enable a desired division ratio to be obtained. Further, not all the elements of the chain need be of the fully programmable type shown in Figure 3.

The elements may be fabricated in npn or pnp form as desired.

Other variations are possible within the scope of the present invention.

Claims

1. An emitter coupled logic divider comprising a plurality of similar elements each in the form of a D-type divide-by-two flip flop, each element except the first, being clocked by the output of the previous element, and the outputs of the elements being gated to provide an output of the divider, each element having a set and a reset input and a transfer input arranged so that the set and reset inputs operate normally in one state of the transfer input and operate to program the output of the element in a second opposite state of the transfer input.

2. A divider as claimed in claim 1 wherein the gated output of the divider provides pulses to the transfer input.

3. A divider as claimed in claim 1 or 2 wherein the output of each element is fed to a NOR gate, the output of which constitutes the output of the divider.

4. A divider as claimed in any of claims 1 to 3 wherein transfer and NOT transfer pulses are provided by the gated output of the divider.

5. A divider as claimed in any preceding claim wherein each element comprises a D-type master-slave divide-by-two flip flop and wherein the set, reset and transfer inputs are applied to both the master and slave sections of the flip flop.

6. A divider as claimed in any preceding claim wherein a first differential pair is provided whereto the set and reset inputs are applied, the differential pair being enabled by the transfer pulses.

7. A divider as claimed in claim 6 wherein transfer and not transfer inputs are provided, the transfer and not transfer inputs being fed differentially to a second differential pair, one transistor of the second pair serving to enable the first differential pair.

8. A divider as claimed in claims 5 and 7 wherein a first and a second of the differential pairs are provided for each of the master and slave sections of the flip flop.

9. An emitter coupled logic divider substantially as hereinbefore described with reference to and as illustrated in Figures 2 and 3 of the accompanying drawings.