GB2217127A - Direct frequency synthesiser - Google Patents

Abstract

A direct frequency synthesiser comprises an accumulator or adder including a multiplicity of individual adder elements appertaining to the respective bits of a frequency setting input signal to be applied to the adder in operation of the synthesiser. Latches associated with the adder elements are operable in response to clock pulses to cause the adder to provide an incrementally varying added digital signal, Fig 2(a) which is applied to the gates of two sets of gates together with the outputs Figs 2(c), 2(d), from two D type flip-flop or bistable devices. The flip-flops or bistable devices have opposite polarity triggering characteristics, are connected in parallel, and have applied thereto the output from the adder element appertaining to the most significant bit of the frequency setting input signal Fig 2(b). The digital outputs from the respective sets of gates, Figs 2(e), 2(f) correspond to triangular waveform analogue signals in quadrature phase relationship with one another and are fed to respective digital-to-analogue converters which provide respective signal outputs at the requisite frequency set by the frequency setting input signal. <IMAGE>

Description

IMPROVEMENTS RELATING TO FREOUENCY SYSMIESIZERS This invention relates to frequency synthesizers. More especially, the present invention is concerned with direct frequency synthesizers of the general kind in which accumulator or adder means under the control of frequency setting input data and in response to the clock pulses provides an incrementally and cyclically varying address signal which is applied to memory means in which are stored a multiplicity of digital signals corresponding to individual samples of signal waveforms to be generated. The incrementally varying address signal applied to the memory means causes the requisite samples of waveform to be read out and fed to a digital- toanalogue converter which provides an output signal of the requisite frequency and waveform (i.e. sineware).

In many applications of such direct frequency synthesizers, especially radar and radio applications, the synthesizer is required to provide quadrature outputs (i.e. I and Q outputs having a 90" phase difference between them). For this purpose, the synthesizer will include two memory means having appertaining digital- to- analogue converters. For data re-timing purposes the synthesizer may include a number of registers into which data (e.g. frequency setting data) is latched in response to clock pulses before being applied to the adder means, memory means and the digital-to-analogue converters.

The synthesizer may be arranged to provide two output signals of the same frequency having a pre-determined phase relationship between them (i.e. sinewave and cosinewave).

Frequency synthesizers of the above general kind when fabricated in integrated circuit form consume an unduly large chip area and, moreover, due to ~ the access time required by the memory means (e.g. ROM) difficulties may arise in certain applications in operating the synthesizer at sufficiently high speeds.

The present invention overcomes the above- mentioned disadvantages by providing a direct frequency synthesizer comprising accumulator or adder means (i.e. full adder) including a multiplicity of individual adder elements appertaining to the respective bits of a frequency setting input signal to be applied to the adder means in operation of the synthesizer, latch means associated with the adder elements and operable in response to clock pulses to cause the adder means to provide an incrementally varying added digital signal which is applied to the gates of two sets of gating means together with the outputs from two D type flip-flop or bistable devices of opposite polarity triggering connected in parallel and having applied thereto the output from the adder element appertaining to the most significant bit of the frequency setting input signal to the adder means, in which the digital outputs from the respective sets of gating means correspond to triangular waveform signals in quadrature phase relationship with one another and in which the digital outputs are fed to respective digital-to-analogue converters which provide respective signal outputs at the requisite frequency set by the frequency setting input signal applied to the adder means.

By way of example the present invention will now be described with reference to the accompanying drawings in which: Figure 1 shows a schematic circuit diagram of a direct frequency synthesizer according to the invention; and, Figure 2 shows the waveforms of outputs at various points of in the circuit diagram of Figure 1.

Referring to Figure 1 of the drawings, the direct frequency synthesizer illustrated comprises a conventional digital adder (i.e.

full adder) or accumulator 1 which includes a multiplicity of digital adder elements 2 the number of which will be dependent upon the maximum number of bits defining a digital frequency setting input signal applied to the input bus 3 of the synthesizer. The digital adder 1 also includes clock controlled latches 4 located between the adder elements 2 with further latches 4 being provided in the respective outputs of the adder elements, the number of latches 4 in the respective outputs of the adder elements appertaining to the eight most significant bits of the frequency setting input signal (i.e.

229 - 222 - in present example) increasing by one as the bit significance of the appertaining adder element diminishes. This ensures data synchronisation of the inputs to gating means 5 and 6.

For the operation of the digital adder 1, clock pulses are generated by a clock signal generator 7, which preferably comprises a stable crystal-controlled oscillator having a frequency up to 3 GHz and applied simultaneously to all of the latches 4 of the adder 1 which accordingly operate to allow the bits of the frequency setting signal applied to respective adder elements 2 of the digital adder input bus 3 to be added together and to provide multiples of these added bits in response to successive clock pulses until the adder becomes filled and returns to zero.

Referring now to Figure 2 of the drawings this shows waveforms that occur at various points in the circuit arrangement of Figure 1. The sawtooth waveform (a) is an analogue representation of the summed output from the adder 1. The waveform (b) shows the phase of the most significant bit output (MSB) from the digital adder. Reverting to Figure 1 it can be seen that this output (b) is divided into two parallel paths one of which contains a conventional D type (D+) flip-flop or bistable 8, which triggers from the rising edges of the input data pulses whilst the other parallel path contains a conventional D type (D-) flip-flop or bistable 9, which triggers from the falling edges of the input pulses. The outputs from the respective flip-fIops 8 and 9 are shown as waveforms (c) and (d) in Figure 2 which are in quadrature relationship with one another.The flip-flop outputs together with the summed outputs of the adder drive respective groups of exclusive/OR gates 5 and 6. The digital outputs from the groups of gates 5 and 6 are shown in analogue form at (e) and (f) in Figure 2.

For the purpose of maintaining DC correctness the output from the gate 5 appertaining to the most significant bit and connected to the flip-flop 8 is inverted by an inverter 10 as shown.

The outputs from the groups of gates 5 and 6 thus produce digital representations of triangular waveforms which are adequate approximations to sinewaves without the need for a read only memory (ROM) which has been provided in known direct frequency synthesizers of the form previously described and which due to accessing time imposes a limitation on the speed of operation of the synthesizer and, moreover, occupied space on the integrated circuit.

As can be seen from Figure 1, the outputs from the group of gates 5 and 6 are applied to respective digital- to- analogue converters which are of conventional form, and one of which is shown at 11.

Each of the converters comprises current sources/switches 12-19 the current sources having the value of current sources indicated. The three most significant bits contain an array of four, two and one equal value current sources 12, 13 and 14 while the fourth most significant bit has a half value source 15. The second current source array containing the four least significant bits and comprising current sources of four, two, one equal and one half value source 16, 17, 18 and 19 connects to the array of current sources appertaining to the four most significant bits through a dual-current divider 20.

This current divider consists of an array of resistors providing the requisite current division characteristics. A full description of such digital-to-analogue converters and their mode of operation is described in IEEE Journal of Solid-State Circuits, VOL, SC-15, No.6, DECEMBER 1980. The converters also have clock- operated latches 4 in the input bus which couple the outputs from the groups of gates 5 and 6 to the current sources 12-19. The converter outputs are in quadrature phase relationship.

The converters convert the digital input signals from the gates 5 and 6 into triangular waveforms having the frequency determined by the frequency setting input signal applied to the digital adder 1.

The outputs from the converters are applied to the inputs of fast buffer amplifiers, such as the amplifier shown at 21 for converter 11. These amplifiers need only have a bandwidth sufficient for the output frequency (e.g. 500 MHz) although the clock frequency may be as high as 3 GHz. Moreover, the amplifier 21 need not be linear since square wave outputs are acceptable. The outputs I & Q from the converters are in quadrature relationship with one another.

Claims (8)

1. A direct frequency synthesizer comprising accumulator or adder means including a multiplicity of individual adder elements appertaining to the respective bits of a frequency setting input signal to be applied to the adder means in operation of the synthesizer, latch means associated with the adder elements and operable in response to clock pulses to cause the adder means to provide an incrementally varying added digital signal which is applied to the gates of two sets of gating means together with the outputs from two D type flip-flop or bistable devices having opposite polarity triggering characteristics connected in parallel and having applied thereto the output from the adder element appertaining to the most significant bit of the frequency setting input signal to the adder means, in which the digital outputs from the respective sets of gating means correspond to triangular waveform analogue signals in quadrature phase relationship with one another and in which the digital outputs are fed to respective digital-to-analogue converters which provide respective signal outputs at the requisite frequency set by the frequency setting input signal applied to the adder means.

2. A direct frequency synthesizer as claimed in claim 1, in which the output from a gate of one set of the gating means appertaining to the most significant bit of the adder output is inverted.

3. A direct frequency synthesizer as claimed in claim 1 or claim 2, in which the respective sets of gating means have gates appertaining only to the more significant bits (e.g. highest significant eight bits) of the frequency setting input signal to the adder means.

4. A direct frequency synthesizer as claimed in any preceding claim, in which each of the digital-to-analogue converters comprises two groups of current sources/switches corresponding to bits of diminishing significance and having corresponding diminishing current values.

5. A direct frequency synthesizer as claimed in claim 4, in which the two groups of current sources are connected together through a dual current divider.

6. A direct frequency synthesizer as claimed in any preceding claim, in which the outputs from the digital-to-analogue converters are applied to respective fast buffer amplifiers.

7. A direct frequency synthesizer as claimed in claim 6, in which the fast buffer amplifiers are non-linear and have relatively narrow bandwidths.

8. A direct frequency synthesizer substantially as hereinbefore described with reference to the accompanying drawings.