GB2216359A - Television signal synchronisation coding - Google Patents

Abstract

Video data is transmitted by means of a system which splits out 2 synchronisation signals from the information signal and then codes the synchronisation information in such a way that all the synchronisation information for each particular field is held in a small portion of that field and is transmitted in the form of a short code. At the receiver the code is detected and decoded such that synchronisation is re-established. Without knowing the correct timing and coding an unauthorised user is unable to re-establish synchronisation and thus a meaningless signal is obtained. <IMAGE>

Description

Synchronisation This invention relates to a method of synchronisation between two units which are separated by, for example, an RF link or a cable. In particular, but not exclusively, it relates to a method for synchronising video signals between a video camera/RF transmitter and a receiver.

Video data is generally transmitted as a series of fields or frames each comprising a number of lines. In order that the receiver can make sense of the information transmitted, it clearly must be able to determine the start of each field and each line. This is known as field and line synchronisation (sync). It is normally achieved by the provision of field and line sync pulses which are transmitted at suitable intervals along with the video data.

If video is to be transmitted in a secure manner, i.e. one in which only an authorised receiver can view the information, then some form of coding of the signal is required. However, the sync information must still be present in the coded signal so that correct synchronisation can be achieved after decoding. In addition to coding of the video, it is preferable that the synchronisation information should also be coded for greater security and also that such coding should be protected against transmission impairments such as noise, fading, ghosting etc., all of which can degrade the quality of the final image produced at the receiver.

A method of synchronisation according to the present invention thus enables video or other data to be securely transmitted to a receiver and also allows for bandwidth reduction and the capability of transmitting colour signals.

According to the present invention there is provided a method for transmitting data of the type comprising information signals and synchronisation signals, comprising: separating out the synchronisation signals from the information, compressing the synchronisation information in such a manner that all the synchronisation information for each particular time period is held in a small portion of that time period and transmitting sequentially in a fixed time period the synchronisation signal and information signal.

In a preferred embodiment, the data is video data comprising a plurality of lines of video information forming a field of information, and line and field sync signals superimposed.

The sync information for each field may be transmitted in the form of a short digital code. A receiver may be adapted to set up a timing circuit independent upon the code and thus to re-establish synchronisation, which may then be combined with a transmitted video signal to provide recombined video data.

Embodiments of the invention will now be described by way of example only with reference to the accompanying drawings in which: Figure 1 shows schematically the transmission of secure video data; Figure 2 shows a circuit adapted to secure the synchronisation data from a video signal; Figure 3 shows video waveforms before and after coding; Figure 4 shows a synchronisation decoding circuit; and, Figure 5 shows a circuit which can be used to reduce the effects of jitter on a received signal.

Referring to Figure 1 video information is received from a camera 1 in the form of a standard video signal.

Such a signal is shown in Figure 3a which includes, in addition to the video information, field sync edges F and lines sync pulses L. In a typical 50Hz system, the period of each field is 20 milliseconds and there are 3121 lines within each field. This signal is broken down into separate video and synchronisation (sync) components in a separator stage 2. Such units are common in the art. The separate signals are applied to respective units 3 and 4 for subsequent processing such as bandwidth reduction or video enhancement. Furthermore the sync encoding, as will be further described, is achieved in unit 4. The video and sync data are then recombined for transmission over an RF link. This is shown as an RF link for convenience, but may alternatively be a cable or fibre optic link.

Complimentary processing takes place upon reception so that the signals may be combined in a standard form for presentation to a T.V. display, video recorder, or circuitry adapted to further process the data.

Figure 2 shows in more detail the sync encoding unit 4. In this unit, the sync having been separated from the video is further separated into line L (15KHz) and field F (50Hz) components. The line component L is delivered to a phase locked loop (PLL) 6 which is arranged to generate a clock waveform at a high frequency, typically 3MHz. This is used to drive a counter 7 which is in turn reset every line by a signal from the PLL in synchronism with line pulses. Counter 7 feeds an eight bit counter 8 which is pre-loaded with any desired pattern. In this case the pattern 11001001 has been chosen as an example.

The separated field sync information F in the form of field sync edges (Fig. 3a), is applied via a delay 9 to the enable input of the eight bit counter 8, from which it will be seen that the pattern held on the counter is enabled only for one line in every field. The delay line 9 is arranged such that the output from the counter, which contains all the line sync information in a coded form, is output, on each fieldlon the first line after the leading edge of the field pulse. This is shown more clearly in Figure 3b where the signal at A represents the field pulse edge and that at B represents the line sync informa.ion, which only lasts for one line but includes within this line an 8 bit code 11001001.An OR gate 10 combines the line and field components and a low level 3MHz clcck compcnent signal from PLL 6 is added to produce the sync waveform shown in Figure 3b, which iE a tristate wavefcrr only containing line sync information on the two lines following the field sync edge. This sync signal may now be added to the video signal from which it waC originally separated to produce the composite signal shown in Figure 3c.As is shown in Figure 3c a low level tone ccde has also been added to the video data and it is seen that it is very difficult for an unauthorised person who receives this data te be able to differentiate the sync information fror the video information.

Upon reception it wil be cpprecicte-d that it is essential the coded sync is re-converted to standard sync information in order that the transmitted data can be viewed by an authorised recipient. Figure 4 shows a circuit for achieving this deccding.

Referring to Figure 4, after the coded sync has been removed from the composite signal, which is achieved by waiting for a suitable field edge, then the 3MHz low level tone is extracted by a tuned circuit 11 and applied to a high Q PLL, 12 which is adapted to produce a waveform of typically 20MHz. Meanwhile, the leading edge A is detected 13 and applied via a delay 14 to the enable pin of an eight bit shift register 15 which is clocked by, a suitable division 16 of the signal from the PLL 12. By using suitable inverters such as inverter 17 on the outputs of the shift register then at the end (:' sequence E, i.e. 11001001 in this case, the outputs fron shift register 15 are all low.These are fed to a comparator 18 such that the shiit register and comparator tc.gether act as an 8 bit correlator. The output from this ccrrelator, which is in the form of a pulse, is fed to an AND gate 1, together with the signal P + B from code detector 2C, which is delayed by US as shown at 21.Thus, an edge "R" is produced which contains the phase information for both line and field sync Pulse R is used to reset respective counters 22 and 23 Which are fed in series by the PLL and frorr which, respectively, line sync and field sync is obtained.

It will be seen that the timing incertainty of the system of Figure 4 is determined by the PLL frequency (20MHz). Thus a jitter of 50 nanoseconds will be observed Such inaccuracy is acceptable for system such as monochrome T.V., but for cther uses such as colour T.V.

the jitter must be further reduced. Figure 5 shows a convenient apparaus for reducing the jitter by a factor of at least ten.

In the apparatus of Figure 5 the line sync pulses are fed via a delay 24 to a ramp generator 25. The output of the ramp generator is sampled by pulse R to produce a d.c.

voltage component on a holding capacitor 26. This component is filtered with typically a one Hz filter 27, which thus achieves a smoothing or averaging function, and fed as one input to a comparator 28. The ramp voltage, via a variable delay 29 is used as the other input to the comparator. It will be seen that the output edge of the comparator is now a jitter reduced version of the incoming line sync.

Once it has been established that the "R" pulse and line sync are coincident it is desirable to inhibit the resetting of the line sync counter. This may be achieved by a simple detector 30 via a delay 31 of ten or more field periods (200ms or more).

Claims (8)

1. Apparatus for transmitting data of the type comprising information signals and synchronisation signals, comprising; means for separating the synchronisation signals from the information signals, means for coding the synchronisation signals in such a manner that all the synchronisation information for each particular time period is held in a small portion of that time period and means for transmitting sequentially in a fixed time period the synchronisation signal and information signal.

2. Apparatus as claimed in Claim 1 adapted for use with video data comprising a plurality of lines of video information forming a field of information and line and field synchronisation signals super-imposed.

3. Apparatus as claimed in Claim 2 wherein the compression means comprises a store for holding a digital code, and timing means, responsive to the synchronisation signals, to cause the store to output the stored code during a known time period within each field.

4. Apparatus as claimed in Claim 3 including further timing means for enabling the code only for one line in every field.

5. Apparatus as claimed in Claim 3 or Claim 4 wherein the timing means includes a phase locked loop actuated in dependance upon the line synchronisation pulses, and a delay means.

6. Apparatus for receiving a signal of the type transmitted by apparatus according to any of claims 1 to 5, comprising means for detecting the start of the coded signal, means adapted to give a first signal when the complete coded signal has been received and means for generating synchronisation pulses in dependance upon the first signal.

7. Apparatus as claimed in Claim 6 wherein the means of generating a first signal in response to the coded signal comprises, a shift register of equal number of parallel outputs to the coded signal and having invertors on one or more of its outputs, the arrangement of the invertors being such that when the coded signal has been fed sequentially into the shift register, the outputs, after any inversion, are all of the same magnitude and sign; and a comparator adapted to provide an output pulse if the outputs from the shift register are all of the same magnitude and sign.

8. A receiving circuit substantially as described with reference to, and as illustrated by, the accompanying drawings.

8. A transmitting circuit substantially as hereinbefore described with reference to the accompanying drawings.

9. A receiving circuit substantially as described with reference to, and as illustrated by, the accompanying drawings.

Amendments to the claims have been filed as follows 1. Apparatus for transmitting data comprising information signals and line and field synchronisation signals, which apparatus comprises means for separating the synchronisation signals from the information signals; means for transmitting the information signal and, in a fixed time period once per field or frame a coded signa] at a time determined by one or more synchronisation signals and; means for continuously transmitting a fixed rate clock tone at a level substantially lower than that of the information and coded signals.

2. Apparatus as claimed in Claim 1 wherein the clock signal is a 3 MHz signal.

3. Apparatus as claimed in Claim 2 wherein the compression means comprises a store for holding the digital code and timing means, responsive to the synchronisation signals, to cause the store to output the stored code during a single known time period within each field.

4. Apparatus as claimed in Claim 3 wherein the timing means includes a phase locked loop actuated in dependance upon the line synchronisation pulses, and a delay means.

5. Apparatus for receiving a signal of the type transmitted by apparatus according to any of claims 1 to 5, comprising means for extracting the clock tone, means for detecting the start of the coded signal, means adapted to give a first signal when the compete coded signal has been received and means for generating synchronisation pulses in dependance upon the first signal and the clock tone.

6. Apparatus as claimed in Claim 6 wherein the means of generating a first signal in response to the coded signal comprises, a shift register of equal number of parallel outputs to the coded signal and having invertors on one or more of its outputs, the arrangement of the invertors being such that when the coded signal has been fed sequentially into the shift register, the outputs, after any inversion, are all of the same magnitude and sign; and a comparator adapted to provide an output pulse if the outputs from the shift register are all of the same magnitude and sign.

7. A transmitting circuit substantially as hereinbefore described with reference to, and as illustrated by, the accompanying drawings.