GB2211988A

GB2211988A - Current matching of bipolar transistors

Info

Publication number: GB2211988A
Application number: GB8725688A
Authority: GB
Inventors: Jeffrey Peter Harris
Original assignee: STC PLC
Current assignee: STC PLC
Priority date: 1987-11-03
Filing date: 1987-11-03
Publication date: 1989-07-12
Anticipated expiration: 2007-11-03
Also published as: GB8725688D0; GB2211988B

Abstract

In an integrated circuit, current matching of a plurality of bipolar transistors is effected by the provision of polysilicon emitter resistors 17 one for each transistor. The resistor values are determined so as to provide matching. Oxide isolation of the resistors may be employed to give a very compact arrangement. The integrated circuit may also include field effect transistors. <IMAGE>

Description

IMPROVEMENTS IN INTEGRATED CIRCUITS.

This invention relates to integrated circuits, and in particular to current matching of bipolar transistors in such circuits.

In an integrated circuit incorporating high current bipolar transistors it is generally necessary to provide some means of matching the currents carried out these transistors. In general, current mismatch arises from voltage drops along the supply and ground rails of the circuit as a result of the electrical resistance of these rails.

This is a particular problem where a high rrt trarsi#tor str#ctu#-e compLiseb d umber or similar transistors connected in parallel. Current mismatch can result in current hogging by one or more transistors with consequent reduction in the electrical performance of the circuit.

Typically, current matching is achieved by resistor ballasting of the transistor emitters, the values of the ballast resistors are chosen such that the currents through the transistors are matched.

Conventionally, the ballast resistors require implanted or diffused regions each formed on a separate resistor island or isolation land. This arrangement is comparitively bulky and provides a severe limitation on the density of integration that can be achieved.

The object of the invention is to minimise or to overcome this disadvantage.

According to the invention there is provided an integrated circuit, including a plurality of bipolar transistors, and polysilicon emitter resistors one for each said transistor, and wherein the relative values of the resistors are such that, in use, matching of the currents carried by the transistors is provided.

the arrangement is of particular advantage in integrated circuits incorporating both CMOS and bipolar devices.

An embodiment of the invention will now be described with reference to the accompanying drawing in which: Figure 1 is a schematic diagram of a portion of an integrated circuit; and Figure 2 is a schematic diagram of the circuitry associated with the transistor of Figure 1.

Referring to the drawings, Figure 1 shows part of an array of adjacent npn bipolar power transistors in an integrated circuit. The transistors are disposed between supply rails lla, lib and a ground rail 12, each rail comprising e.g. a metal track. The supply rails are coupled to the collection of the transistors via cu 1. dse current is supplied to the transistors via a further pair of metal tracks 14c, 14b provided with base contacts 15.

The transistors are provided with polysilicon emitters 16. Typically the transistors are formed by a process as described in our UK Specification No.

2,174,244 (P.D. Scovell et al 15-13-8 Div A). The emitter of each transistor is coupled to a polysilicon ballast resistor 17 via a metallisation 18. The ballast resistors 17 are coupled to the ground rail 12 via contacts 19. The polysilicon forming the ballast resistors is deposited on oxide (not shown) so that electrical isolation is provided between the base metal lines 14a and 14b and the resistors. The resistors can thus be disposed over the transistor collector resulting in an efficient use of chip area. The value of each polysilicon resistor is determined by its width which in turn is determined by the particular patterning of the mask used to define these resistors. The manner in which this is performed can be seen from reference to Figure 2 of the drawings.It can be shown that the difference between adjacent ballast resistors Rn and Rn+l is given by the expression

where Rbm and Rem are the base and emitter metal resistive increments respectively and m is the total numbers of emitters. The average voltage drop across the ballast resistors should be chosen high enough so that the emitters operate at the same current densities but not so high as to effect the overall saturation voltage.

Ballast resistor voltage drops of 50mV are suitable.

As the polysilicon resistors are oxide isolated and no separate resistor isolation land is required, the arrangerant is very compact. IL will be appreciate that this technique may be employed in integrated circuits consisting either of bipolar devices only or of a mixture of bipolar and field effect devices.

Claims

1. An integrated circuit, including a plurality of bipolar transistors, and polysilicon emitter resistor one for each said transistor, and wherein the relative values of the resistors are such that, in use, matching of the currents carried by the transistors is provided.

2. An integrated circuit as claimed in claim 1, wherein said transistors are polysilicon emitter transistors.

3. An integrated circuit as claimed in claim 1 or 2, wherein each polysilicon resistor is disposed on an oxide layer.

4. An integrated circuit as claimed in claim 1, 2 or 3, and further includong field effect transistors.

5. An integrated circuit substantially as described herein with reference to and as sohwn in the accompanying drawing.