GB2209079A - Multi-processor system initialisation - Google Patents

Abstract

Functional means (10, 12, 14) are controlled by a system including working units (11, 13, 15) in the form of micro-controllers having inter-integrated serial bus inter-faces and of like form except for means establishing dedication, wherein address allocation to each unit (11, 13, 15) is effected from a main central processor (16) through a single serial channel (18A, 18B, 18C) connecting the units in series by way of their reset terminals (11R, 13R, 15R) and output terminals (11T, 13T, 15T), the initialisation of the first unit (11) being executed by the main CPU removing the reset signal from the reset terminal (11R) and each subsequent unit (13, 15) being initialised in turn from the output terminal (11T, 13T) of the preceding unit by removal of the reset signal from the reset terminal (13R, 15R) of the unit when an initialisation routine of the preceding unit ends, address allocation being effective only during or on termination of the initialising routine of each unit. <IMAGE>

Description

APPARATUS FOR UTILISING PROCESSORS This invention relates to an apparatus (herein called the main apparatus) comprising a plurality of operational means each required to perform a respective function (which may be different in respect of each of the operational means or common to some or all of them) beginning at co-ordinated starting times and for this purpose controlled by a control system, the latter comprising at least one central (computer) processing unit (herein called the main CPU) and a plurality of slave (computer) processing units (herein called working units), associated respectively with the operational means, and communication means establishing communication between the main CPU and the working units to enable the latter to receive and transmit signals appropriate to their functions for bringing about operation of their respectively associated operational means.Such apparatus is herein called apparatus of the kind specified.

One of the objects of the present invention is to provide, in an apparatus of the kind specified, a control system which, is capable economically of meeting the requirements of a number of different forms of main apparatus especially in respect of the numbers of operational means embodied therein and in respect of different types of operational means.

Another object of the invention is to enable the working units to be controlled from the main CPU without the necessity to employ a large number of channels in the communication means e.g. conductors in the bus means connecting the main CPU with the working units and devoted exclusively to addressing the latter. Further it is an object to avoid the necessity to employ a large number of terminals on each working unit thereby freeing such terminals for other purposes e.g. permitting other signals to be transmitted thereto or received therefrom for the purpose of determining or controlling the functions performed by the working units in respect of their associated operational means.

According to the invention there is provided an apparatus of the kind specified wherein wherein at least a plurality of the working units each includes an initialising means having an input terminal requiring a first predetermined signal state to be established thereon to initialise the working unit and an output terminal on which a corresponding state is also established at the end of an initialising routine performed by the unit after establishment of said first state, the working units being arranged to be initialised in sequence by a channel (herein called the serial chain channel) provided by the communication means effectively establishing a chain of communication starting from the main CPU to the input terminal of a first one of the working units and continuing to the input terminal of each successive working unit from the output terminal of the preceding one of the working units.

The term n initialising" and its derivatives is used herein in the manner conventionally understood in the art to mean conversion of the working unit concerned from a state in which entities therein during operation are required to attain given (but possibly varying) electrical potentials to an initial state in which they have respective predetermined starting potentials. In particular but not exclusively one form of initialising routine is one in which an address means included in the working unit is brought into a condition in which it is able to be set to respond to a predetermined address code transmitted to it from the main CPU and will respond exclusively to that code.

The invention will now be described with reference to the accompanying diagrammatic drawing which shows schematically an apparatus of the kind specified embodying three operational means of the main apparatus respectively associated working units and a main CPU.

The apparatus may be in the form of a vending machine and whilst a wide variety of operational units may be incorporated it is mentioned by way of example that the first operational unit 10 may be a card reader for reading a card, herein called a club card, inserted into, or swiped through a suitable slot in the machine by a user and embodying a record member. The card may carry a record of the identity of the user and of various data items applicable to the type of main apparatus, goods vended, class of user, site of apparatus and other matters. It could be programmed to record a credit of a given amount applicable to that user and that card, it being assumed that the user will have prepaid the amount in question to some suitable receiving station. The purpose of the operational means 10 is to render the machine usable by the particular user inserting the card.

As a possible alternative the operational means 10 may comprise a coin- receiving device which, in response to insertion of a coin or coins of the appropriate denomination or denominations renders the machine usable.

In yet another arrangement the operational means 10 may be a printer and for convenience in the following description it will be assumed to be such.

The operational means 12 may comprise a credit register for reading the credit still available to the user and possibly provided with means for decrementing this credit as a function of the number of vends for which a particular club card has been used by insertion into the operational means 10.

The operational means 14 may comprise a means for rendering articles for vending or renting available to the user either by unlocking a locked compartment containing the article or moving the compartment between a position in which the article is accessible and can be taken out by the user or replaced when necessary and â position in which the article is not so accessible.

It will be understood that other operational means may be provided which have been omitted for simplicity, for example means indicating what articles are present or the number of any given articles present, and means indicating whether the user has correctly operated the machine and possibly displaying instructions to facilitate correct operation.

Associated operatively with each of the operating means 10, 12 and 14 is a working unit, these being designated 11, 13 and 15. Each may comprise a microcontroller with a serial bus interface and which may be of the type designated Mullard I2 C. Referring to the working unit 11 (I2 C) this integrated circuit unit includes an address means llA settable by an appropriate address allocating input signal to establish any one of a plurality of addresses for the working unit 11. The unit further includes a plurality of functional means llA, llB, llC, llE, llF, which can be hard wired on the board containing the I C integrated circuit unit each to perform certain of the functions required to bring about operation of the means 10, 12, 14.In each working unit only one of the functional means llB to llF will be so wired and that one will be connected appropriately (e.g.

by hard wiring) to the address means llA, or 13A, or 15A as the case may be to be brought into operation when the 2 address means is correctly addressed. Thus the I C units incorporated in the working unit or boards 11, 13, 15 can be of common form (identical) leading to considerable economy in their provision.

Corresponding address means 13A, 15A and functional means 13B-13F and 15B-15F are provided respectively in the working units 13 (I 2C) and 15 (I 2 C) except that (as mentioned) the functional means able to be brought into 2 2 use on the units 13 (I C) and 15 (I C) and selected by appropriate wiring are different in these units as required by the different characters of the operational means 12 and 14. Not all of the functions to be performed by the operating units 10, 12, 14 will normally be brought about or controlled solely by the selected functional units llB, 13C and 15D as indicated schematically by the hard wiring links 10A, 12A, 14A established through interface means 22A, 23A, 24A and by the controlling hard wiring links llG, 13G, 15G from the address means llA, 15A to the selected functional means llB, 13C, 15D. Signals from supplementary functional means included in the main CPU will usually be required to achieve full performance of the intended functions of the operating means. For example when the operating means 10 is a printer the working unit 11B may contain the paging, line spacing, word spacing and similar "housekeeping" functions but the signals providing the text or graphics will usually be derived from a supplementary functional means in the main CPU. Once the main CPU has correctly addressed the unit 11 this will serve not only to access the supplementary signals to the functional means llA and operating means 10 but because the supplementary functional means in the main CPU is uniquely functionally associated with the means in the CPU providing the correct address signal this will ensure that these supplementary signals are supplied to and effective in only the unit 11.

The working units are controlled as to their time of operation by a main CPU 16. The address and functional signals from the main CPU are conveyed through bus means 18 which is shown in double lines to signify that it contains a plurality of separate conductors. In the present case there may be five conductors one of which, acting as a serial chain channel, is for convenience shown separately at 18A, 18B, 18C and 18D.

The remaining conductors of the bus means are shown as having links 19, 20, 21 interfacing with respective address means and functional means of the working units and may be allocated to the functions respectively of data, clock signal, 0-volt (common), and 24-volt transmission.

There will now be described how a working unit is initialised and thereby placed in a condition to receive and transmit an address signal along the conductor 18A forming the first part of the serial chain channel of the bus means 18. All of the units are held initially in a "reset" state "O" and are sequentially released one at a time. This is achieved by removing the reset signal from the input terminal which is the reset terminal of the working unit (designated llR for the unit 11). Until the reset signal has been removed from the input terminal the working unit is incapable of subsequently receiving or transmitting any instructions.

When the reset signal has been removed from terminal llR of the first working unit this unit starts an initialising routine by means incorporated in it for this purpose and it is then in a state to transmit and receive information, address codes, and other data to and from the main CPU 16. All other working units are not so capable until they have been initialised and performed their respective initialising routines.

The establishment of an address in the address means llA, 13A, 15A, of each 1 2 C unit can be brought about in alternative ways.

In the first (simpler) way the main CPU 16 includes means for storing in effect a table comprising address codes and functional signals. Thus a plurality of (different) address codes will each pertain to a particular form of operating means e.g. printer, display means, etc. The correlation i.e. association between a particular address code and a particular form of operating means may be established by ensuring that each address code is followed (when the apparatus is in full operation) uniquely by signals providing the functions supplementing those brought about by the functional means of the working unit appropriate to the associated operating means e.g., an address code furnished by the main CPU for a working unit controlling a printer would be correlated, i.e. followed, by signals bringing about printing of textual information, (the function means llB for example providing the paging etc. function).

Thus in address allocation by this first mode, initialisation of unit 11 would be followed by transmission to it of the address code pre-stored in the main CPU 16 and which is correlated with the supplementary functional data appropriate to a printing means.

The store means for the pre-stored address codes of the main CPU would be assigned to output (i.e. furnish) these in the sequence of initialising the units 11, 13, 15 etc. This requires that the units 11, 13, 15 have to be connected in the bus conductor 18A, 18B, 18C in the proper (physical) sequence. This may not always be convenient and the second way of establishing addresses is more flexible.

In this second embodiment of the invention, although the various operating means still require to be brought into operation in a predetermined order, the various I2 C working units 11, 13, 15 controlling them can be connected in the bus in any order.

The main CPU 16 has (as before) means for storing a plurality of (different) address codes respectively associated with means for furnishing (from store means) supplementary function signals appropriate to respective (companion) functional means e.g. llB, 13C, 15D.

After initialisation of any working unit, say 11, it is arranged to transmit to the main CPU an identification signal which identifies the functional means e.g. llB which has been selected (by the hard wiring configuration) as appropriate to control the operating means 10 e.g. a printer. The main CPU 16 includes means for recognising the identification signal and, in response to receipt of the identification signal, thereafter transmitting to the address means of the working unit 11 that address code which is associated with the proper supplementary signal store e.g. one furnishing supplementary printing signals.

Thus in operation as each working unit is initiated its address means can have set into it the proper address appropriate to its selected functional means irrespective of the (physical) position of its connection in the bus means.

Reverting to the initialisation routine, at the end of the initialising routine performed by unit 11 (after allocation and transmission of its address code from the main CPU 16) the output terminal llT is caused to remove the reset signal via channel 18B from the input terminal 13R of the next succeeding working unit 13. At this stage unit 11 will have been given its operative address and consequently only unit 13 will perform an initialising routine and will then receive from the main CPU its operative address code, or transmit a function identity signal to, and thereafter receive (its own distinctive) operative address code from, the main CPU 16.

Subsequent, sequential initialising of the working unit 15 initiated from output terminal 13T of unit 13 occurs in a like manner.

Thus address codes can be simply and easily allocated to the working units without utilisation of more than one channel in the communication means thus greatly simplifying the hardware of the main CPU and working units and the software for any given form of main apparatus and mode of operation.

Although the communication means to establish 2 initialisation of the I C units 11, 13 and 15 in sequence preferably utilises only a single channel in the form of a conductor i.e. comprising the wires 18A, 18B, 18C it would be possible for the communication means to comprise a radio link in which similarly only a single channel need be used. Further, it is within the scope of the invention for the bus means to be in the form of a ring from which sub-links such as 19, 20, 21 interface with respective working units instead of an open-ended chain as illustrated. This however would not apply to the serial chain channel 18A, 18B, 18C.

It will be apparent that each working unit such as 11 and its associated operational means 10 can be brought into operation in sequence although the operations of these units may overlap in real time.

Communication may be bi-directional along the bus means 18 from each of the working units which can signal its state and enable the main CPU to recognise and if need be monitor and signal the function performed by the associated operational means 10, 12 and 14 as the case may be.

The control system is thus extremely flexible in the sense that it can be readily adapted economically to meet the requirements of a wide variety of different forms of main apparatus.

Further the employment of a single conductor 18A, 18B, 18C incorporated in the bus means to provide a serial communication channel for initialising each working unit in sequence permits other conductors in the bus means and other terminals on each working unit to be utilised for other purposes, that is feeding input and output signals to the main CPU or to the associated operational means 10, 12 and 14 as the case may be.

Claims (8)

1. An apparatus of the kind specified wherein at least a plurality of the working units each includes an input terminal requiring a first predetermined signal state to be established thereon to initialise the working unit and an output terminal on which a corresponding state is also established at the end of an initialising routine performed by the unit after establishment of said first state, the working units being arranged to be initialised in sequence by a channel (herein called the serial chain channel) provided by the communication means effectively establishing a chain of communication starting from the main CPU to the input terminal of a first one of the working units and continuing to the input terminal of each successive working unit from the output terminal of the preceding one of the working units.

2. Apparatus according to Claim 1 wherein each working unit includes function identification means providing, as part of the initialisation routine, for transmission of a function identity signal to the main CPU identifying the function to be performed by the working unit and its associated operation means.

3. Apparatus according to Claim 2 wherein the main CPU includes means for allocating an address code to each working unit transmitted thereto by the communication means in response to operation of the function identification means of the working unit concerned.

4. Apparatus according to any one of the preceding claims wherein some or all of the working units intrinsically embody means to carry out all of the functions required by different kinds of the operational means included in the apparatus, but include dedication means establishing that each such working unit will perform only one of such functions.

5. An apparatus according to any one of the preceding Claims wherein the input terminal is the reset terminal of the working unit concerned.

6. An apparatus according to any one of the preceding Claims wherein the communication means comprises a multiconductor bus in which a single conductor provides the serial chain channel.

7. Apparatus according to any one of the preceding Claims wherein each of the plurality of working units comprises a micro-controller with an inter-integrated serial bus interface.

8. Apparatus substantially as hereinbefore described with reference to the accompanying drawing.