GB2272083A - Serial interface expansion/multiplexing. - Google Patents
Serial interface expansion/multiplexing. Download PDFInfo
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- GB2272083A GB2272083A GB9222583A GB9222583A GB2272083A GB 2272083 A GB2272083 A GB 2272083A GB 9222583 A GB9222583 A GB 9222583A GB 9222583 A GB9222583 A GB 9222583A GB 2272083 A GB2272083 A GB 2272083A
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- data
- computer system
- central processing
- processing means
- data set
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
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- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Mathematical Physics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Information Transfer Systems (AREA)
Abstract
An interface apparatus (1) to interface several serial computer peripheral devices to a single computer system (2) via the computers expansion slot (23). The interface apparatus includes an interface circuit (15) connected to the expansion slot, a central processing unit (11) connected to the interface circuit, and a plurality of asynchronous transmission units (191 - 194) which connect the central processing unit to the required device. <IMAGE>
Description
APPARATUS FOR INTERFACING A PLURALITY OF SERIAL
COMPUTER PERIPHERAL EQUIPMENTS AND A COMPUTER SYSTEM
The invention relates to an interface device, more particularly to an apparatus for interfacing simultaneously more than two serial computer peripheral equipments and a computer system.
A conventional computer system is usually provided with two serial RS-232 communication ports, thus permitting the connection of two serial computer peripheral equipments thereto.
Some fully automatic systems require more than two serial computer peripheral equipments in order to accomplish the desired functions. These computer peripheral equipments include a coin receiving unit, a bar code reading device, a magnetic card reading device, a touch-operated monitor and a printer. For example, when a car is to be parked in an automatic car parking system, the driver has to pay a basic fee before a gate of the car park is opened. Upon payment of the basic fee, a bar-coded stub, which states the entry time thereon, is printed and is provided to the driver. When leaving the car park, the bar-coded stub is fed to the bar code reading device, and the computer of the car parking system calculates the additional fees to be paid. The required additional fees are then displayed on the monitor.The gate of the car park is opened only after the additional fees have been paid.
Another example of a fully automatic system which uses the above-mentiqned computer peripheral equipments is an automatic movie ticket vending machine.
Although the operation of such fully automatic systems seems simple, such systems do not have a simple construction. Note that the printer can be connected directly to the printer port. The computer system, however, has only two serial ports, making it impossible to connect the remaining computer peripheral equipments to a respective serial port if the fully automatic system requires four or more serial computer peripheral equipments.
One solution to the above problem is to use time division multiplexing to connect the computer peripheral equipments and the computer system. However, such a solution requires a complicated operating software and is relatively slow if a large number of computer peripheral equipments are available.
Therefore, the objective of the present invention is to provide an interface apparatus which utilizes the expansion slot of a computer system to permit the simultaneous interfacing of more than two serial computer peripheral equipments and the computer system.
Accordingly, the interface apparatus of the present invention is used to interface a plurality of serial computer peripheral equipments and a computer system and comprises:
an asynchronous transmission unit connected to each of the computer peripheral equipments, said asynchronous transmission unit generating a first interrupt signal and storing a first data set from the corresponding computer peripheral equipment in an internal data register thereof when the corresponding computer peripheral equipment wishes to send the first data set to the computer system;
a central processing means receiving the first interrupt signal, said central processing means determining which one of the asynchronous transmission units has generated the first interrupt signal and reading the internal data register of the asynchronous transmission unit which generated the first interrupt signal; and
an interface circuit provided on an expansion slot of the computer system and connecting electrically the central processing means and the computer system, said interface circuit being controlled by the central processing means to provide the first data set to the computer system;
said interface circuit generating a second interrupt signal and receiving a second data set from the computer system when the computer system wishes to send the second data set to one of the computer peripheral equipments, said second interrupt signal being received by the central processing means so as to enable the central processing means to receive the second data set, said central processing means activating the asynchronous transmission unit which corresponds to said one of the computer peripheral equipments and providing the second data set to said one of the computer peripheral equipments via the corresponding asynchronous transmission unit.
Other features and advantages of the present invention will become apparent in the following detailed description of the preferred embodiment, with reference to the accompanying drawings, of which:
Figure 1 is a schematic circuit block diagram of the preferred embodiment of an interface apparatus according to the present invention; and
Figures 2 to 4 are schematic electrical circuit diagrams which illustrate portions of the interface apparatus of the present invention.
Referring to Figure 1, the preferred embodiment of an interface apparatus (1) according to the present invention is shown to comprise a CPU (11), a random access memory (RAM) unit (13), an interface circuit (15) , a switch panel (17) and an asynchronous transmission means (19). The interface circuit (15) is provided on an expansion slot (23) of a computer system (2) in order to effect electrical connection with the computer CPU (21). The computer system (2) is operated in accordance with a software driver routine (25) in order to activate the interface apparatus (1) and permit bidirectional data transmission. The switch panel (17) is operated in order to select which ones of the serial computer peripheral equipments (not shown) are to be used.
The asynchronous transmission means (19) is connected to the serial computer peripheral equipments, such as a touch-operated monitor, a magnetic card reading device, a bar code reading device, a coin receiving unit, etc., which should be connected to the serial communications port of the computer system (2).
Whenever one of the serial computer peripheral equipments wishes to send data to the computer system (2), the asynchronous transmission means (19) will transmit an interrupt signal to the CPU (11). The CPU (11) responds by sending a set of queries to the asynchronous transmission means (19) in order to verify which one of the serial computer peripheral equipments wishes to transmit data to the computer system (2).
After verification, the CPU (11) stores data from the asynchronous transmission means (19) in an internal data register thereof. The CPU (11) then transfers the data in said internal data register to a selected region in the RAM unit (13).
After data has been stored in the RAM unit (13), the
CPU (11) provides an address output which is decoded and which is used to activate the interface circuit (15). Data in the RAM unit (13) is then sent to the interface circuit (15). During the read/write cycle of the computer system (2), the CPU (21) detects the presence of a data status signal from the interface circuit (15) via the expansion slot (23). Data from the interface circuit (15) is read by the computer system (2) and is stored in the memory of the latter. This illustrates how data transfer from the computer peripheral equipment to the computer system is accomplished with the use of the present invention.
If the computer system (2) wishes to send data to one of the computer peripheral equipments, the computer system (2) initially provides an address signal at the address bus thereof. The address signal is provided to the interface circuit (15) via the expansion slot (23).
The address signal is decoded and is used to activate the interface circuit (15). The interface circuit (15) responds by sending an interrupt signal to the CPU (11). After verifying that there is valid data at the data bus, the CPU (11) stores the data in the internal data register thereof. The CPU (11) then transfers the data in the internal data register to a selected region in the RAM unit (13).
In accordance with the operating software of the CPU (11), the CPU (11) determines which one of the computer peripheral equipments is to be accessed by the computer system (2). The CPU (11) then generates an address signal which is used to select the asynchronous transmission means (19) of the computer peripheral equipment which is to be accessed. The CPU (11) checks the status of an internal data register of the asynchronous transmission means (19). If the internal data register is empty, the data in the RAM unit (13) is provided to the selected computer peripheral equipment via the asynchronous transmission means (19).
This illustrates how data transfer from the computer system to the computer peripheral equipment is accomplished with the use of the present invention.
Because of the relatively large circuitry involved, the schematic electrical circuit of the interface apparatus of the present invention is shown in three parts. Figure 2 illustrates the CPU (11), the RAM unit (13), the interface circuit (15) and the switch panel (17). Figure 3 illustrates a portion of the asynchronous transmission means (19). Figure 4 illustrates the interrupt circuit of the asynchronous transmission means (19) and how the asynchronous transmission means (19) is connected to the computer peripheral equipments. The operation of the preferred embodiment is described in greater detail in the succeeding paragraphs.
Referring to Figure 2, the interface apparatus of the present invention further comprises an expansion connector (18) which is connected to the CPU (11) and which can be used when expanding the capabilities of the interface apparatus. The interface circuit (15) includes an address latch (151), a first address decoder (152), a second address decoder (153), a first data latch (154), a second data latch (155), a first data latch control circuit (156) and a second data latch control circuit (157). The first data latch control circuit (156) includes a flip-flop (158) and a control switch (159). The second data latch control circuit (157) includes a flip-flop (160) and a control switch (161).
When the computer system (2) wishes to send data to one of the computer peripheral equipments, the computer system (2) initially sends an address signal to the second address decoder (153) via the expansion slot (23). After decoding the received address signal, the second address decoder (153) generates a pulse at pin 18 of the same. Pin 18 of the second address decoder (153) is connected to the CLK pin of the second data latch (155) and to the PR pin of the flip-flop (160) of the second data latch control circuit (157). Upon reception of the pulse at the CLK pin thereof, the second data latch (155) stores the data from the expansion slot (23) of the computer system (2) therein.
After receiving the pulse at the PR pin thereof, the
SINT1 signal, which is present at the /Q output of the flip-flop (160), is set to 0. The SINT1 signal is sent to pin 13 of the CPU (11). Pin 13 of the CPU (11) is an interrupt pin (INT1). Once interrupted, the CPU (11) sends the address of the second data latch (155) to the first address decoder (152). Pin 17 of the first address decoder (152) provides a pulse to pin 1 (OC) of the second data latch (155). Pin 1 (OC) is an output enable pin, thereby enabling the data stored in the second data latch (155) to be loaded into the internal data register of the CPU (11). The CPU (11) then generates an address signal and a write enable (WE) signal to the RAM unit (13), thereby permitting the transfer of data from the internal data register of the
CPU (11) to a selected region in the RAM unit (13).
The pulse which was received at pin 1 (doc) of the second data latch (155) is simultaneously received by the CL pin of the flip-flop (160) of the second data latch control circuit (157). The pulse at the CL pin serves as a clear signal pulse and is used to reset the /Q output of the flip-flop (160) to 1, thereby informing the CPU (11) that the interrupt has ended so that the CPU (11) can revert to the normal operating cycle. During the period of the above operation, when an address signal is present at the expansion slot (23), the control switch (161) of the second data latch control circuit (157) is selected. The output at pin 12 of the second address decoder (153) is maintained at an enable state. Whether the enable state is at a high logic state or at a low logic state depends on whether the circuit is designed as a positive or negative logic circuit.The output at pin 12 of the address decoder (153) is used to turn on the control switch (161), thereby enabling the /Q output of the flip-flop (160) to be sent to the expansion slot (23) for reception by the computer system (2). Therefore, when the pin 1 (OC) of the second data latch (155) receives a pulse to enable the output of the latter, the /Q output of the flip-flop (160) simultaneously changes from a low logic state to a high logic state. The control switch (161) is turned on in order to inform the computer system (2) that data in the second data latch (155) has been read by the CPU (11) and that the next batch of data can be stored in the second data latch (155).
Referring to Figures 2 and 3, when the CPU (11) wishes to send data to a computer peripheral equipment, the CPU (11) generates an address signal to the first address decoder (152). The address signal corresponds to the asynchronous transmission means (19) which, in turn, corresponds to the computer peripheral equipment that is to be accessed. Pins 12, 13, 14 and 15 of the first address decoder (152) are used as select control pins (SO, S1, S2, S3). In the preferred embodiment, the asynchronous transmission means (19) includes four asynchronous transmission units (191, 192, 193, 194), each of which is connected to a respective computer peripheral equipment, such as a touch-operated monitor, a magnetic card reading device, a bar code reading device or a coin receiving unit.The select control pins (S0-S3) of the first address decoder (152) are connected to a respective one of the asynchronous transmission units (191-194). Assuming that the CPU (11) wishes to send data to the asynchronous transmission unit (192), the address signal which is provided by the CPU (11) to the first address decoder (152) is decoded, and the latter responds by generating an enable signal at the S2 select control pin so as to activate the asynchronous transmission unit (192). The
CPU (11) then sends a read enable (RE) signal to pin 21 of the asynchronous transmission unit (192) and an address signal at pins 26 to 28 of the latter, thereby enabling the CPU (11) to check the status of data in the internal data register of the asynchronous transmission unit (192) via the data bus D0-D7 of the latter. After verifying that the internal data register has no data stored therein, the CPU (11) sends a write enable (WE) signal to pin 18 of the asynchronous transmission unit (192) and an address signal at pins 26 to 28 of the latter. Data from the computer system (2), which was stored temporarily in the RAM unit (13), is then provided to the asynchronous transmission (192) via the data bus D0-D7 for storage in the internal data register of the latter.
Referring to Figure 4, the asynchronous transmission unit (192) provides STN1, CTS1, SOU1 and RTS1 transmission signals to a plug (32), which is a 20-pin electrical connector that is adapted for use with standard magnetic card and bar code reading devices.
The asynchronous transmission unit (191) is connected to a 9-pin plug (31) that is adapted for use with a monitor. The asynchronous transmission unit (193) is connected to a 20-pin plug (33) which is similar to the plug (32). The asynchronous transmission unit (194) is connected to a plug (34) that is adapted for use with a coin receiving unit.
The preceding paragraphs illustrate in great detail how data transfer from the computer system to the computer peripheral equipment is accomplished with the use of the present invention. When it is desired to send data from one of the computer peripheral equipments to the computer system, an interrupt signal,
INTO, INT1, INT2 or INT3, is sent by the corresponding asynchronous transmission unit (191-194) to an interrupt processing circuit (35), as shown in Figure 4. The interrupt processing circuit (35) generates an interrupt signal (SINTO) which is received by the CPU (11) at pin 12 of the latter. At this stage, the CPU (11) does not know which one of the asynchronous transmission units (191-194) has generated the interrupt signal.The CPU (11) thus executes an inquiry routine, wherein the CPU (11) first sends a read enable (RE) signal to pin 21 of one of the asynchronous transmission units (191-194) and an address signal at pins 26 to 28 of the latter. The CPU (11) then reads the contents of the internal data register of said one of the asynchronous transmission units (191-194) via the data bus D0-D7. If it has been detected that the internal data register of said one of the asynchronous transmission units (191-194) has no data therein, the
CPU (11) then executes the inquiry routine for another asynchronous transmission unit (191-194).
If it has been detected that the internal data register of one of the asynchronous transmission units (191-194) has data therein, the CPU (11) again sends a read enable (RE) signal to pin 21 of said one of the asynchronous transmission units (191-194) and an address signal to pins 26 to 28 of the latter, thereby enabling the CPU (11) to read the contents of the internal data register of said one of the asynchronous transmission units (191-194) and store the data in the internal data register thereof. The CPU (11) then sends an address signal to the first address decoder (152) and to the RAM unit (13). The first address decoder (152) responds by sending a write enable (WE) signal to the RAM unit (13) via pin 19 of the former, thereby activating the RAM unit (13) to permit the transfer of data from the internal data register of the CPU (11) to a selected region in the RAM unit (13).The succeeding steps are similar to those executed when data is sent by the computer system (2) to the computer peripheral equipment.
After data has been stored in the RAM unit (13), the
CPU (11) sends an address signal to the first address decoder (152), which address signal corresponds to the first data latch (154). After decoding the received address signal, the first address decoder (152) generates a pulse at pin 18 of the same. Pin 18 of the first address decoder (152) is connected to the CLK pin of the first data latch (154) and to the PR pin of the flip-flop (158) of the first data latch control circuit (156). Note that the data stored in the RAM unit (13) is retrieved by the CPU (11) and is stored in the internal data register of the same before sending the same to the first data latch (154). Upon reception of the pulse at the CLK pin thereof, the first data latch (154) retrieves the data from the CPU (11) and stores the same therein.After receiving the pulse at the PR pin thereof, the Q output of the flip-flop (158) is set to 1 and is sent to the control switch (159) of the first data latch control circuit (156).
During the read cycle of the computer system (2), the computer CPU (21) sends the address of the control switch (159) via the expansion slot (23). The address signal is decoded by the second address decoder (153), and pin 12 of the second address decoder (153) generates an enable signal which is used to turn on the control switch (159). The output signal from the control switch (159) is used to confirm whether or not there is valid data present at the first data latch (154). If valid data is present at the first data latch (154), the computer CPU (21) sends another address signal to the second address decoder (153).The second address decoder (153) responds by sending a pulse to pin 1 (OC) of the first data latch (154) via pin 17 of the former, thereby enabling the first data latch (154) to send data to the computer CPU (21) so as to be stored in the internal data register of the latter. At the same time, the pulse at pin 17 of the second address decoder (153) is simultaneously received by the
CL pin of the flip-flop (158) of the first data latch control circuit (156). The /Q output of the flip-flop (158) changes to a logic 1 and is received by pin 15 of the CPU (11), thereby informing the CPU (11) that the last byte of data has been received and that the first data latch (154) is ready to accept the next byte of data.
The above paragraphs illustrate in great detail how data transfer from the computer peripheral equipment to the computer system is accomplished with the use of the present invention.
The function of the address latch (151) is to store temporarily the address signal which is generated by the CPU (11). This is necessary since the CPU (11) uses time division multiplexing to transmit data and address signals. Therefore, the address signal is latched at the appropriate time and is not lost when the CPU (11) transmits data signals.
The advantages and characterizing features of the interface apparatus of the present invention are as follows:
1. At least two serial computer peripheral equipments may be connected simultaneously to one computer system with the use of the present invention.
The present invention is therefore ideal for use in a fully automatic system.
2. The present invention is primarily hardware-based and is fast and efficient. The control software involved is relatively simple.
Claims (8)
1. An apparatus for interfacing a plurality of serial computer peripheral equipments and a computer system, comprising:
an asynchronous transmission unit connected to each of said computer peripheral equipments, said asynchronous transmission unit generating a first interrupt signal and storing a first data set from the corresponding computer peripheral equipment in an internal data register thereof when the corresponding computer peripheral equipment wishes to send said first data set to said computer system;
a central processing means receiving said first interrupt signal, said central processing means determining which one of said asynchronous transmission units has generated said first interrupt signal and reading said internal data register of said asynchronous transmission unit which generated said first interrupt signal;;
an interface circuit provided on an expansion slot of said computer system and connecting electrically said central processing means and said computer system, said interface circuit being controlled by said central processing means to provide said first data set to said computer system; and
said interface circuit generating a second interrupt signal and receiving a second data set from said computer system when said computer system wishes to send said second data set to one of said computer peripheral equipments, said second interrupt signal being received by said central processing means so as to enable said central processing means to receive said second data set, said central processing means activating said asynchronous transmission unit which corresponds to said one of said computer peripheral equipments and providing said second data set to said one of said computer peripheral equipments via said corresponding asynchronous transmission unit.
2. The apparatus as claimed in claim 1, wherein said central processing means comprises a random access memory unit to store temporarily said first and second data sets received thereby.
3. The apparatus as claimed in claim 1, wherein said central processing means executes an inquiry routine in which said central processing means reads said internal data register of said asynchronous transmission units in order to determine which one of said asynchronous transmission units has generated said interrupt signal.
4. The apparatus as claimed in claim 2, wherein said interface circuit comprises:
a first data latch receiving said first data set from said central processing means;
a second data latch receiving said second data set from said computer system;
a first address decoder receiving a first address signal from said central processing means and enabling said first data latch to latch said first data set thereat;
a first data latch control circuit controlled by said first address decoder to provide a first status signal to said computer system so as to indicate to said computer system that said first data set has been latched at said first data latch;;
a second address decoder which is controlled by said computer system upon detection of said first status signal so as to enable said first data latch to provide said first data set to said computer system and so as to instruct said central processing means to send the next said first data set to said first data latch;
said second address decoder receiving a second address signal from said computer system and enabling said second data latch to latch said second data set thereat;
a second data latch control circuit controlled by said second address decoder so as to generate said second interrupt signal in order to indicate to said central processing means that said second data set has been latched at said second data latch;;
said second address decoder being controlled by said central processing means upon reception of said second interrupt signal so as to enable said second data latch to provide said second data set to said central processing means; and
said second address decoder further controlling said second data latch control circuit to generate a second status signal to said computer system so as to instruct said computer system to send the next said second data set to said second data latch.
5. The apparatus as claimed in claim 4, wherein said interface circuit further comprises an address latch to latch an address signal from said central processing means thereat.
6. The apparatus as claimed in claim 1, further comprising a switch panel which is operable so as to select which ones of said computer peripheral equipments are to be used.
7. The apparatus as claimed in claim 1, further comprising an expansion connector connected to said central processing means.
8. The apparatus for interfacing a plurality of serial computer peripheral equipments and a computer system as substantially described hereinbefore with reference to the accompanying drawings.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB9222583A GB2272083A (en) | 1992-10-27 | 1992-10-27 | Serial interface expansion/multiplexing. |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB9222583A GB2272083A (en) | 1992-10-27 | 1992-10-27 | Serial interface expansion/multiplexing. |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB9222583D0 GB9222583D0 (en) | 1992-12-09 |
| GB2272083A true GB2272083A (en) | 1994-05-04 |
Family
ID=10724149
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB9222583A Withdrawn GB2272083A (en) | 1992-10-27 | 1992-10-27 | Serial interface expansion/multiplexing. |
Country Status (1)
| Country | Link |
|---|---|
| GB (1) | GB2272083A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2302967A (en) * | 1995-07-03 | 1997-02-05 | Behavior Tech Computer Corp | Switch for computer peripheral device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1234698A (en) * | 1968-07-03 | 1971-06-09 | Ncr Co | A communication system for transgerrin data between a computer and a plurality of remote data terminals |
| US4124888A (en) * | 1975-12-24 | 1978-11-07 | Computer Automation, Inc. | Peripheral-unit controller apparatus |
| WO1982000374A1 (en) * | 1980-07-11 | 1982-02-04 | Ncr Co | Input/output processor and method of communication for data processing system |
| GB2094522A (en) * | 1981-02-17 | 1982-09-15 | Pitney Bowes Inc | Mailing system |
-
1992
- 1992-10-27 GB GB9222583A patent/GB2272083A/en not_active Withdrawn
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1234698A (en) * | 1968-07-03 | 1971-06-09 | Ncr Co | A communication system for transgerrin data between a computer and a plurality of remote data terminals |
| US4124888A (en) * | 1975-12-24 | 1978-11-07 | Computer Automation, Inc. | Peripheral-unit controller apparatus |
| WO1982000374A1 (en) * | 1980-07-11 | 1982-02-04 | Ncr Co | Input/output processor and method of communication for data processing system |
| GB2094522A (en) * | 1981-02-17 | 1982-09-15 | Pitney Bowes Inc | Mailing system |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2302967A (en) * | 1995-07-03 | 1997-02-05 | Behavior Tech Computer Corp | Switch for computer peripheral device |
| GB2302967B (en) * | 1995-07-03 | 1998-11-11 | Behavior Tech Computer Corp | Switch for computer peripheral device |
Also Published As
| Publication number | Publication date |
|---|---|
| GB9222583D0 (en) | 1992-12-09 |
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| WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |