GB2208321A - Logic probe - Google Patents

Abstract

In a logic probe having the facility to detect logic pulses of shorter pulse width than a selected duration, a detected input pulse is delayed by the selected duration in a delay network (18) and fed to the D input of a D-type flip-flop (12). The undelayed logic pulse is fed to the CLK input. If the input pulse is a negative pulse and is longer than the delay time, the D input will be at logic zeero when the trailing edge of the undelayed pulse arrives at CLK and the flip-flop remains reset. If the delay is longer than the detected pulse the flip-flop will set and then be immediately reset by way of an inverter (20), producing a short pulse on its Q-BAR output, which is latched in a latch flip-flop (22). Positive pulses are similarly detected by flip-flops (24, 26). A microprocessor (30) polls the latch flip-flops, signals whenever a short pulse is detected, and its polarity, and then clears the latch.

Description

LOGIC PROBE This invention relates to a logic probe for detecting pulses in digital systems.

A logic probe is a compact, inexpensive, hand held instrument which may easily be moved around a circuit to investigate levels at any point. There are many such probes available that are of varying degrees of sophistication. Most are able to detect not only the static level at a circuit point (logic level 0 or 1) but can also detect pulses and the polarity of pulses, that is whether they are positive going (from logic 0 to logic 1 and back to logic 0) or negative going (1 to O to 1). Many can also indicate the existence of indeterminate logic levels.

A major problem in circuit design is to eliminate spurious effects caused by 'glitches' in the circuit. A glitch is an unwanted, rogue pulse or series of pulses of very short duration, typically a few nanonseconds. Glitches may also often occur in a stream of longer pulses which makes them all the more difficult to detect. Such pulses are undesirable and can have a significant detrimental effect on the operation of the logic and the microprocessor in a system, and so it is essential that their existence is identified so that they can be eliminated.

Previously, it has been necessary to use expensive and complex test equipment such as an oscilloscope or a logic analyser to detect glitches, and even these pieces of apparatus cannot always detect random short pulses in the nanosecond range.

The present invention aims to overcome the above mentioned problems and accordingly provides a logic probe as defined in the claims.

In a preferred embodiment of the invention the logic probe can be preset to one of a plurality of pulse width values and the probe can detect the presence of any pulses of shorter width or duration than the selected value.

The invention has the advantage that it enhances the value of the logic probe to designers and engineers and replaces the need for logic analysers and other expensive equipment with a relatively cheap and convenient device. Furthermore it can detect rogue pulses that even more complex equipment might not detect.

A better understanding of the invention may be gained from the following description of preferred embodiments thereof, given by way of example with reference to the accompanying drawings, wherein: Figure 1 is a schematic diagram of an embodiment of the invention; and Figure 2 shows explanatory waveforms (A) to (I) occurring at the points thus labelled in Figure 1.

Referring to Figure 1, the logic probe tip is connected via appropriate buffering stages to an input terminal 10 which is connected directly to the clock (CLK) input of a D-type bistable 12 of the type which is triggered by a positive-going transition on its CU input and thereupon copies the logic level on its D input to its Q output. The input terminal 10 is also connected via an inverter 14 to the CL input of another D-type bistable 16 of the type triggered by a positive going transition. The input terminal 10 is moreover connected via a variable delay network 18 to the D inputs of both bistables 12 and 16.

The Q output of the bistable 12 is connected back to the over-riding, active low reset terminal R thereof via an inverter 20, so that, whenever this bistable is set it immediately resets itself, producing a short positive pulse at its Q output, the pulse-width being determined by the propagation delays of the bistable 12 and inverter 20. The short positive pulse is latched in a further D-type bistable 22 which, when set, signals that a negative-going pulse has occurred with a width less than the delay time of the variable delay network 18, as will appear more fully below.

Similarly the Q-BAR output of the bistable 16 is connected back to its set input S via an inverter 24 so that this bistable normally remains set and, if reset, immediately sets itself and produces a short positive pulse on its Q-BAR output. This pulse is latched in another D-type bistable 26 to signal that a positive-going pulse has occurred with a width less than the delay time of the network 18.

The circuit thus far described is interfaced with the remainder of the logic probe circuit which is based, in a manner known in itself, on a microprocessor 30. The microprocessor is connected to an input multiplexer 32 which serves both input keys 34 on the probe and the outputs of the latch bistables 22 and 26. This microprocessor can thus poll the state of these bistables, as well as of the keys which are used, in a well known manner, to select probe functions and also to adjust the delay time of the network 18 up and down. This network is not shown in detail since it utilizes conventional technology. A tapped delay line, preferably cascaded decode delay lines, and multiplexers driven off an address bus 36 allow the desired delay time to be selected.The microprocessor is also interfaced to a display device 38, drives conventional LED's and receives conventional logic probe inputs such as "positive edge" and "negative edge". It also provides reset signals via an output multiplexer 40, in particular signals to reset the latch bistables 22 and 26 after these have been polled.

Consider now the operation when a positive pulse that makes a low to high and back to low transition (010) over a time T is applied to the terminal 10 in Figure 1. A corresponding waveform timing diagram is shown in Figure 2, waveform (A).

On applying power to the circuit the Q-BAR output of the bistable 16 will go to a logic high state (1) and the Q output to a logic low state (0). Since Q-BAR is high, the output of the inverter 24 will be logic low (O). The output of this inverter is connected to the SET (S) input of the bistable 16. As a result the Q-BAR output will be forced to a logic low statue (0). This action then causes the SET input to go high, the bistable (3) is then stable with the Q-BAR output low.

The positive pulse (A) is applied to the circuit. The output (B) of the inverter 14 is connected to the CLK input of the bistable 16. The output of the variable delay network 18 is applied to the D input of the bistable 16. By selecting a delay value, the output of the variable delay line 18 is set to produce a delayed pulse of the input pulse, waveform (C), of delay tl.

The case initially considered is when t1 is less than T.

The output of the inverter 14 makes a low to high transition on the trailing edge of the inverted input pulse, waveform (B). At this time the D input of the bistable 16, namely the output of the variable delay network 18, will be logic high (1). The positive CLK transition therefore causes the Q output to remain at a logic high state (1), the stable state. No short pulse is signalled.

Consider now selecting a different delay value that causes the output of the variable delay network 18 to produce the waveform (D) of delayed time t2, which is greater than T. On the trailing edge of the input pulse, the low to high transition of the inverter 14 output, the D input of the bistable 18 will be logic low (O). The Q-BAR output of the bistable 16 will then go to a logic high (1) state. This, in turn, causes the output of the inverter 24 to go to logic low state (0). This action directly sets the bistable, over riding the CLK and D inputs, causing the Q output to return to a logic low state (0). The result is a fast pulse, waveform ) on the Q-BAR output.

It can be seen that the circuit comprising the variable delay network 18, the inverter 14, the bistable 16 and the inverter 24 will generate fast positive pulses on the Q-BAR output of the bistable 16 whenever a positive going pulse is applied to the circuit that has a width of less than the selected delay value of the delay network 18. No fast pulses are produced when input pulses are of greater width than the selected delay value.

Detection of negative going pulses, logic high to low back to high ( 1 0 1 ) are similarly detected using the delay network 18, the bistable 12 and the inverter 20.

The input pulse (F) of duration T is shown delayed by the delay t1 less than T to produce pulse (G). At the time of the positive going edge of (F), (G) is low and the bistable 12 accordingly remains in its stable, reset state. If however, the delay exceeds T, i.e. the delayed pulse is pulse (H) delayed by t2, the positive going edge of (F) occurs while (H) is still high and the bistable 12 is accordingly set to produce a fast pulse (I).

Various modifications in detail to the logic may obviously be made. It would also in principle be possible to clock the bistables 12 and 16 off the leading edges of the delayed pulses provided by the delay network 18, the input pulse and inverted input pulse being connected to the appropriate D inputs. However, the clocking of the bistables is dependent upon the delay network always providing an adequate pulse at its output. Having regard to the drive capability and impedance of this network, clocking cannot always be guaranteed if the input pulse is very fast. The configuration of Figure 1 is therefore much preferred since the failure of an adequate pulse to emerge from the delay network will lead to detection by default.

The microprocessor can signal detected short pulses in various ways, preferably distinguishing the polarity thereof. For example the microprocessor 30 can sound a buzzer whenever a short pulse occurs and indicate on its display device 38 the set delay time (i.e. the width threshold below which a pulse has fallen) and the polarity of the offending pulse.

Claims (9)

CLAIMS:

1. A logic probe for detecting logic levels and pulses in an electronic circuit, comprising detecting means for detecting a pulse at a selected point in the circuit, means for determining whether the width of a detected pulse is shorter than a predetermined pulse width.and means for signalling that such a short pulse has been detected to the user.

2. A logic probe according to claim 1, wherein the detecting and determining means distinguish the polarity of the short pulse and the signalling means -indicate the polarity of the short pulse.

3. A logic probe according to claim 1 wherein the determining means comprises delay means arranged to delay the detected pulse by the predetermined pulse width, and a two-state logic device having the delayed pulse as a first input and the undelayed pulse as a second input, the logic device having an output arranged to change logic state when a transition in a particular direction occurs on one of the inputs at a time when the other input is at a particular level.

4. A logic probe according to claim 3, wherein the said one of the inputs is the second input, the said other input is the first input and the said transition is the trailing edge of the undelayed pulse.

5. A logic probe according to claim 3 or 4, wherein the logic device is arranged to revert to a datum logic state after changing state in response to the said transition and is connected to a second logic device serving to latch the change of state of the first said logic device.

6. A logic probe according to claim 5, comprising a microprocessor arranged to poll the state of the second logic device and then to reset the second logic device.

7. A logic probe according to claims 3 to 6, wherein there are two first logic devices responsive to detected pulses of opposite polarities respectively.

8. A logic probe according to any preceding claim, comprising means for adjusting the predetermined pulse width to a desired value.

9. A logic probe substantially as herein described with reference to the accompanying drawings.