GB2207316A - Integrated circuit - Google Patents

Abstract

A very low frequency pulse generator suitable for use in an integrated circuit consists of several pulse generators of different p.r.f's connected through a logical OR circuit to the input of a monostable trigger to set it when a predetermined transition occurs in the output of the OR circuit, and an AND-gate connected to receive the pulses from the generators and the output pulse of the monostable trigger. The duration of the pulse from the monostable trigger is shorter than those of the pulses from the generators. The output pulse from the AND-gate may be fed back to reset the pulse generators to a particular combination of states. <IMAGE>

Description

Integrated Circuit This invention relates to integrated circuits, and in particular to a low frequency pulse generator suitable for integration on a semiconductor chip.

There are many applications of electronics circuitry which require the generation of pulses at a low frequency. For example, the operation of flashing direction indicators of motor vehicles requires the generation of pulses at 1 - 2 Hz, and the production of certain displays from the output of a computer. It would be desirable to include a suitable low frequency pulse generator in an integrated circuit also providing other functions but the circuits used hitherto for producing pulses at low frequency require the use of an uneconomic area of the semiconductor chip. The direct generation of pulses at low frequency requires the use of a circuit having a long time constant, which necessitates the use of a high value capacitor occupying a large area of the chip.An alternative way is to use a high frequency pulse generator and apply the pulses to a frequency divider; in this case the many dividing stages required occupy an unacceptably large area of the semiconductor chip.

It is an object of the present invention to provide a circuit for producing pulses at a low frequency which can be constructed on a relatively small area of a semiconductor chip.

According to the present invention there is provided a circuit arrangement for producing pulses at a low frequency including two or more rectangular wave generators producing pulses at different frequencies, and logic means responsive to the pulses from all of the generators to produce an output pulse when the pulses from all of the generators execute predetermined transitions within a predetermined duration.

The predetermined duration may be provided by the set period of a monostable trigger controlling an AND gate or similar logical element. The monostable trigger may be set in response to a logical OR combination of the pulses from the generator} so that, for example, the trigger is set by a transition from low to high of one generator,while the or each other generator is low.

The AND gate or similar logical element may also receive the pulses from all of the generators so that it produces an output only if the monostable trigger is set and all of the generators, other than the one which caused the trigger to be set, execute a transition from low to high whilst it is set. The duration of the set state of the monostable trigger should be less than the duration of a pulse from any of the generators.

It is not necessary for the predetermined transitions of the pulses from the generators all to be the same, that is all low to high or all high to low.

In order that the invention may be fully understood and readily carried into effect, an example of it will now be described with reference to the accompanying drawings, of which: Figure 1 is a diagram of a circuit according to the invention; Figure 2 shows the relative timing of pulses in the circuit of Figure 1 under certain circumstances; and Figure 3 shows the relative timing of pulses in the circuit of Figure 1 under other circumstances, In the example of the invention shown in Figure 1 there are three rectangular wave generators 1; 2 and 3 having different pulse repetition frequencies. The output pulses of the generators 1, 2 and 3 are applied to the inputs of an OR gate 4 and to the inputs of an AND gate 5.A monostable trigger 6 is connected to be set by a low to high transition at the output of the OR gate 4 and to apply its output pulse to a forth input of the AND gate 5. The output 7 of the AND gate 5 provides the output of the circuit.

The generators 1, 2 and 3 may be square wave generators. The monostable trigger 6 produces an output pulse of fixed duration which is shorter than the duration of the pulses produced by any of the generators 1, 2 and 3.

In the operation of the circuit output pulses are produced from the AND gate 5 whenever the pulses from all of the generators 1, 2 and 3 have rising edges within the duration of a pulse from the monostable trigger 6.

If the pulse duration of the trigger 6 is lengthened the frequency of output pulses from the AND gate 5 increases and may become irregular. On the other hand, provided that the pulse duration of the trigger 6 is sufficiently short it can be shown that the mean time between the output pulses from the AND gate 5 is B.C.D./3AZ for a 3 generator circuit, where B, C and D are the periods of the waves from the generators 1, 2 and 3 and A is the duration of the pulse from the trigger 6, it being assumed that no two of B, C and D are related by a whole number.

Figure 2 shows square waves 10, 11 and 12 output from the generators 1, 2 and 3 respectively. The broken line 13 indicates the simultaneous rising flanks in the waves 10, 11 and 12 which together set the monostable trigger 5 which produces at its output the pulse 14.

Since all three of the waves 10, 11 and 12 are high following the simultaneous rising flanks the output from the AND gate 5 is a pulse 15 similar to the pulse 14.

In the example shown in Figure 2, the period of the square wave 10 is 3ps that of wave 11 4ps and that of wave 12 5ps and the pulse from the monostable trigger 6 has a duration of 0.25ps. This means that as well as being set at the time represented by the lines 13, the monostable trigger 6 is also set 3ps later in response to a rising flank of the wave 10, and 8ps later in response to a rising flank of the wave 11, giving rise to output pulses 16 and 17 from the trigger 6. Neither of these pulses pass through the AND gate 5 because for the duration of the pulse 16 both waves 11 and 12 are low and for the duration of the pulse 17 both waves 10 and 12 are low.It can be shown that the next time a pulse output appears from the AND gate 5 is the next time the rising flanks of the waves 10, 11 and 12 occur at the same time, that is to say 60s later.

Figure 3 shows the case where the rising flanks are not quite synchronised. A pulse 20 from the trigger 6 is produced in response to the rising flank of a pulse 21, but it is not until both pulses 22 and 23 have risen that an output pulse 24 appears from the AND gate 5. This means that the pulse 24 is of shorter duration than the pulse 20.

If desired the output pulse from the AND gate 5 can be lengthened by applying it to a second monostable trigger, not shown in the drawings.

The output pulses are not necessarily evenly spaced in time but over an extended time period will tend to have a constant average interval between them.

In order to ensure a regular succession of output pulses from the AND gate 5 it may be desirable to trim one or more of the generators 1, 2 and 3 so that they produce pulses of the required duration at the required repetition rate, This trimming could for example, be achieved by selectively switching into the circuit additional resistive or capacitive element by the overdriving of zener diodes which converts them to short circuits.

More stable periodicity of the output pulses would be obtained if the output pulse from the AND gate 5 were to be connected back to reset the generators 1, 2 and 3 to a predetermined position in the cycle so that errors in the frequencies of the generators are corrected each time an output pulse is produced.

This could be used in conjunction with the trimming of the generators described above.

The invention is particularly advantageous when used in an integrated circuit because no long time constants are required necessitating the use of high value capacitors or resistors, and moreover no long divider chain is needed. The generators 1, 2 and 3 may, for example, be astable schmitt trigger circuits, and the other components may be of conventional construction.

Although the invention has been described with reference to a specific example using positive logic, it could equally well be made using negative logic, or even some positive and some negative logic. Of course, the invention may use only 2 generators or 4 or more if desired.

Claims (14)

CLAIMS:

1. A circuit arrangement for producing pulses at a low frequency including two or more rectangular wave generators producing pulses at different frequencies, and logic means responsive to the pulses from all of the generators to produce an output pulse when the pulses from all of the generators execute predetermined transitions within a predetermined duration.

2. An arrangement according to claim 1 wherein the predetermined duration is determined by the set period of a monostable trigger, the set period having a duration less than the duration of a pulse from any of the rectangular wave generators.

3. An arrangement according to claim 2 wherein the logic means includes a logical element responsive to an output from the monostable trigger.

4. An arrangement according to claim 3 wherein the logical element is also connected to receive pulses from all of the rectangular wave generators.

5. An arrangement according to claim 3 or 4 wherein the logical element is an AND-gate.

6. An arrangement according to any one of claims 2 to 5 wherein the logic means includes a logic circuit connected to set the monostable trigger in response to a transition occurring in a logical OR combination of the pulses from the rectangular wave generators.

7. An arrangement according to any one of the preceding claims in which the predetermined transitions in the pulses from the rectangular wave generators are all of the same sense.

8. An arrangement according to any one of claims 1 to 6 in which at least one of the predetermined transitions in the pulses from the rectangular wave generators is of the opposite sense to the other such predetermined transition or transitions.

9. An arrangement according to any one of the preceding claims wherein at least one of the rectangular wave generators includes means for trimming the duration of the pulses which it produces.

10. An arrangement according to claim 9 wherein the trimming means includes additional resistive or capacitive elements which are selectively connected to the particular rectangular wave generator by short-circuits produced by over-driving zener diodes.

11. An arrangement according to any one of the preceding claims wherein the output pulses of the arrangement are applied to reset the rectangular wave generators to a predetermined position in the cycle, so that the output pulses of the arrangement have a more stable periodicity.

12. An arrangement according to any one of the preceding claims wherein the rectangular wave generators are astable Schmitt trigger circuits.

13, A circuit arrangement for producing pulses at a low frequency substantially as described herein with reference to and as illustrated by the accompanying drawings.

14. An integrated circuit incorporating a circuit arrangement for producing pulses at a low frequency according to any one of the preceding claims.