GB2200518A

GB2200518A - Data pulse timing

Info

Publication number: GB2200518A
Application number: GB08702046A
Authority: GB
Inventors: Wilkin Reed
Original assignee: Crystalate Electronics Ltd
Current assignee: Crystalate Electronics Ltd
Priority date: 1987-01-30
Filing date: 1987-01-30
Publication date: 1988-08-03
Also published as: GB8702046D0

Abstract

A digital data communication system comprises a first station (1 Fig 1) at which a coded information signal 14 is generated comprising a series of bit-signifying data pulses, 15, 16, 17 each occupying a particular time interval T1, T2, T3, each data pulse incorporating, at the commencement thereof, a marker pulse 18, 19, 20. The marker pulses 18, 19, 20 are formed by maintaining the first level B for a first time interval T4, T6, T8 followed by the second level A for a second time interval T5, T7, T9, the sum of each first and second time interval being substantially less than the corresponding time interval T1, T2, T3 occupied by a data pulse 15, 16, or 17. The coded signal is transmitted to a second station (8). Detection of the marker pulses 18, 19, 20 is used to initiate a time delay of one half the particular time interval and then a short pulse is applied to a clock input terminal of a shift register (9). The coded signal is thereby clocked into the shift register (9) and may be displayed at (21), further processed or used at (13) to provide a functional response. <IMAGE>

Description

TITLE: DATA COMMUNICATION SYSTEM This invention relates to digital data communication systems of the type in which a coded information signal comprising a series of data pulses is generated at and transmitted from a first station and received and processed at a second station.

Such data communication systems are well known in which information in the form of a stream of signal units is transmitted over a transmission path to a receiving station.

The transmitted information signal may contain a succession of data pulses of the same level and it is necessary to be able to discriminate between these pulses at the receiver. This has commonly been achieved by employing a synchronised system in which a clock in the receiver is synchronised with a clock in the transmitter such that the receiver is provided with the correct time relationship for satisfactory reception and interpretation of the information signal. In such an arrangement the receiver is dependant upon the transmitter for its timing.

It is an object of the invention to provide a data communication system which does not require the receiver to be synchronised with the transmitter. Marker pulses are incorporated with data pulses in the information signal being transmitted and the marker pulses are used to generate timing signals in the receiver.

The present invention provides a digital data communication system comprising: means to generate at a first station a coded information signal comprising a series of data pulses each occupying a particular time interval, each data pulse incorporating, at the commencement thereof, a marker pulse, the marker pulses being adapted to be maintained at a first level for a first time interval and at a second level for a second time interval, the first and second time intervals for a marker pulse when summed together being less than the particular tine interval occupied by the data pulse in which it is incorporated: means to transmit the information signal to a second station; means to receive the information signal at the second station, detection of the marker pulses providing timing data for use in processing the received information signal.

The data pulses are bit-signifying pulses, ie pulses which signify binary digits, and assume one of the two levels corresponding with the first and second levels of the marker pulses, such levels suitably denoting '0' or '1' bits respectively, or vice versa.

Each data bit-signifying pulse is identified and characterlsed by a transition in the marker pulse from the first level to the second level between the first and second time intervals such transition being similar to a transition from a bit '0' to a bit '1' or vice-versa. For the remainder of its time interval the data bit-signifying pulse is at the first or second level, equivalent to a bit '0' or a bit '1', according to the information being transmitted.

The transition in each marker pulse when detected at the second station is used to generate timing signals. Such timing signals may, for example, be employed for clocking the information signal into a shift register at the second station. The received information signal at the second station may, if required, be subjected to operations such as further processing or decoding or may be used to initiate a desired response. If, for example, the information signal comprises or embodies an identity code, such code may, after receipt at the second station be displayed or used to provide some functional response, eg in the machine, system, or process control fields.

The rece-ived identity code may, if desired, be compared with a pre-set code provided at the second station by a programmed device and provide a functional response conditional upon correlation, or otherwise, between the received identity code and the pre-set code.

The transmitted information signal may also include at the beginning and/or end thereof protocol-verifying data pulses which may, for example serve as 'start' or 'stop' bits.

The invention is now described, by way of example only, with reference to the accompanying drawings in which; Figure 1 shows a schematic representation of transmitting and receiving stations forming an embodiment of data communication system according to the invention, and Figure 2 represents a coded information signal involved in the data communication system of Figure 1.

At a first station 1, a trigger circuit 2 is initiated from internal or external sources and starts a clock pulse generator 3. The output from the clock pulse generator 3 is connected by way of a multiplexing sequencer 4 to a coding logic circuit 5 in which coded information may be set from a programmed or programmable means (not shown). This means may comprise a known form of programmed memory device such as the programmed matrix described in the specification of published British Patent Application No. GB 2167621A. Alternatively it may comprise a keyboard arrangement or a series of switches.

The output from the coding logic circuit 5 is arranged to control a code transmitter 6 which outputs a coded information signal for transmission to a second station 8 by well-known means such as wire links or by radio, infra-red or ultrasonic techniques. An example of the coded information signal being transmitted is illustrated in Figure 2. The coded information signal 14 comprises a succession of data pulses at first and second levels A and B. These data pulses signify bits (binary digits) and a data pulse at level A denotes a '1' while a pulse at level B denotes a 'O'. In the coded information signal 14 shown in Figure 2, a data pulse 15 maintained at level B (denoting a '0' bit) occupies a time interval T1 while further successive data pulses 16 and 17 maintained at level A, (denoting two '1' bits) occupy time intervals T2 and T3 respectively.With reference to data pulse 15, a marker pulse denoted by hatched region 18, is provided incorporated at the commencement thereof and maintained at level B for a first time interval T4 and at level A for a second time interval T5, the sum of the first and second time intervals T4 and T5 being less than the tlme interval T1 occupied by the data pulse 15. By way of specific example, the marker pulse 18 is suitably maintained at level B for a time interval T4 which is one-eighth of the time interval T1 for the data pulse 15 and then at level A for a further time interval T5 which is one-eighth of the time interval T1. Consequently after one-eighth of the time interval of the data pulse 15 a transition from level B to level A occurs and the detection of such a transition is used to mark the data pulse 15.In like manner, detection of transitions from level B to level A in subsequent marker pulses denoted by hatched regions 19 and 20, is used to mark the data pulses 16 and 17. With reference to data pulse 16, the marker pulse 19 is maintained at level B for a first time interval T6 and at level A for a second time interval T7, the sum of T6 and T7 being less than the time interval T2 occupied by the data 2 pulse 16. For data pulse 17, the marker pulse 20 is maintained at level B for a first time interval T8 and at level A for a second time interval Tg, the sum of T8 and Tg being less than the time interval T3 occupied by the data pulse 17.

The transitions from level B to level A effectively denote a change from a bit '0' to a bit '1'. The coded information signal 14 is transmitted to a second station 8 by well-known means (not shown) such as wire links, or by radio , infra-red or Ultrasonic techniques. The signal 14 is received by a receiver amplifier 7 at the second station 8 and then applied to a data input terminal of a shift register 9 and also to a delay circuit 10. When the transition from level B to level A in a marker pulse (eg 18) is detected at the second station 8, a time delay is initiated by the delay circuit 10 and which is suitably equal to one-half of the time interval (eg T1) for the data pulse (eg 15) in which the marker is incorporated. A short pulse is then produced by the pulse generator 11 and applied to a clock input terminal of the shift register 9. The information signal then appearing at the data input terminal of the shift register 9 is thereby clocked into the shift register 9. Some of the outputs of the shift register may conveniently be used to verify protocols appropriate to the data commmunication system.

These outputs may conveniently be connected to a decoding logic circuit 12 in such a manner as to ascertain when the correct protocol has been received by the shift register. The other outputs of the shift register 9 contain coded data information.

This information nay be displayed, if required, on a display means 21 or fed to other circuits for any other required purposes.

If, for example, the coded data information comprises an identity code, the outputs from the shift register 9 containing it nay also be connected to the decoding logic circuit 12. The decoding logic circuit 12 may be preset to a specific code by suitable means such as, for example, a programmed matrix device as described in the specification of published British Patent Application No. GB 2167621A. Other programmed or programmable memory devices may alternatively be employed for this purpose, or a keyboard arrangement or a series of switches could be used. It can be arranged such that when correlation exists between the received coded information signal and the preset code, an output is obtained from the decoding logic circuit 12 and this may be used to switch a function circuit 13.The function circuit 13 then performs a designed function which may include retransmitting a signal back to the first station 1 to signify that the information signal 14 transmitted by the first station 1 has been received and identified by the second station 8.

Within the scope of the invention is the possibility of providing a plurality of second stations each incorporating a particular identity code. When one of these second stations comes into transmission/reception contact with the first station it may be required to determine, at the first station, the identity of the second station. This can be achieved by transmitting from the first station a sequence of suitably spaced coded information signals covering the range of codes of all of the second stations. When the particular second station receives the coded signal in the sequence which corresponds with its own pre-set code, it responds immediately to the first station and its identity is determined from a knowledge of the coded signal at the first station which gave rise to the response.

Claims

1. A digital data communication system comprising: means to generate at a first station a coded information signal comprising a series of data pulses each occupying a particular time interval, each data pulse incorporating, at the commencement thereof, a marker pulse, the marker pulses being adapted to be maintained at a first level for a first time interval and at a second level for a second time interval, the first and second time intervals for a marker pulse when summed together being less than the particular time interval occupied by the data pulse in which it is incorporated: means to transmit the information signal to a second station; detection of the marker pulses providing timing data for use in processing the received information signal.

2. A digital data communication system according to Claim 1, in which the data pulses are bit-signifying pulses and assume one of the two levels corresponding with the first and second levels of the marker pulses.

3. A digital data communication system according to Claim 2, in which the first and second levels denote '0' or '1' bits respectively or vice-versa.

4. A digital data communication system according to Claim 2 or 3, in which each data bit-signifying pulse is identified and characterised by a transition in the marker pulse from the first level to the second level between the first and second time intervals such transition being similar to a transition from a bit '0' to a bit '1' or vice-versa.

5. A digital data communication system according to Claim 4, in which for the remainder of its time interval, after the first and second time intervals, the data bit-signifying pulse is at the first or second level, equivalent to a bit 'O' or a bit '1', according to the information being transmitted.

6. - A digital data communication system according to any preceding Claim, in which the transition in each marker pulse, when detected at the second station, is used to generate timing signals.

7. A digital data communication system according to Claim 6, in which the timing signals are employed for clocking the information signal into a shift register at the second station.

8. A digital data communication system according to any preceding Claim, in which the received information signal at the second station is subjected to further processing or decoding, or used to initiate a desired response.

9. A digital data communication system according to Claim 8, in which the information signal comprises or embodies an identity code, which code, after receipt at the second station, being displayed or used to provide some functional response.

10. A digital data communication system according to Claim 9, in which the received identity code is compared with a pre-set code provided at the second station by a programmed device, and provides a functional response conditional upon correlation, or otherwise, between the received identity code and the pre-set code.

11. A digital data communication system according to Claim 8, in which a plurality of second stations are provided, each incorporating its own unique pre-set identity code, said first station being adapted and arranged to generate aird transmit a sequence of suitably spaced coded information signals covering the identity codes of all of the second stations, and such that when a particular second station receives the coded signal inthe sequence which corresponds with its own pre-set code, it provides a response to the first station and its identity is determinable at the first station from a knowledge of the coded signal at the first station which gave rise to the response.

12. A digital data communication system according to any preceding Claim in which the information signal transmitted to the second station includes,- at the beginning and/or end thereof, protocol-verifying data pulses.

13. A digital data communication system constructed and arranged substantially as hereinbefore described with reference to the accompanying drawings.