GB2178272A - Clock extraction from coded data streams - Google Patents
Clock extraction from coded data streams Download PDFInfo
- Publication number
- GB2178272A GB2178272A GB08601709A GB8601709A GB2178272A GB 2178272 A GB2178272 A GB 2178272A GB 08601709 A GB08601709 A GB 08601709A GB 8601709 A GB8601709 A GB 8601709A GB 2178272 A GB2178272 A GB 2178272A
- Authority
- GB
- United Kingdom
- Prior art keywords
- data stream
- time interval
- masking
- transition
- longest
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0054—Detection of the synchronisation error by features other than the received signal transition
- H04L7/0066—Detection of the synchronisation error by features other than the received signal transition detection of error based on transmission code rule
Abstract
A method of extracting clock information from a coded data stream. A first pulse train is derived from the data stream, each pulse corresponding to a logic level transition. Some of these pulses will occur at double the clock rate. To remove these spurious pulses, the longest time interval occurring, between transitions is determined and the pulse train is masked for a large fraction of this interval. The pulse train may be produced by means of a differentiate and full-wave rectification circuit.The longest time interval and the masking time may be determined by resistor-capacitor (R-C) charging circuits, the R-C combinations being ratio'd to give the desired fraction. <IMAGE>
Description
SPECIFICATION
Clock extraction from coded data streams
TECHNICAL FIELD
The present invention concerns a method and also apparatus for the extraction of clock signal information from a transmitted coded data stream.
In orderto transmit a digital serial data stream it is usual to code the data so that there is sufficient information within the stream to recover a timing clock which is subsequently used to define the data bit periods.
This invention has application to communications links, especially links that employ Manchestertype coding for data transmission.
BACKGROUND ART
When the bit repetition rate oftransmitted data is invariant and known, clock signal information can be extracted and signal recovered by a combination of frequency synthesis, edge detection and plan-lock tracking. A problem will arise however should the receiver clock frequency drift, and extraction is especially difficult when the bit repetition rate is unknown orvaried.
DISCLOSURE OF THE INVENTION This invention allows the extraction ofclocksignal information without prior knowledge of its frequency provided the code satisfies the following criterion:- i) The longest permissible time interval without a data transition is defined by the code; and, ii) Data transitions occur at regularly spaced intervals.
The biphase codes, for example Manchester type codes, satisfy these conditions.
In accordance with a first aspect of thins invention there is provided a method for extracting the clock period from a coded data stream, this method comprising the steps of:producing a pulse train responsive to the data stream, each pulse corresponding to a data transition; determining from the data stream the longest time interval between transitions; generating a masking time signal, corresponding thus to a masking time that is a fixed fraction of the longest time interval determined; and, using the masking time signal to suppress pulses, in the pulse train, that occur during the masking time aforesaid.
In accordance with a second aspect ofthis invention there is provided apparatus for extracting the clock period from a coded data stream of the type having the longest permissible time interval without a transition defined by the code ofthe data stream and in which a data dependenttransition occurs at regularly spaced time intervals in the data stream,the apparatus comprising pulse series producing meansforproduc- ing a pulse series in dependence upon the transitions in the coded data stream, a masking time interval generatorfor producing a masking time interval signal of masking period tfor masking pulses in the pulse series produced in dependence upon transitions not coinciding with the longest possible time interval in the data stream without a transition, first circuit means for establishing a first electrical condition indicative of the longesttime interval inthedatastreamwithouta transition, further circuit means for establishing a further electrical condition having a predetermined
relationship to the first electrical condition, and a control comparator, responsive to the first and further electrical conditionsforcontrolling the masking time interval generator such that the duration of the masking period t is controlled in dependence upon the longest permissible time interval in the data stream without a transition.
In this invention, the longest time interval between data transitions is represented as an electrical quantity and this is used to define, by simple ratio, a second quantitywhich is representative of a blanking time interval.This blanking interval isjustshorterthanthe time interval between the regularlyspaced transitions. An incoming data transition triggers an output which is prevented from responding to further data transitionsforthe duration ofthe blanking interval. If the raw, uncoded, data is random then eventually the output will be triggered by one ofthe regularly spaced transitions and henceforth, if there are no transmission errors received, the output will be a regular square wave at a frequency in defined ratio to that of the clock.The clock can then be obtained by multiplication techniques.
The concept is illustrated by a circuit design to measure the period of the clock embedded in a biphase encoded data stream and use this information to recreate the clock frequency. A biphase encoded data stream is one which there is a transition in every bit period, to carry the clock content and a data dependenttransition. Figures 1(a) and (b) respectively give Manchester Biphase and Biphase Mark as examples. Fortheformerthere is always a transition in the middle ofthe bit period and a data dependent transition at the end; forthe latterthere is always a transition at the end of a bit period and a data dependent transition in the middle.In orderto extract the clock from biphase codes the input signal figure 2(a) can be differentiated figure 2(b) and full wave rectified figure 2(c) after which the data dependent transitions can be masked out figure 2(d) leaving a series of pulses figure 2(e) at regular intervals. The masking out of date dependent pulses figure 2(c) is straightforward if the clock frequency and hence period is already known; one method of achieving this is by using a masking time delay of signal width t (where ttB, t > B/2; B is the bit period) which is triggered from arriving pulses and masks pulses which arrive during the following timet (figure 2(d)).
The masking ofthe data dependent transitions leaves a stream of regularly spaced pulses figure 2(e) which is the clock recovered from the coded data.
If the clock period is not known then it can be found by measuring the width ofthe incoming pulses. In a
Biphase code, transitions are separated by either B or
B/2 (See figure 1). The width of eitherthe short pulses (B/2) orthe long pulses (B) can be measured by representing the pulse width by the voltage on a capacitor CM which is charged during the period between pulses. The voltage representing the longer pulses (width B) can be stored on a reservoir CR.
If a smallertiming capacitor Ciin the ratiot:B is charged at the same rate as the measuring capacitor
CM and the voltage compared with that on the reservoir capacitor CR then after a time t the voltage on the two capacitors CT, CR Will be equal and the charging time can be used as the masking interval to blank outthe data dependent transitions. In a similar mannerthevoltage representing the width of B/2 pulses could be stored on the reservoir CR and a ratio oft:-52 used forthetiming and measuring capacitors CT, CM.
BRIEF IN TROD UCTION OF THE DRAWINGS
In the drawings accompanying this specification: Figure 1 shows a set of timing diagrams illustrating clock signal, data signal, (a) Manchester II biphase coding, and, (b) Manchester biphase mark coding; Figure2showsafurthersetoftiming diagrams illustrating (a) biphase coded data, (b) differentiated data signal, (c) the latterfollowing full-wave rectification, (d) a masking signal, and, (e) a clock output signal provided by masking the differentiated and rectified signal (c) above;
Figure 3 is a circuit diagram for one implimentation of receiver clock extraction circuit, a circuit for applying the method of this invention; and, Figure 4shows a set oftiming diagrams forsignals exhibited at points A to H of the foregoing circuit.
DESCRIPTION OFA PREFERRED EMBODIMENT
So that this invention may be better understood, an embodimentthereofwilt now be described with reference to the accompanying drawings.
The description thatfollows is given by way of example only.
The circuit shown in figure 3 comprises a differentiate and full-wave rectifying unit 1 to serve as a means for producing a pulse series. This is followed by a R-S latch 3, this serving as a masking time interval generator. The reset function ofthis latch 3 is controlled buy a combination oftiming sub-circuits.
The latter comprise a number oftransistor pairs T1, T2; ...; T9, T10, three pairs of whichrnamely pairs T5, T6; T7, T5; and Tg, To are arranged in long-tail pair configuration and are powered by a respective current source I.
Associated with each long-tail pairT7, Tg; T5, T6; and T,,Tlothere is a resistor RM, RR and RT and a storage capacitor Chrlr CR and CT.
These capacitors CM, CR and CT act as measuring, reservoir and timing capacitors, respectively. Transistors T1 and T2 serve as a current mirror and a reference voltage VAEF2 iS applied to their bases. Transistors T3 and T4 are cascaded to the bases of transistors T5 and
T6 respectively. A further reference voltage VREF1 iS applied to the bases oftransistors T8 and Tg.
The configuration is as shown.
The width of the long pulses, B, is stored on the reservoir capacitorCR asfollows:- i) The input waveform (A) is compared with reference voltage VASFI.
ii) If voltage at (A) < VREF1, point B is held at a voltage of VREFS-VBEI (where VBE is the base-emitter voltage of Tq orT2when an emitter current of I is flowing).
iii) Ifvoltage atA) )VREF1 thenthevoltageofB rises as the measuring capacitor CM is charged through RM.
iv) The reservoircapacitor ischargedsuchthat after many pulses the voltage at C rises to the maximum voltage of (B) -VBE (T3). The voltage rise of C is approximately proportional to the width, B, of the long incoming pulses.
When this has occured the clock is extracted from the incoming data as follows :- v) The incoming pulse goes through a differentiate and full-wave rectify circuit 1 to produce a stream of pulses at (D).
vi) Each pulse sets the output (E) ofthe Rs latch 3 to logic high. If E is at logic low the voltage at (F) is fixed at its base level of VREFP-VBEI (oftransistorT2).
vii) If E is at logic high (at a voltage > VAEFi) the voltage at (F) begins to rise as the timing capacitor CT is charged through RT.
viii) The voltage at (F) is reproduced one VBE lower at(G).
(ix) The voltage at (G) is compared with the static voltages at (C). "t" seconds after the nodes (F) and (G) begin to rise the voltage at (G) exceeds that at (C) and the comparatorT5, T6 output, (H), changes to logic high.
x) When (H) goes high (E) is resetto logic low which causes the voltage at (F) to return quickly to its base level of VAEF2-VBE I.
xi) When (F) returns to its base level, (G) follows to its base level and the comparatorT4, T6 switches again such that its output, (H) falls to logic low.
xii) The R-S latch 3 is now readyto respond to the next pulse produced by a transition in the incoming data stream at (A).
xiii) The clock information is available as a train of equally spaced spikes at (H) or as a train of equally spaced pulses of width tat (E).
A similar circuit can be generated which ratios the charging resistors R ratherthan the measuring capacitor and the timing capacitor.
To allow correction of the clock output signal for data distortion,the raw clock signal is preferably followed by a phase-lock loop sub-circuit.
Claims (6)
1. Apparatus for extracting the clock period from a coded data stream of the type having the longest permissible time interval without a transition defined by the code of the data stream and in which a data dependent transition occurs at regularly spaced time intervals in the data stream, the apparatus comprising pulse series producing means for producing a pulse series in dependence upon the transition in the coded data stream, a masking time interval generatorfor producing a masking time interval signal of masking period t for masking pulses in the pulse series produced in dependence upon transitions not coinciding with the longest possible time interval in the data stream without a transition, first circuit means for establishing a first electrical condition indicative of the longest time interval in the data stream without a transition, further circuit means for establishing a further electrical condition having a predetermined relationship to the first electrical condition, and a control comparator, responsive to the first and further electrical conditions for controlling the masking time interval generator such that the condition ofthe masking period t is controlled in dependence upon the longest permissible time interval in the data stream without a transition.
2. Apparatus, as claimed in claim 1, wherein the first circuit means and the further circuit means each comprise a capacitor, the capacitances ofthese being in at the same ratio as that of the time interval and the masking period
3. Apparatus, as claimed in claim 2, wherein the first circuit means and the further circuit means each comprise a resistor,the resistances of these being in the same ratio as that of the time interval and the masking period.
4. Apparatus, as claimed in anyoneofthe preceding claims, wherein the pulse series producing means serves to provide differentiation and full-wave rectification for the coded data stream.
5. Apparatus for extracting the clock period from a coded data stream, constructed, adapted and arranged to operate, substantially as described hereinbefore with reference to and as shown in the accompanying drawings.
6. A method for extracting the clock period from a coded data stream, this method comprising the steps of:producing a pulse train responsive to the data stream, each pulse corresponding to a data transition; determining from the data stream the longest time interval between transitions; generating a masking time signal, corresponding thus to a masking time that is a fixed fraction of the longest time interval determined; and, using the masking time signal to suppress pulses, in the pulsetrain,that occurduringthe masking time aforesaid.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB858501827A GB8501827D0 (en) | 1985-01-24 | 1985-01-24 | Clock extraction from coded data streams |
Publications (3)
Publication Number | Publication Date |
---|---|
GB8601709D0 GB8601709D0 (en) | 1986-09-17 |
GB2178272A true GB2178272A (en) | 1987-02-04 |
GB2178272B GB2178272B (en) | 1988-10-26 |
Family
ID=10573357
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB858501827A Pending GB8501827D0 (en) | 1985-01-24 | 1985-01-24 | Clock extraction from coded data streams |
GB08601709A Expired GB2178272B (en) | 1985-01-24 | 1986-01-24 | Clock extraction from coded data streams |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB858501827A Pending GB8501827D0 (en) | 1985-01-24 | 1985-01-24 | Clock extraction from coded data streams |
Country Status (1)
Country | Link |
---|---|
GB (2) | GB8501827D0 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2200518A (en) * | 1987-01-30 | 1988-08-03 | Crystalate Electronics | Data pulse timing |
WO2016085600A1 (en) * | 2014-11-26 | 2016-06-02 | Qualcomm Incorporated | Symbol transition clocking clock and data recovery to suppress excess clock caused by symbol glitch during stable symbol period |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB1542655A (en) * | 1975-05-29 | 1979-03-21 | Teletype Corp | Decoding diphase signals |
EP0104761A2 (en) * | 1982-08-30 | 1984-04-04 | Xerox Corporation | Data and clock recovery system for data communication controller |
-
1985
- 1985-01-24 GB GB858501827A patent/GB8501827D0/en active Pending
-
1986
- 1986-01-24 GB GB08601709A patent/GB2178272B/en not_active Expired
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB1542655A (en) * | 1975-05-29 | 1979-03-21 | Teletype Corp | Decoding diphase signals |
EP0104761A2 (en) * | 1982-08-30 | 1984-04-04 | Xerox Corporation | Data and clock recovery system for data communication controller |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2200518A (en) * | 1987-01-30 | 1988-08-03 | Crystalate Electronics | Data pulse timing |
WO2016085600A1 (en) * | 2014-11-26 | 2016-06-02 | Qualcomm Incorporated | Symbol transition clocking clock and data recovery to suppress excess clock caused by symbol glitch during stable symbol period |
US9490964B2 (en) | 2014-11-26 | 2016-11-08 | Qualcomm Incorporated | Symbol transition clocking clock and data recovery to suppress excess clock caused by symbol glitch during stable symbol period |
Also Published As
Publication number | Publication date |
---|---|
GB8601709D0 (en) | 1986-09-17 |
GB8501827D0 (en) | 1986-09-17 |
GB2178272B (en) | 1988-10-26 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
732 | Registration of transactions, instruments or events in the register (sect. 32/1977) | ||
PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 19960124 |