GB2052925A - Means and method for encoding and decoding data signals recorded on information carrier - Google Patents

Abstract

In a random access system for use with apparatus for recording on and reproducing information from selectable portions of a video or audio information carrier, a bit code generator provides digital address signals in serial fashion which are synchronized with a stable time reference such as the 3.58 mHz color subcarrier embedded in a video signal to be recorded on the carrier. The recorded signals are sampled in the decoding process at a frequency which is also synchronized with the same time reference, so that the time relation between the bit codes and the sampling "slices" is invariant. Decoding of such signals may be accomplished reliably by means of relatively simple-computer software.

Description

SPECIFICATION Means and method for encoding and decoding data signals recorded on information carrier Background of the Invention and Prior Art The present invention relates generally to the storage and retrieval of information of high density and particularly to a method and system for encoding an information carrier by optical or electrical means with a series of data signals and thereafter decoding such data signals. The invention is especially useful in connection with apparatus#for accessing selectable portions of a video disc wherein predetermined addresses adapted to identify individual disc frames or tracks are recorded on and reproduced from the disc. The invention also comprehends an information carrier which is encoded with data signals, for example, multiple addresses as described herein.

There is no intention, however, to limit the invention to use with rotating information carriers such as video discs or to the encoding and decoding of address signals. The basic concepts of such invention are adaptable to video tape or any other media on which video and/or audio information is to be recorded. The data signals may represent any kind of alpha numeric information or other intelligence, such as, for example, programmed instructions governing the movement of a random-access video disc player arm.

In a memory system for recording and retrieving high density information employing an information carrier such as a video disc, each individual block or segment of information must be associated with a unique address in order to enable the random access of such block or segment. For example, a video disc may be composed of as many as 50,000 concentric tracks or frames, each representing the informational content of a complete TV picture. It is well known in this art to record on each frame, concurrently with its video content, a coded digital signal constituting the address of that frame by means of which the information may be retrieved. The location on a video disc frame normally selected for each address is within those portions of the frame occupied by the informationless part of an incoming video signal.The number of binary bits in the digital code depends upon the total number of frames to be encoded. For example, in order to encode 50,000 frames and assign a unique address to each frame requires a digital code consisting of sixteen bits, since 216 = 65,536.

An example of a prior art invention which teaches the encoding of a rotatable information carrier with a series of digital addresses in the manner described may be found in United States Patent No. 3,931,457 to Mes. In that patent, addresses are applied to successive concentric information video disc frames during the informationless portion thereof. In order to decode addresses recorded as described in Mes, in accordance with prior art methods, it is necessary to sample the digital information at time intervals short enough to enable a computer to interpret the data received in sufficient detail to determine whether a valid code is present, and if so, to decode the digital information and provide an appropriate visual or other indication.

Typically, each bit of a digital address code (or any digital data signal) consists of either of two preselected patterns of voltage "highs" and "lows", one such pattern indicating a binary "1" and the other a binary "0". To recover or decode such a digital address signal, the address information on a given frame is identified by standard circuitry and then divided into an arbitrary number of parts or "slices". The voltage value of each slice, "low" or "high", is then determined and loaded into a micro-computer for decoding. The micro-computer first determines whether a valid pattern of highs and lows is present for each bit in the entire address signal and if such valid patterns are found for the entire address, the computer decodes the signal and converts it into analog form for display purposes.

An inherent drawback in prior art decoders of the type described lies in the fact that the bit sample rate is not synchronized with the time reference which establishes the width of the encoded bits. Such asynchronism inevitably causes variations of indeterminate nature to occur in the relation between the samples and the bit patterns to be detected, as the computer "looks at" successive bits. The greater the number of bits in a given code, the more acute the problem becomes. Depending upon the number of bits in a code, the sampling rate, and the degree of sophistication of the decoding algorithm, this asynchronism may make it difficult or impossible for the computer to interpret the code as valid. A much more complicated decoding algorithm then becomes necessary in order to decipher the code.

This asynchronism problem may be partially alleviated by requiring a non-random start of the sampling process, so that, for example, the first "slice" coincides rather precisely with the start of the first bit of the address code. But to require such a non-random start imposes unreasonable hardware constraints. Increasing the slicing rate gives more accurate information about the sampled bit codes, but this approach also has drawbacks. For example, it requires more computer memory for processing, greater computer speed and more processing time is involved.

The inventors have, therefore, reasoned that synchronism between the time reference for the bit code pulses of a digital address signal or any other digital data signal and the frequency at which such signal is sampled is highly advantageous and that the use of this technique enables the selection of the lowest possible sampling rate and the simplest computer decoding algorithms consistent with reliability and short decoding time.

Summary of the Invention It is a general object of this invention to provide an improved method and system for encoding and/or decoding data signals from an information carrier.

it is a more specific object of this invention to provide an improved method and system for encoding and/or decoding address signals in digital form from an information carrier, such signals serving to identify selectable portions of such carrier.

It is a yet more specific object of this invention to provide an improved method and system for encoding on and/or decoding address signals in digital form from a video disc, such signals serving to identify such frames or tracks thereof.

-It is a further object of this invention to provide an information carrier on which address signals are encoded identifying selectable portions of such carrier in a manner to facilitate decoding of such signals.

in accordance with the preferred embodiment of this invention a system is disclosed for use with apparatus for recording on and/or reproducing video and/or audio information from selectable portions of an information carrier, such as a video disc or video tape, which comprises means for encoding and decoding address signals in digital form on such carrier, such signals being adapted to identify selectable portions of such carrier, for example, the individual frames or tracks of a video disc. The encoding means includes a serial bit code generator for generating serial bit codes to be encoded on designated portions of the information carrier, the code numbers being increased in magnitude from one address location to the next by means of a counter geared to the position of the recording means in relation to the information carrier.The bit code generator is synchronized with a time reference of stable frequency inherent in the associated recording and reproducing system or embedded in the incoming video signal.

The decoding means includes means for sampling or "slicing" the encoded signal at a rate which is synchronized with the same time reference so that the slices maintain a known, though not necessarily static, relation with the pattern of the bit code. To facilitate maximum simplicity in the decoding software, the sampling process is timed so that each bit in the entire code is intersected by the sampling slices at precisely the same time intervals along its width.

A signal ideally suited for the common time reference for encoding and decoding in accordance with this invention is the color subcarrier embedded in a broadcast video signal, which, under the NTSC system in the Unites States, is 3.58 mHz or the analogous frequency under the PAL system in Europe.

ln order to build further redundancy into the encoding/decoding system of this invention, a bit code pattern is employed wherein each binary "zero" or binary "one" begins with a rising pulse. In addition, each such bit has unequal portions of ''high'' and ''low'' voltage portions.

These features render a code easier for a computer to identify even if asynchronism is involved.

The invention further comprises the method carried out by the above system and the information carrier having address signals recorded thereon in accordance with such method.

Brief Description of the Drawings Figure 1 is a block diagrammatic representation of a system for encoding address signals on a video disc in accordance with this invention.

Figure 2 is a block diagrammatic representation of a system for decoding address signals from a video disc in accordance with this invention.

Figures 3a and 3b are graphic representations of the voltage bit patterns indicative of a binary "1" and a binary "0" respectively, in accordance with this invention.

Figure 4 is a graphical representation of a digital address signal composed of binary bits, with portions removed, on which are superimposed a series of sampling "slices", all in accordance with this invention.

Figure 5 is a graphical representation of a digital address signal composed of binary bits, with portions removed, on which are superimposed a series of sampling "slices", in accordance with the prior art.

Figure 6 is a diagrammatic representation of a portion of the digital address signals encoded on a video disc in accordance with this invention.

Description of the Preferred Embodiment For illustrative purposes, this invention will be described and illustrated as applied in encoding and decoding address signals on a video disc although it is readily adaptable for use with other types of information carriers. However, since the video disc is particularly suited to rapid random access of any selected frame or other portion of the information carried on such disc, the importance of the invention is best appreciated in that environment.

Encoding With reference now to Fig. 1, a system is illustrated in block diagrammatic form for encoding address signals on the frames of a video disc in accordance with a preferred embodiment of this invention. A video signal supplied from any suitable source 10, such as a TV camera, is analyzed by a video processor 12 in order to extract needed information, thereafter amplified, and fed through mixer stage 14 to a laser modulator 16 which modulates a laser beam (not shown) focused on the surface of a rotating video disc 18.

The video signal is optically recorded on disc 18 as either a series of concentric tracks or frames or as a single spiral track. For the purposes of this invention, either method is acceptable. In accordance with United States practice under the NTSC system, 525 horizontal lines of the incoming video signal constitute a complete picture which is recorded on a single frame constituting a complete revolution of disc 18. A small number of these horizontal lines are informationless in order to accommodate vertical retrace of the video signal. Each such horizontal line is initiated by a horizontal sync signal and the remainder is available for adding any desired data. This informationless portion of each video frame therefore constitutes a convenient location within which to record an address signal in digital form.

A bit code generator 22, interconnected with processor 12, is adapted on command to generate serial bit codes representing or identifying successive frames on disc 18. Processor 12 contains an internal 3.58 mHz oscillator 24 which locks onto the color subcarrier of the same frequency embedded in the video signal from source 10. Processor 12 supplies two signals to generator 22, a signal 25 representing the color subcarrier frequency and a horizontal sync signal 26 appearing at the start of each horizontal line. The color subcarrier constitutes a highly stable time reference which generator 22 employs to establish and control the width of each bit in the digital address code to be recorded. The significance of this selection will become apparent from what follows.

The purpose of providing horizontal sync 26 to generator 22 is to trigger the start of each bit code. As long as a given frame is being recorded, generator 22 produces the same bit code on every one of the 525 lines constituting such frame. Processor 12 supplies a gate pulse 28 to open line gate 30 each time a selected informationless line, such as line 13, or its counterpart on the opposite side of the disc, such as line 276, appears, so that a given coded signal is supplied to mixer 14 and recorded twice on each disc frame.

Responsive to the relative position of the modulated laser beam and the disc 18, disc stage 32 causes counter 34 to step the coded address signal from one number of the next higher in sequence, so that a unique address is recorded with each frame.

Decoding To decode address signals recorded as set forth above, appropriate photo detector optics 40, focused on disc 18, transmit a video signal carrying information received from disc 18 to video processor 42. From processor 42, the information on selected lines such as lines 13 and 276, i.e. the previously recorded address signal, is fed to signal level detector 46 which compares these address signals with a plurality of arbitrary DC voltage references 48, for example, four as shown.

Sampling signals generated within timing and control section 50 determine the voltage value of the address signal at these different levels and the results are loaded into memory 44. The sampling signals are synchronized through connection 52 with a 3.58 mHz oscillator 53 in processor 42. Oscillator 53 in turn locks onto the 3.58 mHz signal inherent in the recorded video signal. A line decode signal 54 from processor 42 directs micro-computer 56, through timing and control section 50, to access the address signals in memory 44 and determine if any of the four levels of such signal represents a valid code. If so, the code is analyzed and transmitted to frame number display 58.

The 3.58 mHz signal is employed by timing and control section 50 to generate the sampling slices. The time separation of the sampling slices and the width of each binary bit in the address signal are thus derived from a common time reference. The advantage of this procedure is best understood by examining the sampling or slicing procedure in greater detail.

Sampling In accordance with this invention and in distinction to the known prior art, it is found advantageous to select a bit pattern for a binary "0" and a binary "1" as shown in Figs. 3a and 3b, respectively. Both the binary "0" and the binary "1" begin with a rising voltage pulse so that there is always a positive indication when the first bit of a code formed with these patterns is present. Both the binary "0" and the binary "1" have the same bit width.To insure adequate distinction between the two patterns, the high voltage portion of the binary "1", t', is made three times the width of the high portion of the binary "0", t,, and conversely the low voltage portion of the binary "1", t'2, is one-third the width of the low portion of the binary "O", t2 Turning now to Fig. 4, there is shown a portion of a recorded digital address code in accordance with this invention, which is adapted to be sampled as described in connection with Fig. 2. Each bit is patterned in accordance with Figs. 3a and 3b and is divided into eight equal time units. Bit 1 through Bit 8, therefore, comprise time units numbered from 1 to 64.

Superimposed on these bit patterns are sampling "slices" numbered 1 through 65 as indicated by dotted lines, slice number 1 being arbitrarily selected to occur 0.5 time units prior to the start of the leading edge of bit number 1 to indicate random start. Since both the bit width and the slicing width are related to the same 3.58 mHz frequency, any convenient relationship between these two widths can be selected and maintained. For example, it is convenient to provide a slice width which is exactly equal to one time unit as above defined, i.e. 1 /8th the width of one bit. Assume for purposes of illustration that a relatively simple decoding software algorithm is employed by micro-computer 56 in the decoder of Fig. 2 which registers a "valid" code if the two slices at the beginning and end of each bit in the code of Fig. 4 form in combination a (high, low) pair.It is at once apparent that there is no change in the time relation between the sampling slices and the bit pattern from bit 1 through bit 8. Table I below includes information equivalent to that of Fig. 4 but in tabular form, and illustrates the fact that no such change occurs.

TABLE I

Time Slice No. (Units) Slice Value Bit Validity 1 .5 Low 2 0.5 High 3 1.5 High 4 2.5 Low 5 3.5 Low Bit 1, 6 4.5 Low Valid 7 5.5 Low 8 6.5 Low 9 7.5 Low 10 8.5 High 11 9.5 High 12 10.5 High 13 11.5 High Bit 2, 14 12.5 High Valid 15 13.5 High 16 14.5 Low 17 15.5 Low 50 48: :5 50 48.5 High 51 49.5 High 52 50.5 High 53 51.5 High Bit 7, 54 52.5 High Valid 55 53.5 High 56 54.5 Low 57 55.5 Low 58 56.5 High 59 57.5 High 60 58.5 Low 61 59.5 Low Bit 8, 62 60.5 Low Valid 63 61.5 Low 64 62.5 Low 65 63.5 Low For example, slice pairs (2,9); (10,17); (50,57); and (58,65) are all seen by the computer as compatible with (high, low) bit patterns and hence the signal as a whole is determined to be valid and decodabie. Obviously, mathematically exact time equivalence between the slice width and the width of a time unit is an impossibility. But the frequency stability of the color subcarrier necessary to achieve sufficiently error-free equivalence in any practical application of this invention is significantly less demanding than that required for reproduction of a highquality color video signal. This makes the color subcarrier a particularly successful choice for the common time reference to be employed in the method of this invention.Even if there is any minor variation of this time reference, the very fact that it controls both bit width or recording and slicing interval on playback tends to cancel the effect of any such variation.

In the example of Fig. 4 and Table I, the ratio between the bit width and the slicing interval or width is not only constant but it is a whole number, thus insuring that the slices look at each bit at the same points along its width as the sampling process progresses. This permits the use of a relatively simple decoding software as outlined. However, within the scope of this invention, it is only necessary that this ratio, as established by the common time reference, be a known constant. As a result, the voltage values of successive bits may be determined at different points along their respective widths. But, this is a variance whose effects are predetermined and for which appropriate decoding software can be written with moderate increase in complexity.

In order to appreciate the damaging effect of asynchronism between the address encoding and sampling procedure, it is useful to compare the results of Fig. 4 and Table I with a hypothetical prior art case.

Prior Art Sampling Method Fig. 5 is a graphic representation of a hypothetical series of binary bits employing an arbitrary pattern and labeled as "BIT 1" through "BIT 8", collectively representative of some or all of a recorded digital address signal. Fig. 5 and the accompanying Table II are introduced at this point to illustrate a shortcoming of prior art signal sampling procedures. Each bit in Fig. 5 consists of an initial "high" voltage portion followed by a "low" voltage portion. Each bit is also divided arbitrarily into eight equal time units represented by the timing marks numbered "0" through "64". Superimposed on the pattern of bits are evenly spaced "slices" represented by dotted lines numbered consecutively beginning with slice No. 1, which occurs at a random time relative to time "0".In the example shown, slice No. 1 begins 0.49 time units prior to time "0" which is coincident with the leading edge of BIT 1.

Assume a form of computer software comparable to that suggested for decoding in connection with Fig. 4 is employed to "look for" a (high, low) pair every eight time units, repeated eight times. Such software is easily confused by small changes in the way the sampling slices intersect the bit patterns. If the time between slices, or slice "width" is not equal to the bit time unit or an exact multiple or submultiple, but rather differs from it by a small error factor, this error becomes cumulative and may prevent the computer from detecting a valid bit pattern by the time the last bit of a code is read. Fig. 5 illustrates the hypothetical case in which the slice width without knowledge or intent of the circuit designer is .99 times the bit time unit, i.e. the slice rate is 1 percent low.This may easily result if different time references control the bit code generator and the sampling process. By the time the 61 sot slice is reached the valid "high", "low" bit pattern is no longer present. The reason for this is made clear by examination of the Table II below, which lists the successive slices of Fig. 5 by number, the time of occurrence of each in relation to the time units, the resultant voltage values determined by the computer software, and the validity or invalidity of each bit so detected.

TABLE IT (Prior Art)

Time Slice No. (Units) Slice Value Bit Validity 1 -0.49 Low 2 0.50 High 3 1.49 High 4 2.48 High 5 3.47 High Bit 1, 6 4.46 Low Valid 7 5.45 Low 8 6.44 Low 9 7.43 Low 10 - 8.42 High 11 9.41 High 12 10.40 High 13 11.39 High Bit 2, 14 12.38 Low Valid 15 13.37 Low 16 14.36 Low 17 15.35 Low 50 48.02 High 51 49.01 High 52 50.00 High 53 50.99 High Bit 7, 54 51.98 Low Valid 55 52.97 Low 56 53.96 Low 57 54.95 Low 58 55.94 Low 59 56.93 High 60 57.92 High 61 58.91 High Bit 8, 62 59.90 High Invalid 63 60.89 Low 64 61.88 Low 65 62.87 Low Slice 61 falls just prior to the end of bit 7 rather than at the start of bit 8. This causes slice 58 to register as a "low". Thus, slices 58 and 65 register together as a (low, low) pair instead of a (high, low) pair and bit 8 appears invalid. As a result, the computer finds the entire code to be invalid.

It is apparent from the above example, that the greater the error, high or low, or the greater the unintentional, unplanned for lack of correspondence between the bit time unit and the slice width or interval, the sooner the slicing operation will produce an invalid bit pattern with a given type of decoding software. The greater the number of bits in an address code, the more serious this lack of correspondence becomes. A purpose of this invention is, therefore, to eliminate this error factor thereby simplifying the task of decoding software of any given degree of sophistication, and increasing the reliability of the entire system. It should be understood that the problem inherent in the slicing procedure outlined in Fig. 5 is not simply that of a variance in the way successive bits are intersected by the sampling slices but also the fact that since this variance isn't known, its effect cannot be allowed for in the decoding software. As a practical matter, of course, if such a variance is produced intentionally, i.e. by reference to a common time reference in accordance with the present invention, the relation between the arbitrary bit time unit and slicing interval is preferably such that the slice-to-bit pattern relation is cyclic. For example, with such a relation, every fourth bit may be sampled in identical fashion. This then provides the necessary information on which to base a relatively uncomplicated decoding software algorithm.

Illustrative Example Consider now the following practical example of the use of a frame address signal encoding and decoding system and method in accordance with this invention. Assume a 5,000 frame video disc on each frame of which a unique address signal is to be recorded along with a video signal. This may be done by means of a thirteen bit code, since this will accommodate 2'3 or 8,1 92 distinct numbers. Assume further that it is desirable to record each entire 13 bit signal on a single video line.Simple calculations will show that, given the time available per line exclusive of the horizontal sync pulse, one may allocate precisely 16 cycles of the 3.58 mHz color subcarrier of the incoming video signal to each bit, yielding a bit width of 1.1174604 micro-seconds, for a total signal width of 58. 107942 micro-seconds. Each cycle of the color subcarrier is 279.36511 nano-seconds in length so that if one chooses a slicing width equal to two (2) cycles of the subcarrier, there are precisely eight slices per bit or one hundred four slices for the entire thirteen bit signal.With the type of accuracy which may be expected by using the color subcarrier as the common time reference for bit width and slice width, it is apparent that in one hundred four slices no discernible time shift between slices and bit pattern will occur to confuse even a very simple form of decoding computer software.

Fig. 6 is a diagrammatic representation of a portion of a thirteen bit address code patterned in accordance with the teachings of this invention and recorded on a single line such as line 13 of the frames on a video disc. In the illustration of Fig. 6, twenty such frame addresses have been shown, represented digitally as the numbers 1 through 20, each beginning after the horizontal sync pulse is recorded.

If a larger number of frames must be accomodated, the number of bits may clearly be increased as necessary and several informationless lines may be employed to record a single address signal if the length of the code requires it. It should also be understood that there is no requirement that the same line or lines on each frame be employed to record successive address signals so that radial alignment of such signals is not a requirement. The address signals may, for example, follow a spiral pattern utilizing all of the available informationless lines as the disc recording progresses from center to periphery or vice versa.

Within the scope of this invention, it should be understood that the signals recorded and encoded as described need not be limited to address signals or limited to digital form, nor are the various details of the associated encoding and decoding systems described to be regarded as other than illustrative. For example, an analog signal such as a ramp function may be selected for each address code with the slope of the ramp being the variable corresponding to successive address locations, or, alternatively, the address signals may consist of frequency modulated codes of constant amplitude. In either case the resultant signals are amenable to a sampling process in decoding wherein the relation of the sampling process and the code generator means to a common time reference produces the beneficial results detailed above.Those skilled in the electronics art will readily be able, without the exercise of further invention to apply the teachings described herein to such other forms of data or address signals.

It is additionally emphasized that there is no intent to limit the use of this invention to the employment of the 3.58 mHz color subcarrier, as any well defined frequency may be used as long as both the address signal and the sampling slices are derived therefrom. For example, the data signals on alternate frames of a video disc may easily be related to a 3.58 mHz NTSC subcarrier and the corresponding PAL system subcarrier, respectively.

An information carrier, such as a video disc on which is recorded an address signal synchronized with a stable frequency source inherent in the recording systems, such as a color subcarrier, is itself an aspect of the invention described herein and all such carriers so recorded are, therefore, included within its scope.

Claims (33)

1. In a method for encoding data signals for recordation on an information carrier and thereafter decoding and reproducing such data signals, wherein the decoding of such recorded signals after recordation includes sampling thereof at predetermined intervals, the improvement comprising the steps of (a) relating said encoded data signals to one or more stable time references, and (b) synchronizing the intervals at which such signals are thereafter sampled with said stable time references.

2. A method of Claim 1 wherein said data signals are encoded digitally.

3. A method of Claim 1 wherein said data signals are encoded as analog signals.

4. The method of Claim 1 wherein said data signals are frequency modulated.

5. The method of Claim 1 wherein said data signals are address signals adapted to identify selectable portions of said information carrier.

6. In a method for encoding and decoding data signals in digital form on an information carrier, the improvement comprising the steps of: generating a series of binary bit codes representative of said data signals, synchronizing the formation of each of said data signals with a stable time reference in a manner such that the width of each bit is a first multiple of the width of each cycle of said stable time reference, and detecting said data signals by sampling each of said bit codes at intervals whose width is a second multiple of each cycle of said stable time reference.

7. The method of Claim 6 wherein the ratio between said first and second multiples is a whole number.

8. The method of Claim 6 wherein said information carrier is adapted to record a video signal and wherein said stable frequency is inherent in said signal.

9. The method of Claim 8 wherein said inherent signal is a color subcarrier.

10. The method of Claim 9 wherein said color subcarrier has a frequency of 3.58 mHz.

11. The method of Claim 6 wherein said data signals are address signals adapted to identify selectable portions of said information carrier.

12. In a random access system for use with apparatus for recording on and/or reproducing information from selectable portions of an information carrier, a method of encoding address signals in digital form for recording on an information carrier so as to identify such selectable portions thereof comprising the steps of: generating a series of binary bit codes each representing a unique address signal and synchronizing the formation of each of said signals with a stable time reference inherent in said information recording and/or reproducing apparatus so that the width of each bit is an exact multiple of the width of each cycle of such stable time reference.

13. The method of Claim 12 wherein said time reference is inherent in the information signal to be recorded on said carrier.

14. The method of Claim 13 wherein said information signal is a video signal and said time reference is a color subcarrier.

15. For use with apparatus for recording on and/or reproducing information from addressable portions of an information carrier, a system for encoding data signals in digital form on said information carrier and for decoding said data signals comprising means for generating a series of binary bit codes representative of said data signals, means for synchronizing the formation of said data signals with a stable time reference inherent in said information recording and/or reproducing apparatus so that the width of each bit is an exact multiple of the width of each cycle of said time reference and means for detecting said data signals including means for sampling each of said bit codes at a frequency such that the interval between samples is a second exact multiple of each cycle of said time reference.

16. A system as in Claim 15 wherein each of said binary bits begins with a rising pulse portion.

17. System as in Claim 16 wherein each of said binary bits comprises unequal voltage high and low portions.

18. A system as in Claim 17 wherein the high voltage portion of a bit representing a binary "0" is shorter in length than the high voltage portion of a bit representative of a binary "1".

19. The system of Claim 15 wherein said stable frequency is a video signal color subcarrier.

20. A system as in Claim 19 wherein said color subcarrier is 3.58 mHz.

21. A system as in Claim 15 wherein said sampling means includes means for sampling each of said encoded data signals at a plurality of reference voltage levels to determine if a spurious code is present.

22. The system of Claim 15 wherein said information carrier is a video disc and each of said selectable portions thereof is a frame consisting of one entire video picture.

23. A system as in Claim 15 wherein said information carrier is video tape.

24. An information carrier for recording video information wherein digital data signals are encoded on said carrier each of said data signals consisting of a series of binary bits whose width is an exact multiple of the color subcarrier of said video signal.

25. An information carrier as in Claim 24 wherein said data signals are address signals adapted to identify selectable portions of said carrier.

26. An information carrier as in Claim 25 wherein said selectable portions of said information carrier are concentric frames thereon.

27. An information carrier as in Claim 24 wherein said carrier is a video disc.

28. An information carrier as in Claim 26 wherein each of said bit codes begins with a rising pulse portion.

29. An information carrier as in Claim 24 wherein said carrier is recorded magnetically.

30. An information carrier as in Claim 24 wherein said carrier is recorded optically.

31. A method for encoding and decoding data signals on an information carrier substantially as hereinbefore described with reference to the drawings.

32. A system for encoding and decoding data signals on an information carrier substantially as hereinbefore described with reference to and as shown in the accompanying drawings.

33. An information carrier for recoding video signals substantially as hereinbefore described with reference to the accompanying drawings.