GB2198899A - Circuit arrangement with two serially connected high-voltage switches - Google Patents

Abstract

A pair of transistors (TR1, TR2) are serially connected through an inductor (L) to a supply with associated components connected to the transistors which determine various periods of operation. In order to ensure that the transistors (TR1, TR2) are rendered non-conducting simultaneously sensors (S1, S2) sense their change in base current to produce pulses in monostable multivibrators (M1, M2) whose relative phases are compared in a digital phase comparator (PC). The drive for each transistor (TR1, TR2) from its associated driver stage (DR1, DR2) is via an associated device (DC1, DC2) having a characteristic used to control the cut-off of its associated transistor one of the devices (DC2) having a variable characteristic which is controlled by the output of the phase comparator (PC) to ensure the required simultaneous non-conduction. <IMAGE>

Description

DESCRIPTION: "CIRCUIT ARRANGEMENT WITH TWO SERIALLY CONNECTED HIGH-VOLTAGE SWITCHES" The invention provides a circuit arrangement comprising first and second high-voltage power switches connected in series, control means for repeatedly cutting off each of the switches, which control means are connected to a signal source for producing a drive signal for each of the switches, the control means for each switch comprising a device having a characteristic which is used in the control of the drive signal for its associated switch, and a comparison stage for controlling the characteristic of one of the devices in order to ensure that the high-voltage power switches are automatically cut-off substantially simultaneously.

A circuit arrangement of the above type is described in Published European Patent Application No. 0 110 461 Al. The arrangements described in that published application sense the voltage at the junction of the two switches and compares it with a reference voltage, the resulting comparison being used to control the characteristic of one or each device which in this case are formed by delay devices whose characteristic is their delay period.

The operation of this arrangement relies on the output circuit being balanced with an inductor connected to the main current path electrodes of the two switches which are not connected to each other. Whilst such an arrangement might be quite satisfactory when operating at a single frequency it is not so satisfactory in the case where the arrangement is intended to operate at different flyback times, such as in the case of a line output stage of a data graphics display where it is desired to obtain supplies from the line output transformer which is formed in part by the above inductors and where a number of taps have to be provided to cater for the changes in flyback time.

Zt is an object of the present invention to provide a circuit arrangement of the above type which can be used to overcome the above difficulty.

The invention provides a circuit arrangement comprising first and second high-voltage power switches connected in series, control means for repeatedly cutting off each of the switches, which control means are connected to a signal source for producing > drive signal for each of the switches, the control means for each switch comprising a device having a characteristic which is used in the control of the drive signal for its associated switch, and a comparison stage for controlling the characteristic of at least one of the devices in order to ensure that the high-voltage power switches are automatically cut-off substantially simultaneously, characterised in that said arrangement additionally comprises means for producing a pulse for each respective switch when said switches are cut-off, means for applying the pulses so produced to said comparison stage in which the phase relationship between the pulses for the first and second switches are compared to produce the control for the characteristic of the said one device.

The invention has the advantage that by not having to sense the voltage at the junction of the two switches means that these switches do not have to be part of a balanced circuit and a single load, such as the primary of a transformer, can be connected between the switches and its associated supply. It also has the advantage that if used in a balanced circuit it is independent of any imbalance that might be present.

For an arrangement where the first and second switches comprise respective first and second bipolar transistors it may be further characterised in that the means for producing a pulse for each respective switch at cut-off comprises first and second sensors respectively coupled to the base of the first and second transistors for sensing the change of base current in each transistor at cut-off, the first and second sensors being connected to respective first and second pulse generators each of which produces a discrete pulse when the transistor with which it is associated is cut-off.

Advantageously, each sensor may be in the form of a current transformer.

A preferred embodiment of the invention is characterised in which each pulse generator is a gated monostable multivibrator whose gating signal is derived from the signal source. In such a case both monostable multivibrators may be formed by a single integrated circuit.

The above and other features of the invention will now be described, by way of example, with reference to the accompanying drawings, in which: Figure 1 is a diagram, partly in block form, of a circuit arrangement according to the invention, Figure 2 shows various idealised waveforms associated with the operation of the circuit arrangement of Figure 1, Figure 3 is a modified diagram of the circuit arrangement of Figure 1, Figure 4 shows various idealised waveforms associated with the operation of the circuit arrangement of Figure 3, and Figure 5 is a more detailed diagram of the circuit arrangement as shown in Figure 3.

Figure 1 is a diagram, partly in block schematic form, of a line deflection circuit having a line output stage for energising a line deflection coil Ly. The line output stage comprises first and second controlled switches in the form of high voltage npn bipolar power switching transistors TR1 and TR2 with the collector of transistor TRI being connected to a voltage supply B+ through an inductor L whilst its emitter is connected to the collector of transistor TR2 whose emitter is connected to earth. The inductor L may be the primary of a transformer the secondary windings of which supply respectively the eht supply for the final anode of a display tube associated with the deflection circuit and the low voltage supply or supplies for other parts of the circuit.A diode D1 and a retrace capacitor CR1 are each connected in parallel with the transistor TR1 whilst a diode D2 and retrace capacitor CR2 are similarly connected in parallel with transistor TR2. A trace capacitor CT and the deflection coil Ly are serially connected between the collector of transistor TR1 and earth.

The line output stage operates in known manner with the voltage stored in trace capacitor CT producing the required sawtooth current through deflection coil Ly which initially flows through the diodes D1 and D2 for a first part of a trace period and subsequently through the transistors TR1 and TR2 through a second part of a trace period to produce the required sawtooth deflection current in the deflection coil Ly. The retrace period is initiated by rendering transistors TR1 and TR2 non-conducting by the negative going edge of the drive pulse which is applied to their bases, these transistors having been previously rendered conducting prior to or at the commencement of the second part of the trace period.During the retrace period the inductance and capacitance in the line output stage resonate to produce a half sine wave flyback pulse which is followed by the start of a further trace period. For optimum operation the two transistors TR1 and TR2 should become non-conducting simultaneously otherwise there will be unequal power sharing between the two transistors which could lead to the damage of one transistor or at least the peak voltage will be reduced which in turn would reduce the eht supply when derived from this stage.

Although both transistors may receive at the same time a signal to cut them off simultaneous non-conduction may not be achieved as the storage times of the charge carriers in the transistors may not be equal and may vary with time and temperature. In order to ensure simultaneous non-conduction the transistors are driven in the manner as further described.

A line oscillator stage LO produces pulses at line frequency which pulses are applied from its output to the respective input of a first (DR1) and a second (DR2) driver stage. The output of driver stage DR1 is applied to the input of a device DC1 having a characteristic which is used to control the cut-off signal for transistor TR1, the drive pulse from the device DC1 being applied via a first sensor S1 to the base of transistor TR1.In a similar manner the output of the second driver stage DR2 is applied to the input of a second device DC2 having a variable characteristic which is used to control the drive pulse for transistor TR2 the variation in the characteristic depending upon a signal applied to its control input C, the resulting drive pulse from the device DC2 being applied by a second sensor S2 to the base of transistor TR2.

In one form the devices DC1 and DC2 may be delay stages where the characteristic is their delay period, that for device DC1 being fixed whilst that for device DC2 being variable. Each of the sensors S1, S2 senses the base current of its associated transistor TRI, TR2 and the resulting signal is applied to the input of an associated pulse generator in the form of a gated monostable multivibrator M1, M2. As each transistor TR1, TR2 becomes non-conducting there is a drop in its base current which is sensed by the sensors S1, SZ and applied to the associated monostable M1, M2 to trigger it into its non-stable state. In addition to the input from the sensor, each monostable receives at a further input a gating pulse from the output of the oscillator LO to ensure that the multivibrator is not triggered by other pulses during the remaining part of the line period.The pulse outputs from the monostables M1, ,M2 are applied to respective inputs of a digital phase comparator PC in which the relative phases of the pulses are compared and a voltage produced whose amplitude depends on their phase difference.

This voltage is applied from the output of the phase comparator PC to the control input C of the device DCZ with the variable characteristic which adjusts this characteristic to cause transistor TR2 to become simultaneously non-conducting with transistor TR1.

Where the devices DC1 and DC2 are delay stages the delay period provided by device DC2 is varied to change, if necessary, the time at which the drive pulse is applied to the base of transistor TR2 with respect to that applied to the base of transistor TR1.

Figure 2 shows various idealised waveforms associated with the line deflection circuit of Figure 1 when the devices DC1 and DC2 are delay stages. Figure 2A shows the output of the line oscillator LO used for driving the transistors TR1 and TR2 and also for gating the monostables M1 and M2. The base current for transistor TR1 is shown in Figure 2B which starts to reduce in magnitude at times t1, t10 on receipt of the negative going drive pulse which is delayed by the delay stage DC1 and inverted by driver stage DR1 with respect to the pulse shown in Figure 2A. The charge carriers in transistor TR1 are then removed with the base current reversing in polarity until times t2, t20 when the transistor comes out of saturation and the transistor is very rapidly cut-off to initiate the flyback period.

At times t3, t30 during the following scan period transistor TR1 becomes forward biased when a positive pulse is applied to the base of this transistor and derived from the line oscillator pulse in Figure 2A. This cycle is then repeated. Figure 2C shows the voltage induced by the sensor S1, a sharp rise or fall in this voltage being produced with the changes in transistor TR1 base current. Monostable M1 is triggered by a positive going edge in the presence of a gating pulse (Figure 2A), this condition occurring at times t2, t20 and the pulses produced at the output of monostable M1 are shown in Figure 2D, these pulses being limited in duration by the negative going edge of the gating pulses.

The base current for transistor TR2 is shown in Figure 2E which also starts to reduce at time t1 it being assumed that initially the delay times of delay stages DC1 and DC2 are the same. It is assumed that the storage time for the charge carriers in transistor TR1 is shorter than that for the transistor TR1 and that transistor TR2 )comes out of saturation at time t2'. Figure 2F shows the voltage induced by the sensor S2 and Figure 2G the resulting pulses produced by monostable M2 which pulses are of longer duration than that for monostable M1.The relative phase of these two pulse outputs are compared in the phase comparator PC and the resulting control signal is used to increase the delay period produced by delay stage DC2 such that the negative going pulses are applied to the base of transistor TR2 at times t1,, t10' with the result that the times at which this transistor comes out of saturation are coincident with times t2, t20 for transistor TR1, this being shown in broken lines in Figure 2E.

In the description of the arrangement of Figure 1 the drive stages DR1, DR2 are placed before the devices DC1, DC2. It will be appreciated that in the cases where these devices are delay stages it makes no difference to the operation if the delay stages precede the driver stages DR1, DR2. In addition, whilst only device DC2 is described as providing a variation of the device characteristic it is possible to make the other device DC1 also variable which would be controlled by a complementary control signal from the phase comparator PC -such that as the characteristic of device DC2 is changed in one direction the characteristic of device DC1 is changed in the other direction.With such an arrangement the degree of characteristic variation can be less than that provided by device DC2 when that is the only one which is variable.

Figure 3 shows in more detail parts of the line deflection circuit shown in Figure 1, corresponding reference symbols indicating like components in the two figures. In Figure 3 the drive stages DR1, DR2 are formed by a driver transistor TR3 whose base is connected to the output of the line oscillator LO whilst its emitter is connected to earth. The collector of transistor TR3 is connected through the primary windings, connected in parallel, of respective driver transformers T1, T2 and a resistor R1 to the positive terminal of a low voltage supply B. The lower end of the secondary winding of transformer T1 is connected to the junction between transistors TR1 and TR2 whilst its upper end is connected to the input of device DC1 which consists of a capacitor C1 connected in paralleL with a resistor R2.In this case the characteristic control Led by the device DC1 is the amplitude of the forward drive base current. The resistor R2 and capacitor C1 together with the leakage inductance of transformer T1 are selected to provide the required drive for transistor TR1. The sensor SI comprises a current transformer with the primary winding (which may in practice be a straight conductor) connected between the device DC1 and the base of transistor TR1. The lower end of the secondary winding of transformer T2 is connected to earth whilst its upper end is connected to the input of device DC2 which comprises a capacitor C2 connected in parallel with the series arrangement of a resistor R3 and a npn transistor TR4 which together with the leakage inductance of transformer T2 are selected to provide the drive for transistor TR2, the base of transistor TR4 forming the control input C for this device. Sensor S2 takes the same form as sensor S1 with the primary winding being connected between the device DCZ and the base of transistor TR2. The use of the variation of the amplitude of the drive to the base of a high voltage bipolar transistor to control its turn-off characteristic is described in more detail in our co-pending application United Kingdom patent application number ......... (S85-109(2) - PHB ).One end of the secondary windings of each of the sensors S1 and S2 are connected to earth whilst the other end of each secondary winding is connected to their associated monostable M1, M2 which in this case take the form of a dual monostable multivibrator. The output of the phase comparator PC controls the degree of conduction of transistor TR4 and hence its resistance to vary the amplitude of the drive pulse at the base of transistor TR2.

Figure 4 shows various waveforms associated with the line deflection circuit of Figure 3, the waveforms in Figures 4A to 4G corresponding to the waveforms in Figures 2A to 2G. As there is no intended delay in the paths between the line oscillator LO and the bases of transistors TR1 and TR2 these transistors commence turn off at the same time. It is assumed initially that the amplitude of the drive current from device DC1 is the same as that from device DC2 and that with such a current the charge carriers in transistor TR2 take less time to leak away than the charge carriers in transistor TR1.As a result transistor TR1 comes out of saturation at times t2, t20 whilst transistor TR2 comes out of saturation at the earlier times of t2', t201. As a result of this there is a phase difference between the outputs of the monostables M1 and M2 as shown in Figures 4D and 4G respectively, this difference being compared in the phase comparator PC and the resulting control signal used to reduce the resistance presented by transistor TR4 present in the device DC2 to increase amplitude of the drive current applied to the base of transistor which increases the charge carriers in that transistor and hence the time required for these charge carriers to leak away.

This is shown in broken line in Figure 4E such that times t21, t201 have become coincident with times t2, t20.

Figure 5 is a more detailed diagram of the line deflection circuit shown in Figure 3, corresponding reference symbols again indicating like components in the two figures. Only those parts of the circuit which differ from Figure 3 will be described. The output of the line oscillator LO, which may be formed by a suitable integrated circuit is connected to the base of an npn emitter follower stage transistor TR5 whose emitter is connected through the parallel arrangement of a capacitor C3 and a resistor R5 to the base of driver transistor TR3. The emitter of transistor TR5 is also connected through a resistor R4 to earth whilst its collector is connected to the positive supply rail B which may be at 12 volts.

The primary winding of each driver transformer T1, TZ is shunted by the series arrangement of a capacitor and a resistor providing damping (C4, R6 in the case of T1 and C5, R7 in the case of T2).

The gated dual monostable multivibrator M1, M2 is an integrated circuit of type HEF 4528B data for which can be found in the Philips Data Handbook, Integrated circuits, Part 4, July 1983, Digital Integrated Circuits - CMOS, pages 551 to 556, the pin numbers and designations used in Figure 5 corresponding with those used in the published data. A timing capacitor C6 is connected between pins 1 and 2 (CTCA and RCTCA) whilst a resistor R8 is connected between pins 2 and 16 via the B supply rail (CTCA and VDD), the natural duration of the output pulse from the monostable Ml which appears at pin 6 (OA) (in the absence of the gating pulse) being determined by capacitor C6 and resistor R8.In a similar manner a capacitor C7 is connected between pins 14 and 15 (CTcB and RCTCB) and a resistor R9 between pins 14 and 16 (CTCB and VDD), the natural duration of the output pulse from the monostable M2 which appears at pin 10 (Os) being determined by capacitor C7 and resistor R9.

The gating pulses for the monostables M1, M2 are derived from the local oscillator LO output which is connected via the parallel arrangement of a capacitor C8 and a resistor R10 to the base of an npn transistor TR6, this base also being connected to earth by way of resistor R11. The collector of transistor TR6 is connected through a resistor R12 to the B supply rail and directly to the base of a further npn transistor TR7 whose emitter is connected to earth as is the emitter of transistor TR6. The collector of transistor TR7 is connected through a resistor R13 to the 8 supply rail and supplies buffered gating pulses of the correct polarity directly to pin 3(CDA) for monostable M1 and pin 13 (CDB) for monostable M2.

The digital phase comparator PC is formed by part of a phase-locked loop integrated circuit type HEF 40468 data for which can be found in the above Philips Data Handbook between pages 285 and 298, the pin numbers and designations used in Figure 3 corresponding with those used in the published data. Monostable M1 output at pin 6 is applied to pin 14 (SIGNIN) of phase comparator PC whilst monostable M2 output at pin 10 is applied to pin 3 (COMPIN). Pins 5 and 8 (INH and Vss) are connected to earth whilst pin 16 (VDD) is connected to supply rail 8 Pins 13 and 9 (PC20UT and VCOIN) are interconnected by a resistor R14 whilst the latter pin is connected through a capacitor C9 to earth, capacitor C9 and resistor R14 forming a low pass filter. The voltage controlled oscillator part of this integrated circuit is not used. The output of the comparator is taken from pin 10 (SFOUT) which is connected to earth through a load resistor R15 and directly to the base of a pnp transistor TR8. The emitter of transistor TR8 is connected through a resistor R16 to a reference voltage point on a divider comprising a zener diode D3 and a resistor R16 connected between the B supply rail and earth, resistor R17 being decoupled by a parallel capacitor C10. The collector of transistor TR8 is directly connected to the base of transistor TR4 and provides the control voltage to control the conduction of transistor TR4 to vary its resistance and hence the amplitude of drive pulse for transistor TR2 to ensure that this transistor becomes non-conducting simultaneously with transistor TR1.

Claims (4)

CLAIMS:

1. A circuit arrangement comprising first and second high-voltage power switches connected in series, control means for repeatedly cutting off each of the switches, which control means are connected to a signal source for producing a drive signal for each of the switches, the control means for each switch comprising a device having a characteristic which is used in the control of the drive signal for its associated switch, and a comparison stage for controlling the characteristic of at least one of the devices in order to ensure that the high-voltage power switches are automatically cut-off substantially simultaneously, characterised in that said arrangement additionally comprises means for producing a pulse for each respective switch when said switches are cut-off, means for applying the pulses so produced to said comparison stage in which the phase relationship between the pulses for the first and second switches are compared to produce the control for the characteristic of the said one device.

2. An arrangement as claimed in Claim 1 in which said first and second switches comprise respective first and second bipolar transistors, characterised in that said means for producing a pulse for each respective switch at cut-off comprises first and second sensors respectively coupled to the base of said first and second transistors for sensing the change of base current in each transistor at cut-off, said first and second sensors being connected to respective first and second pulse generators each of which produces a discrete pulse when the transistor with which it is associated is cut-off.

3. An arrangement as claimed in CLaim 2, characterised in which each pulse generator is a gated monostable multivibrator whose gating signal is derived from said signal source.

4. A circuit arrangement comprising first and second high voltage power switches connected in series substantially as herein described with reference to the accompanying drawings.