GB2198896A - Circuit arrangement with a high voltage switch - Google Patents

Abstract

A high voltage transistor (TR1) forms part of a line deflection circuit comprising a diode (D), a retrace capacitor (CR), a trace capacitor (CT) and a deflection coil (Ly) connected as shown. A switching signal for the base of transistor (TR1) is derived from a line frequency signal source (LO) via a driver stage (DR), a control device (DC) and a sensor (S). The sensor (S) senses the base current of transistor (TR1) and at switch-off a pulse is produced which is used to trigger a gated monostable multivibration (M) to its unstable stage, gating pulses for the monostable (M) being obtained from the signal source (LO). The output of the monostable (M) is applied to a first input of a phase comparator (PC) a second input of which receives pulses from the signal source (LO) delayed by a delay stage (DY). The output of the phase comparator (PC) is applied to the control input (C) of the control device (DC) to control a characteristic (e.g. time or amplitude) of the drive signal. In this way the switching of the transistor (TR1) is locked to the signal source (LO). <IMAGE>

Description

DESCRIPTION: "CIRCUIT ARANGEMENT WITH HIGH VOLTAGE SWITCH" The invention provides a circuit arrangement comprising a high-voltage power switch control means for repeatedly cutting off the switch, which control means is connected to a signal source for producing a drive signal for said switch, the control means comprising a device having a characteristic which is used in the control of the said drive signal, and a comparison stage for controlling the characteristic of the said device.

A circuit arrangement of the above type is described in Published European Patent Application No. 0 110 461 Al. The arrangements described in that published application are concerned with the control of two serially connected switches where the voltage at the junction of the two switches is sensed and compared with a reference voltage, the resulting comparison being used to control the characteristic of one or each device which in this case are formed by delay devices whose characteristic is their delay period. The nature of the operation of the arrangement is to ensure that the two switches are simultaneously rendered non-conducting.

No account is taken of the relationship between the signal source and the switching of the switches which could lead to phase changes with time.

It is an object of the present invention to provide a circuit arrangement of the type described in the opening paragraph which can be used to overcome the problem of phase change.

The invention provides a circuit arrangement comprising a high-voltage power switch control means for repeatedly cutting off the switch, which control means is connected to a signal source for producing a drive signal for said switch, the control means comprising a device having a characteristic which is used in the control of the said drive signal, and a comparison stage for controlling the characteristic of the said device, characterised in that said arrangement additionally comprises means for producing a pulse when said switch is cut-off, means for applying the pulses so produced to a first input of said comparison stage, means for applying pulses derived from said signal source to a second input of said comparison stage in which the phase relationship between the pulses for the switch and those from the signal source are compared to produce the control for the characteristic of the said device.

The above arrangement has the advantage that the cutting off of the switch is locked to the signal source in a relatively simple manner to overcome phase changes.

The switch may be a bipolar transistor, whilst the means for producing a pulse at cut-off may comprise a sensor coupled to the base of the transistor for sensing the change of base current at cut-off, the sensor being connected to a pulse generator which produces a discrete pulse when the transistor is cut-off.

Advantageously, the sensor may be in the form of a current transformer whilst the pulse generator may be a gated monostable multivibrator whose gating signal is derived from the signal source.

The pulses from said signal source are applied by way of a delay stage may to the second input of said comparison stage and the delay stage provides a delay period which can be varied. This has a particular advantage which will become apparent.

The device maybe a delay device whose delay period is controlled by said comparison stage for controlling the time at which the transistor is rendered non-conducting.

Alternatively, the device may control the amplitude of the drive current applied to the base of the transistor for controlling its charge storage time and in a particular case may comprise a capacitor and a parallel resistive path, comprising a transistor whose conductivity is controlled from said comparison stage. When using an amplitude control device the arrangement may additionally comprises means for sensing the power in the high voltage transistor, means for sensing when this power is at or near a minimum and for producing an output dependent on the relationship between the power and the said minimum which output is applied to the control input of variable delay stage for controlling the delay period. In this way the switching transistor may be operated under optimum drive conditions.

The- above and other features of the invention will now be described, by way of example, with reference to the accompanying drawings, in which: Figure 1 is a diagram, partly in block form, of one embodiment of a circuit arrangement according to the invention, Figure 2 shows various waveforms associated with the operation of the arrangement of Figure 1, Figure 3 is a diagram of one of the blocks of Figure 1, Figure 4 shows various waveforms associated with the operation of the arrangement of Figure 1 when using the block shown in Figure 3, and Figure 5 is a modification of the embodiment shown in Figure 1, Figure 1 is a diagram, partly in block schematic form, of a line deflection circuit having a line output stage for energising a line deflection coil Ly.The line output stage comprises a high voltage npn bipolar power switching transistor TR1 whose collector is connected to a voltage supply B+ through an inductor L whilst its emitter is connected to earth. The inductor L may be the primary of a transformer the secondary windings of which supply respectively the eht supply for the final anode of a display tube associated with the deflection circuit and the low voltage supply or supplies for other parts of the circuit. A diode D and a retrace capacitor CR are each connected in parallel with the transistor TR1 although the diode may be omitted if the transistor TR1 is capable of conducting in the reverse direction. A trace capacitor CT and the deflection coil Ly are serially connected between the collector of transistor TR1 and earth.

The line output stage operates in known manner with the voltage stored in trace capacitor CT producing the required sawtooth current through deflection coil Ly which initially flows through the diode D for a first part of a trace period and subsequently through transistor TR1 for a second part of the trace period. The retrace period is initiated at the instant when transistor TR1 becomes non-conducting, which transistor has been previously rendered conducting prior to or at the commencement of the second part of the trace period by positive going drive pulses applied to its base.

During the retrace period the inductance and capacitance in the line output stage resonate to produce a half sine wave flyback pulse which is followed by the start of a further trace period. The time at which the flyback pulse commences depends on the charge storage time of transistor TRI as will be described below. With displays, such as those for data graphics with a high line frequency e.g.

64 KHz, it is desirable for the flyback pulse to commence as soon as possible after the removal of the drive pulse from the base of transistor TR1. Although the transistor normally selected for such a line output stage is chosen to have a short charge storage time (of the order of 2 to 3 microseconds) the storage time for a particular transistor may vary with time for various reasons which will produce a phase movement with respect to its drive which is visible on the display screen in the absence of a complicated phase locked loop. This is overcome in the manner to be described.

A line frequency signal source LO produces pulses at line frequency which pulses are applied from its output to the input of a driver stage DR. The drive pulse output of driver stage DR is applied to the input of a drive pulse control device DC in which a characteristic of the drive pulse can be varied depending upon a signal applied to its control input C, the resulting drive pulse from the device DC being applied to the base of transistor TR1 by way of a sensor S. The sensor S senses the current at the base of transistor TR1 and when this transistor becomes non-conducting there is a drop in this current which is sensed by the sensor S and applied to a pulse generator M, in the form of a gated monostable multivibrator, to trigger it into its non-stable state. In addition to the input from the sensor S the monostable M receives at a further input a gating pulse from the output of signal source LO to ensure that the monostable is not triggered by other pulses during the remaining part of the line period. The resulting pulse output from the monostable M is applied to a first input of phase comparator PC. The output of the signal source LO is also applied to a delay stage DY where it is delayed by a finite period which can correspond to the nominal charge storage time for the transistor TRI as given in the data for such a transistor. Alternatively delay stage DY may be adjustable and preset to produce a delay corresponding to the charge storage time of the transistor for TR1 actually in use.The delayed output from the delay stage DY is applied to the second input of the phase comparator PC where the phase of the two inputs are compared and the resulting output applied to the control input C of the control device DC. The manner of operation will be described with reference to Figure 2.

Figure 2 shows various idealised waveforms associated with the line deflection circuit of Figure 1 when the device DC is a variable delay device and the characteristic of the drive pulse in its relative time. Figure 2A shows the output of the signal source LO used for driving the transistor TR1 and also for gating the monostable M. The base current for transistor TR1 is shown in Figure 2B which starts to reduce in magnitude at times tl, t10 on receipt of the negative going drive pulse which is delayed by the delay device DC and inverted by driver stage DR with respect to the pulse shown in Figure 2A.The charge carriers in transistor TR1 arethen removed with the base current reversing in polarity until times t2, t20 when the transistor comes out of saturation and the transistor is very rapidly cut-off to initiate the flyback period, it being assumed that the charge storage time for transistor TRlcorresponds to the above nominal. At times t3, t30 during the following scan period transistor TR1 becomes forward biased when a positive pulse is applied to the base of this transistor and derived from the signal source pulse in Figure 2A. This cycle is then repeated. Figure 2C shows the voltage induced by the sensor S, a sharp rise or fall in this voltage being produced with the changes in transistor TR1 base current.Monostable M is triggered by a positive going edge in the presence of a gating pulse (Figure 2A), this condition occurring at times t2, t20 and the pulses produced at the output of monostable M are shown in Figure 2D, these pulses being limited in duration by the negative going edge of the gating pulses. The line pulses from the signal source LO delayed by the delay stage DY are shown in Figure 2E and from a comparison of Figures ZD and 2E it will be seen that the leading edge of these pulses are coincident and the output of phase comparator PC is such that it does not change the delay period of delay device DC.

The base current for transistor TR is shown in Figure 2F where there is a change in phase such that it starts to reduce at the later times of t11, t101. Figure 2G shows the voltage induced by the sensor S and Figure 2H the resulting pulses produced by monostable M which pulses are of shorter duration than that in Figure 2D. The relative phase of the pulses in Figures 2E and 2H are compared in the phase comparator PC and the resulting control signal is used to reduce the delay period produced by delay device DC such that the negative going pulses of the drive signal are again applied to the base of transistor TR at times t1, t10 with the result that the initial phase relationship is restored as shown in broken line portions in Figure 2F.

In the description of the arrangement of Figure 1 the drive stage DR is placed before the device DC. It will be appreciated that in such a case it makes no difference to the operation if the delay device precedes the driver stage DR.

As an alternative to the device DC being a controlled variable delay device the device DC may be one in which the characteristic controlled is the amplitude of the forward base current. In such a case the amplitude control device DC may take the form shown in Figure 3 and which comprises a capacitor C1 connected in parallel with the series arrangement of a resistor R and an npn transistor TR2, the base of transistor TR2 forming the control input C for this device. The drive current applied to the base of a line output transistor TR1 has an effect on the quantity of charge carriers in the transistor and when the drive current is in excess of that required to cause the transistor to just saturate the transistor contains an excess of charge carriers and the storage time required to remove these charge carriers at transistor cut-off is increased.

In the case of high voltage bipolar switching transistors it is normal for the drive current to be greater than that required for a nominal transistor to be just saturated in order to cater for the spread in characteristics found with transistors of the same type.

Figure 4 show various waveforms associated with the line deflection circuit of Figure 1 using the amplitude control device of Figure 3, the waveforms in Figures 4A to 4H corresponding to the waveforms in Figures 2A to 2H. As there is no intended delay in the path between the signal source LO and the base of transistor TR1 turn off is commenced coincident with the change in the signal source pulse (Figure 4A). It is assumed initially that the amplitude of the drive current from device DC is such that the charge storage time for transistor TR corresponds to the above nominal. As a result, the operation is the same as that described above and the waveforms in Figure 4A to 4E are identical to those in Figures 2A to 2E save for the above mentioned delay.

Figure 4F shows the situation where there is a change in phase such that the base current for transistor TR1 starts to reduce at the later time of t11, t10' with the result that the voltage induced by the sensor S is produced later as shown in Figure 4G and the pulses from the monostable M are shorter as shown in Figure 4H, the full line waveform in Figure 4F and the waveforms in Figure 4G and 4H being identical to the corresponding waveforms in Figures 2F, 2G and 2H save again for the delay. As before the relative phase of the pulses in Figures 4E and 4H are compared in the phase comparator PC and the resulting control signal used to control the device DC.

In this case the amplitude of the applied forward drive pulse is reduced to reduce the charge stored in the transistor TR1 and so reduce its charge storage time. This is shown in broken line form in Figure 4F where it will be seen that whilst the charge carriers in transistor TR1 start to leak away at ti', tlO' the base current reverses its polarity at t2, t20 due to the reduced stored charge and the required phase relationship is restored.

Figure 5 is a diagram, partly in block schematic form, of a modificiation of the line deflection circuit shown in Figure 1, corresponding references indicating like components in the two figures. Figure 5 differs from Figure 1 in that it includes a power sensor PS for determining the relative power in the transistor TR1.

This power sensor PS is shown as a broken line box surrounding the transistor and may in one form comprise a device in thermal contact with the transistor to measure its temperature which will increase with an increase of power in the transistor. The output of the power sensor PS is applied to the input of a power minimum detector PM which looks for the minimum power in transistor TR1. The output of the power minimum detector PM is connected to a control input C of the delay stage DY which in this case is a device which can produce a delay period which is variable under the control of a control signal present at its control input C. In addition the device DC is a device which controls the amplitude of the forward base current for transistor TR1 and may take the form shown in Figure 3.

The operation of the circuit of Figure 5 is identical to that as described in relation to Figure 4 with the addition that a signal corresponding to the power in transistor TR1 produced by the power sensor PS is applied to the input of the power minimum detector PM.

This detector looks for a minimum power in the transistor TR1 and produces an output which is applied to the control input C of the delay stage DY to change its delay period if the above power is not at a minimum. As this delay period is changed so is the time at which the pulses in Figure 4E appear as a result of which the phase comparator PC causes a change in the amplitude of the forward drive current applied to the base of transistor TR1 and hence the charge storage time of this transistor. This continues until the optimum power in transistor TR1 is reached at which time the delay provided by delay stage DY is substantially equal to the charge storage time required for minimum power dissipation.

Although in the description of Figure 5 the power sensor PS is described as being a temperature sensor it could instead sense various voltage(s) and/or current(s) at electrodes of transistor TR1 to allow the power in that transistor to be detected. As an alternative the total supply current to transistor TR1 stage may be sensed to provide an indication of the power and one way that this may be achieved is the inclusion of a resistor of small value between the emitter of transistor TR1 and earth with a capacitor of large value to convey the components at line frequency in parallel with the resistor. In such a case the voltage across the resistor represents the power which voltage is applied to the power minimum detector PM which operates as a voltage minimum detector. Also the sensor S and monostable M producing the pulse when transistor TR1 is rendered non-conducting in Figures 1 and 5 may be replaced by a connection from a winding on a transformer forming the inductor L in the collector circuit of transistor TR1 which provides flyback pulses.

Claims (10)

CLAIMS:

1. A circuit arrangement comprising a high-voltage power switch, control means for repeatedly cutting off the switch, which control means is connected to a signal source for producing a drive signal for said switch, the control means comprising a device having a characteristic which is used in the control of the said drive signal, and a comparison stage for controlling the characteristic of the said device, characterised in that said arrangement additionally comprises means for producing a pulse when said switch is cut-off, means for applying the pulses so produced to a first input of said comparison stage, means for applying pulses derived from said signal source to a second input of said comparison stage in which the phase relationship between the pulses for the switch and those from the signal source are compared to produce the control for the characteristic of the said device.

2. An arrangement as claimed in Claim 1 in which the switch is a bipolar transistor, characterised in that said means for producing a pulse at cut-off comprises a sensor coupled to the base of said transistor for sensing the change of base current at cut-off, the sensor being connected to a pulse generator which produces a discrete pulse when the transistor is cut-off.

3. An arrangement as claimed in Claim 2, characterised in which the pulse generator is a gated monostable multivibrator whose gating signal is derived from said signal source.

4. An arrangement as claimed Claim 1, 2 or 3, characterised in that the pulses from said signal source are applied by way of a delay stage to the second input of said comparison stage.

5. An arrangement as claimed in Claim 4, characterised in that said delay stage provides a delay period which can be varied.

6. An arrangement as claimed in any of the preceding claims, characterised in that said device is a delay device whose delay period is controlled by said comparison stage for controlling the time at which said transistor is rendered non-conducting.

7. An arrangement as claimed in any of the preceding Claims 2 or 3 or 4 or 5 when dependent on Claims 2 or 3, characterised in that said device controls the amplitude of the drive current applied to the base of said transistor for controlling its charge storage time.

8. An arrangement as claimed in Claim 7, characterised in that said amplitude control device comprises a capacitor and a parallel resistive path comprising a transistor whose conductivity is controlled from said comparison stage.

9. An arrangement as claimed in Claim 7 or 8 when dependent on Claim 5, characterised in that it additionally comprises means for sensing the power in said high voltage transistor, means for sensing when this power is at or near a minimum and for producing an output dependent on the relationship between said power and said minimum which output is applied to the control input of said variable delay stage for controlling its delay period.

10. A circuit arrangement substantially as herein described with reference to the accompanying drawings.