GB2198300A - Voltage-to-digital conversion - Google Patents

Abstract

The power consumed by a load (1) supplied from a pair of a.c. supply terminals (2,3) is measured by repeatedly and cyclically connecting respective ends of a voltage sensing resistance (5) and respective ends (11,12) of a current sensing resistance (4) to the input of an analogue-to-digital converter (15) via a multiplexer (13). A microcomputer (7) subtracts the outputs of the converter (15) corresponding to the potentials on the ends of the resistance 5 from each other, as it does those corresponding to the potentials on the points 11 and 12, multiplies together each resulting pair of differences, and accumulates the results. In order to maintain those digital output words of the converter (15) which correspond to the voltage on one end (9) of the sensing resistance (5) in the middle of the converter output range, the microcomputer (7) generates the single most significant bits of these words on one of its outputs (75). These bits are fed back to the converter input via an integrator (95,96,97) to form a negative feedback loop. The resulting ramping of the converter input voltage also results in quantization errors introduced by the converter averaging out with time. <IMAGE>

Description

DESCRIPTION VOLTAGE-TO-DIGITAL CONVERSION This invention relates to a method of generating a succession of multi-bit digital numbers representative of respective successive values of an alternating voltage present between first and second points, in which method said first and second points are repeatedly coupled one after the other to the input of'an analogue-to-digital converter and each said digital number is generated by subtracting a digital output signal of the converter produced in response to the coupling of the first point to its input and a digital output signal of the converter produced in response to the coupling of the second point to its input one from the other. The invention also relates to a circuit arrangement for carrying out such a method.

The performances of present-day analogue-to-digital converters tend to be somewhat limited in respect of their resolution capabilities, i.e. in respect of the number of bits which make up each of their output signals, and it is highly desirable to obtain as high a resolution as possible from the number of bits available. To this end the maximum and minimum values of an input signal to be converted should ideally result in a converter producing the maximum and minimum values respectively of its output signal, so that the complete dynamic range capability of the input signal is accommodated while no part of the dynamic range capability of the converter is wasted.

However, such an ideal situation is difficult to achieve in practice due to offsets which may be produced in a path for the input signal to the converter and/or in the converter itself, which offsets may vary with time causing the input signal dynamic range to shift with respect to the corresponding dynamic range of the converter output signal. The result is that the dynamic range of the converter output signal has to be made wider than the corresponding dynamic range of the input signal in order that the dynamic range of the input signal can be accommodated even in the presence of the offsets. It is an object of the invention to mitigate this problem when the input signal is in the form of an alternating voltage present between first and second points.

The invention provides a method of generating a succession of multi-bit digital numbers representative of respective successive values of an alternating voltage present between first and second points, in which method said first and second points are repeatedly coupled one after the other to the input of an analogue-to-digital converter and each said digital number is generated by subtracting a digital output signal of the converter produced in response to the coupling of the first point to its input and a digital output signal of the converter produced in response to the coupling of the second point to its input one from the other, characterised in that the single most significant bits of digital output signals of the converter produced in response to the coupling of the first point to its input are integrated and the result is coupled as a negative feedback signal to the input of the converter.

It has now been recognised that coupling an integrated version of the single most significant bits of those digital output signals of the converter which are produced in response to the coupling of the first point to the converter input as a negative feedback signal to the converter input can result in said digital output signals being maintained substantially in the centre of the possible range of the converter output signals, whatever offsets occur in a path for the input signal to the converter and/or in the converter itself.Thus, provided that the maximum excursions of the voltage on the second point are symmetrical about the voltage on the first point, the converter gain can be adjusted so that these excursions give rise to substantially the extreme ends of the range of possible values of the converter output signal without fear that changing offsets will subsequently result in clipping of the input signal as it is represented by the converter output signal.The feedback signal in effect itself creates an offset which ramps up and down at a rate determined by the time constant of the integration process and the average value of which is such as to substantially nullify the effect of any other offset present. (The time constant of the integration process should obviously be chosen sufficiently long to ensure that the contribution of the created offset to any two digital output signals of the converter which are subtracted one from the other is substantially the same).In some contexts the presence of the ramping offset may also be an advantage for another reason, in that it may result in identical values of the voltages on the two points occurring on different occasions giving rise to different values of the converter output signal, so that errors due to quantizing of these values by the converter will average out with time.

If desired, a succession of further multi-bit digital numbers representative of respective successive values of an alternating voltage present between said first point and a third point may also be generated, said first and third points in such a case being repeatedly coupled one after the other to the input of the converter and each said further digital number being generated by subtracting a digital output signal of the converter produced in response to the coupling of the first point to its input and a digital output signal of the converter produced in response to the coupling of the third point to its input one from the other.If this is done then the method may be used, for example, to measure the power being consumed by a load if the first and second points are at respective ends of a first resistor which is connected in series with a second resistor across a pair of a.c. supply conductors, if the first and third points are at respective ends of a second resistor connected in series with a said supply conductor, if number pairs comprising a multi-bit digital number specified in the preceding paragraph and a said further multi-bit digital number are generated in succession, and if the components of each said pair are multiplied together and the results accumulated.

The invention also provides apparatus for generating a succession of multi-bit digital numbers representative of respective successive values of an alternating voltage present between first and second points, comprising an analogue-to-digital converter, a multiplexer having a first input to which said first point is coupled, a second input to which said second point is coupled, and an output coupled to the analogue signal input of the converter, and a programmed digital data processing system to an input port of which is coupled the digital signal output of said converter and first, second and third outputs of which are coupled respectively to the input of the converter via an integrator circuit to form a negative feedback path, to a convert control input of the converter and to a control input of the multiplexer, said processing system being programmed to control the multiplexer to repeatedly couple said first input to the multiplexer output and said second input to the multiplexer output one after the other, to apply a convert control signal to the converter each time said first input is coupled to the multiplexer output and each time said second input is coupled to the multiplexer output, to generate each said digital number by subtracting a digital output signal of the converter produced in response to the application of a said convert control signal thereto when said first input is coupled to the multiplexer output and a digital output signal of the converter produced in response to the application of a said convert control signal thereto when said second input is coupled to the multiplexer output one from the other, and to apply the single most significant bits of digital output signals of the converter produced in response to the application of said convert control signals to said convert control input when said first inut is coupled to the multiplexer output to its first output.

An embodiment of the invention will now be described, by way of example, with reference to the accompanying diagrammatic drawings in which Figure 1 is a diagram of a circuit arrangement for measuring the a.c. power consumed by a load, Figure 2 is a flow chart showing the relevant steps carried out in the arrangement of Figure 1, Figure 3 shows part of the chart of Figure 2 in more detail, and Figure 4 shows another part of the chart of Figure 2 in more detail.

Figure 1 shows a circuit arrangement for measuring the a.c.

power consumed by a load 1 which is connected across a.c. mains supply terminals 2 and 3 via a low-ohmic series resistor 4. The measurement is achieved by alternately measuring the voltage across resistor 4, which voltage is a measure of the instantaneous current consumed by load 1, and the voltage across a resistor 5, which voltage is a measure of the instantaneous voltage across load 1, resistor 5 constituting the lower portion of a potential divider connected across load 1, the upper portion of the potential divider being formed by a resistor 6. The components of each pair of successive voltage and current measurements are multipled together to give the instantaneous power, and these results are accumulated. Periodically, for example every five seconds, the accumulated results are divided by the number of results to give the average power.Said number may suitably be, for example, in the order of 5000 when the frequency of the supply fed to terminals 2 and 3 is 50Hz.

The measurement operations are carried out under the control of a programmed digital data processing system in the form of a suitably programmed microcomputer 7 to an input port 8 of which the upper end 9- and the lower end 10 of resistor 5 and the upper end 11 and the lower end 12 of resistor 4 are successively and cyclically coupled via a multiplexer 13, an amplifier 14, an analogue-to-digital converter 15, and a shift register 16A,16B.

To this end a pair of outputs 17 and 18 of microcomputer 7 are connected to select signal inputs 19 and 20 respectively of multiplexer 13 and a further output 21 of microcomputer 7 is connected to an input-enable signal input 22 of multiplexer 13.

The points 9,10,11 and 12 are connected to inputs 23,24,25 and 26 respectively of multiplexer 13, the connection to input 24 being via a resistor 27 which serves to ensure that the external impedance seen by input 24 is substantially equal to the external impedance seen by input 23. The output 28 of multiplexer 13 is connected to the non-inverting input of amplifier 14 the output of which is connected to the analogue signal input 29 of converter 15 via a series resistor 30. The output of amplifier 14 is also connected to its inverting input via a variable resistor 31, the inverting input being connected in turn to terminal 3 (which serves as the arrangement ground although it may in fact be connected to the live line of the supply) via a resistor 32. The gain of amplifier 14 may thus be varied in known manner by varying resistor 31.

Converter 15 is of a kind which generates serially on its output 33 a digital word representative of the analogue voltage currently on its input 29 in response to the application of a logic '1 level to a convert-control input 34 thereof, clock pulses being concurrently produced on a further output 35.

Output 33 is connected to the serial data input 36 of shift register 16A the serial data output 37 of which is connected to the serial data input 38 of shift register 16B. Clock signal output 35 of converter 15 is coupled to the clock signal inputs 39 and 40 of shift registers 16A and 16B respectively via an inverter in the form of a Schmitt NAND gate 41 having parallelled inputs. Convert control input 34 of converter 15 is fed from a further output 42 of computer 7 via a differentiating circuit comprising a capacitor 43 and a resistor 44 and an inverter in the form of a Schmitt NAND gate 45. The relevant input of NAND gate 45 is connected to a positive supply voltage (logic "1") via a clamping diode 46. The other input of NAND gate 45 is connected to the positive supply directly.Resistor 44 is connected to the positive supply, as is a pull-up resistor 47 connected to output 42 of microcomputer 7. A further input 48 of microcomputer 7 is connected to the collector of a transistor 49, which collector is also connected to the positive supply voltage via a load resistor 50. The emitter of transistor 49 is connected to ground, and its base is connected to ground via a clamping diode 51 and to an input terminal 52 via a series resistor 53. Terminal 52 is fed with a low-level version of the a.c. voltage across terminals 2 and 3 via a transformer (not shown). The parallel data outputs 64A and 64B are connected to the input port 8 of microcomputer 7. Further outputs 65 and 66 of microcomputer 7 are connected to output-enable control inputs 67 and 68 of shift registers 16A and 16B respectively.

Microcomputer 7 has an output 69 for serial data, which output is connected to an output terminal 70, and also a further output 75 the significance of which will become apparent below. The part of the arrangement of Figure 1 so far described operates as follows, microcomputer 7 containing inter alia storage locations F1 for a flag, ZCC for the number of zero-crossings occurring in the a.c. voltage across terminals 2 and 3, i.e. on terminal 52, AP for the accumulated measurements of instantaneous power being consumed by the load 1, and AS for the number of measurements currently accumulated in location AP. Microcomputer 7 is programmed to perform the operations shown in the flow chart of Figure 2, in which the various blocks have the following significances.

54 - Initialize. Set flag F1 to logic "1". Clear storage locations ZCC, AP and AS. Set multiplexer 13 by means of an appropriate signal on outputs 17 and 18 to couple its input 24 to its output 28. Enable the inputs of multiplexer 13 by means of a signal on output 21.

55 - Is input 48 logic "1"? 56 - Is input 48 logic "0"? 57 - Measure the voltages on points 9,10,11 and 12, calculate therefrom the instantaneous power consumed by load 1, add this to contents of location AP, and increment contents of location AS. (See Figure 3).

58 - Has a zero-crossing occurred in the a.c. voltage across terminals 2 and 3, i.e. in the voltage on terminal 52? (See Figure 4).

59 - Increment contents of location ZCC.

60 - Have the contents of location ZCC reached 498? 61 - Divide contents of location AP by the contents of location AS and output result to terminal 70. Clear locations AP, AS and ZCC.

62 - Is input 48 logic 1? 63 - Is input 48 logic 0? After initialization microcomputer 7 tests input 48 to determine when a positive half-cycle in the supply starts (steps 55 and 56). When this occurs the voltages on points 9,10,11,12 are then successively and cyclically sampled in step 57, and the corresponding instantaneous power consumed by load 1 is calculated from each set of four samples and accumulated in location AP. This process carries on until it is determined in step 58 that another zero crossing has occurred in the a.c.

supply voltage, at which point the contents of zero-crossing counter location ZCC is incremented (step 59) and it is tested (step 60) whether 498 such zero-crossings have occurred. If not the program returns to block 57. Otherwise (this will occur after approximately 4.98 seconds with a 50Hz supply) the accumulated power samples in location AP are divided by the number of such samples in location AS and the result, being a measure of the average power over the past 4.98 seconds with a 50Hz supply, is outputted to terminal 70 (step 61) and the contents of locations AP,AS and ZCC are cleared. The start of the next positive half-cycle of the supply is then awaited in steps 62 and 63, after which the program returns to block 57.

Figure 3 shows the block 57 of Figure 2 (which may take, for example, approximately 10 millisecs. to perform) in more detail.

In Figure 3 the various blocks have the following significances.

71 - Activate A-D converter 15 and wait until its output signal is completely stored in shift register 16A,16B. Deactivate A-D converter 15.

72 - Disable inputs of multiplexer 13. Set multiplexer 13 to couple its input 23 to its output 28. Enable inputs of multiplexer 13.

73 - Input conents of shift register 16A,16B to microcomputer and store.

74 - Write most significant bit of inputted contents of shift register 16A,16B to output 76.

76 - As 71.

77 - Disable inputs of multiplexer 13. Set multiplexer 13 to couple its input 26 to its output 28. Enable inputs of multiplexer 13.

78 - As 73.

79 - Subtract contents inputted in step 73 from contents inputted in step 78 and store result.

80 - As 71.

81 - Disable inputs of multiplexer 13. Set multiplexer 13 to couple its input 25 to its output 28. Enable inputs of multiplexer 13.

82 - As 73.

83 - As 71.

84 - Disable inputs of multiplexer 13. Set multiplexer 13 to couple its input 24 to its output 28. Enable inputs of multiplexer 13.

85 - As 73.

86 - Subtract contents inputted in step 82 from contents inputted in step 85 and store result.

87 - Multiply result stored in step 79 by result stored in step 86 and add result of multiplication to contents of location AP.

88 - Increment contents of location AS.

The activation and de-activation of converter 15 in steps 71,76,80 and 83 are achieved by the generation of logic "0" and logic "1" respectively on output 42. The disabling and enabling of the inputs of multiplexer 13 in steps 72,77,81 and 84 are achieved by the generation of logic 1" and logic O respectively on output 21. The setting of multiplexer 13 to couple its input 23,24,25 or 26 to its output 28 is achieved by the generation of an appropriate bit-pair on outputs 17 and 18.

The inputting of the contents of shift-register 16A,16B in steps 73,78,82 and 85 is achieved by first generating logic 1 on output 65 and then logic 1 on output 66. (The two shift registers 16A and 16B are provided in the present example because in the particular construction described each input word from converter 15 is in fact 14-bits long whereas the data input 8 of microcomputer 7 is only eight bits wide. The registers 16A and 16B are in fact each 8-bits long in the present example). It will be evident that the result of each step 79 is a measure of the instantaneous voltage between points 9 and 10, i.e. of the instantaneous voltage across terminals 2 and 3.Similarly the result of each step 86 is a measure of the instantaneous voltage between points 11 and 12 (and between points 11 and 10, point 10 being connected to point 12), i.e. of the instantaneous current in load 1. Thus the result of each multiplication in step 87 is a measure of the instantaneous power consumed by load 1.

Step 58 of Figure 2 is shown in more detail in Figure 4, in which the various blocks have the following significances.

90 - Is input 90 logic '0'? 91 - Is flag F1 logic 1'? 92 - Is flag F1 logic "0"? 93 - Set flag F1 is logic '.0..

94 - Set flag F1 is logic "1".

Flag Fl is used to record whether, the previous time test 58 was carried out, a positive half-cycle (Fl=l) or a negative half-cycle (F1=0) was in the process of being presented to input terminal 52 of Figure 1. If the result of test 90 is positive then a positive half-cycle is currently being presented to terminal 52 and the program proceeds to step 92. If the result of step 92 is positive then a negative half-cycle was previously being presented to terminal 52, i.e. a zero-crossing has occurred. In such a case F1 is set to "1" and the program proceeds to the "yes" (Y) output of test 58. Otherwise a positive half-cycle was also being presented previously to terminal 52, i.e. no zero-crossing has occurred, in which case the program proceeds to the "no" (N) output of test 58.A similar process occurs if the result of test 90 is negative (N), signifying that a negative half-cycle is currently being presented to terminal 52. Flag F1 is then tested to determine whether or not a positive half-cycle was previously being presented to terminal 58, the program proceeding to the "yes" or "no" output of test 58 in accordance with the result and flag F1 being reset if appropriate.

As mentioned above (step 74 of Figure 3) microcomputer 7 produces in succession on its output 75 the most significant bit of each digitial word generated by converter 15 which is a measure of the voltage on point 10 of Figure 1. Output 75 is coupled to the analogue input 29 of converter 15 via an integrator circuit comprising an operational amplifier 95 having a capacitor 96 connected between its output and its inverting input. Output 75 is connected to the inverting input via a series resistor 97 and the output of amplifier 95 is connected to input 29 via a series resistor 98. The potential on input 29 is thus a combination of the voltages on the outputs of amplifiers 14 and 95.The non-inverting input of amplifier 95 is connected to the junction of two resistors 99 and 100 connected in series between the positive supply voltage and ground, a capacitor 101 being connected across resistor 100.

If, for example, the most significant bit of each digital word generated by converter 15 which is a measure of the voltage on point 10 is consistently "1", i.e. each such word lies in the upper half of the output range of converter 15, the output voltage of amplifier 95 will become increasingly more negative, pulling input 29 of converter 15 with it and hence reducing the values of the said words so that their most significant bits eventually cease to be "1", i.e. they begin to lie in the lower half of the output range of converter 15. When this happens, however, the output of amplifier 95 ceases to change in a negative direction and starts to change in a positive direction, pulling the input voltage of converter 15 with it and hence increasing the values of the said words once again.Thus a state is reached in which the values of successive said words all lie substantially in the centre of the output range of converter 15, as required.

In fact in the "equilibrium" state the output voltage of amplifier 95 ramps up and down slightly at a rate determined by the values of resistor 97 and capacitor 96. These values should be chosen so that the output voltage of amplifier 95 changes to only a negligible extent between each step 71 and the next step 76 of Figure 3, and between each step 80 and the next step 83 of Figure 3. As mentioned previously, this ramping can result in an improvement in the accuracy of the power measurements outputted to terminal 70, because it can result in an averaging over time of the quantization errors inevitably introduced by converter 15.

It will be evident that the order in which points 9 and 10 and/or points 11 and 12 of Figure 1 are coupled to the multiplexer output 28 may be reversed, if desired, possibly periodically. Moreover, the specific coupling of point 10 or point 12 to the multiplexer output may even be omitted completely if the resistance of the relevant conductors is sufficiently small that any voltage difference present between points 10 and 12 can be neglected.

In a practical construction of the arrangement of Figure 1 various components had the following type numbers or values.

Multiplexer 13 HEF4051 Converter 15 TDA1534 Shift registers 16A,16B HEF4094 Microcomputer 7 MAB8048 Schmitt NAND gates 41,45 1/4 x HEF4093 Amplifiers 14,95 1/2 x TL082 Resistor 30 1K5 Resistor 98 4K7 Resistor 97 180K Capacitor 96 1 micro Farad Capacitor 43 100pF Resistor 44 3K9.

Claims (8)

CLAIM(S)

1. A method of generating a succession of multi-bit digital numbers representative of respective successive values of an alternating voltage present between first and second points, in which method said first and second points are repeatedly coupled one after the other to the input of an analogue-to-digital converter and each said digital number is generated by subtracting a digital output signal of the converter produced in response to the coupling of the first point to its input and a digital output signal of the converter produced in response to the coupling of the second point to its input one from the other, characterised in that the single most significant bits of digital output signals of the converter produced in response to the coupling of the first point to its input are integrated and the result is coupled as a negative feedback signal to the input of the converter.

2. A method as claimed in Claim 1, in which a succession of further multi-bit digital numbers representative of respective successive values of an alternating voltage present between said first point and a third point is also generated, said first and third points being repeatedly coupled one after the other to the input of the converter and each said further digital number is generated by subtracting a digital output signal of the converter produced in response to the coupling of the first point to its input and a digital output signal of the converter produced in response to the coupling of the third point to its input one from the other.

3. A method as claimed in Claim 2, wherein the first and second points are at respective ends of a first resistor which is connected in series with a second resistor across a pair of a.c.

supply conductors, wherein the first and third points are at respective ends of a second resistor connected in series with a said supply conductor, wherein number pairs comprising a multi-bit digital number specified in Claim 1 and a said further multi-bit digital number are generated in succession, and wherein the components of each said pair are multiplied together and the results accumulated.

4. Apparatus for generating a succession of multi-bit digital numbers representative of respective successive values of an alternating voltage present between first and second points, comprising an analogue-to-digital converter, a multiplexer having a first input to which said first point is coupled, a second input to which said second point is coupled, and an output coupled to the analogue signal input of the converter, and a programmed digital data processing system to an input port of which is coupled the digital signal output of said converter and first, second and third outputs of which are coupled respectively to the input of the converter via an integrator circuit to form a negative feedback path, to a convert control input of the converter and to a control input of the multiplexer, said processing system being programmed to control the multiplexer to repeatedly couple said first input to the multiplexer output and said second input to the multiplexer output one after the other, to apply a convert control signal to the converter each time said first input is coupled to the multiplexer output and each time said second input is coupled to the multiplexer output, to generate each said digital number by subtracting a digital output signal of the converter produced in response to the application of a said convert control signal thereto when said first input is coupled to the multiplexer output and a digital output signal of the converter produced in response to the application of a said convert control signal thereto when said second input is coupled to the multiplexer output one from the other, and to apply the single most significant bits of digital output signals of the converter produced in response to the application of said convert control signals to said convert control input when said first input is coupled to the multiplexer output to its first output.

5. Apparatus as claimed in Claim 4, for also generating a succession of further multi-bit digital numbers representative of respective successive values of an alternating voltage present between said first point and a third point, wherein the multiplexer has a third input to which said third point is coupled and wherein the processing system is programmed to control the multiplexer to repeatedly couple said first input to the multiplexer output and said third input to the multiplexer output one after the other, to apply a convert control signal to the converter each time said third input is coupled to the multiplexer output and to generate each said further multi-bit number by subtracting a digital output signal of the converter produced in response to the application of a said convert control signal thereto when said first input is coupled to the multiplexer output and a digital output signal of the converter produced in response to the application of a said convert control signal thereto when said third input is coupled to the multiplexer output one from the other.

6. Apparatus as claimed in Claim 5, wherein the first and second points are at respective ends of a first resistor which is connected in series with a second resistor across a pair of a.c.

supply conductors, wherein the first and third points are at respective ends of a second resistor connected in series with a said supply conductor, and wherein the processing system is programmed to generate number pairs comprising a multi-bit digital number specified in Claim 4 and a said further multi-bit digital number in succession and to multiply together the components of each pair and accumulate the results.

7. A method of generating a succession of multi-bit digital numbers representative of respective successive values of an alternating voltage present between first and second points, substantially as described herein with reference to the drawings.

8. Apparatus for generating a succession of multi-bit digital numbers representative of respective successive values of an alternating voltage present between first and second points, substantially as described herein with reference to the drawings.