GB2093292A - Apparatus and methods for analogue-to-digital conversion and for deriving in-phase and quadrature components of voltage and current in an impedance - Google Patents

Abstract

In a dual slope analogue-to- digital converter an acquisition period formed by a number of fixed intervals determined by the magnitude of the input signal is followed by a conversion period which consequently has a comparatively small variation in length. Thus a problem is overcome since the large range of conversion periods encountered in previous converters is very much reduced. During the acquisition period an integrator 52, 53, 54 integrates an input signal under the control of a comparator 55, 56 and during the conversion period the integrator integrates a reference signal under the control of a comparator 57. The fixed intervals form a geometric progression, allowing a floating point digital output and efficient automatic control of ranges when the converter is used in a component meter. A phase sensitive detector has input corrections, provided via gain- control operational amplifiers, to switch means which connects them alternately with selectable phase to an output amplifier, under control of a reference signal (Fig. 4, not shown). Two different phases, differing by 180 DEG , are used in turn for each measurement, to permit subsequent elimination of D.C. offsets by subtraction. A component meter employing the converter and the phase sensitive detector is also described. <IMAGE>

Description

SPECIFICATION Apparatus and methods for analogue-to-digital conversion and for deriving in-phase and quadrature components of voltage and current in an impedance The present invention relates to methods and apparatus for digital to analogue conversion, particularly where further calculations are to be carried out on the resulting digital signal and where the range of a measuring instrument is to be automatically selected. Thus the invention is useful for example in meters for measuring the impedances (resistive and reactive) of components, in digital voltmeters and in weighing apparatus utilising strain gauge bridges or strain sensitive components.

The present invention also relates to the derivation of in-phase and quadrature components of a signal such as the voltage across, or the current through, an unknown impedance connected to an impedance meter.

In modern known component meters the resistive and reactive elements of a component under test are calculated from a set of complex voltage and current measurements. Hence the components of various equivalent circuits may also be calculated. These calculations are carried out by a digital computer, usually in the form of a microprocessor, which is coupled to the analogue portion of the meter by an analogue to digital converter. In known component meters the converter has to operate a wide dynamic range. Clearly it is difficult to obtain high resolution over a wide dynamic range although this has been attempted in a dual slope converter, where the discharge period of an integrator is resolved by using a very high (for analogue circuits) clock frequency.

When automatic range selection is carried out in known component meters, it is usually necessary to step through some or all of the ranges until the correct range is reached. This is a time-consuming process where automatic test equipment is in operation.

According to a first aspect of the present invention there is provided an analogue to digital converter comprising integration means, switching means for applying either an analogue signal which is to be converted to a digital signal, or a reference signal of opposite polarity to the analogue signal to the integration means, first comparator means for indicating when the output signal of the integrator means reaches a predetermined first magnitude when the analogue signal is applied to the integration means, second comparator means for indicating when the output signal of the integrator means reaches a second predetermined magnitude when the reference signal is applied to the integration means.

control means for controlling the operation of the switching means to carry out conversion cycles in each of which the analogue signal is applied to the switching means for a predetermined interval or an integral number of the predetermined intervals, the control means applying the reference signal to the integration means at or after the end of one of the said intervals, when the first comparator has indicated that the output signal of the integrator means has reached the first predetermined magnitude, the control means applying the reference signal to the integration means at least until the second comparator indicates that the output signal of the integration means has reached the second predetermined magnitude, and digital means for generating for each conversion cycle a first digital signal representative of the total time for which the analogue signal is applied to the integration means, and for generating for each conversion cycle a second digital signal represe,ntative of the total time for which the reference signal is applied to the integration means.

Preferably the total duration of the interval or intervals during which the analogue signal is applied to the integration means is restricted to a set of possible durations in which the possible durations form a geometric progression.

The main advantage of apparatus according to the first aspect of the invention is that the output of the analogue to digital converter is in floating point form. The first digital signal is representative of the exponent of the value of the analogue signal and the second digital signal is representative of its mantissa. Preferably the geometric progression has a common multiplier of two and the first predetermined magnitude is half the maximum possible magnitude of the integrator means output signal and in this case the base of the floating point representation provided by the converter is 2.

Clearly signals in floating point form referred to base 2 are relatively easily manipulated in a computer especially where floating point calculations need to be carried out.

The number of predetermined intervals over which integration of the analogue signals can take place is preferably limited, for example, to eight. If the output signal of the integrator has not reached half the maximum possible value by the end of a predetermined number of intervals, the reference signal is then applied to the integrator input.

A further advantage of the converter according to the first aspect of the invention is that accuracy is improved since the second digital signal is always measured in a restricted range, for example between that corresponding to the maximum output signal of the integration means and half that signal. The second digital signal may be measured by a counter supplied with clock pulses; the counter is reset to zero before the switching means applies the reference signal to the integration means and the counter is stopped when the second comparator means indicates that the integrator output signal has reached the second predetermined magnitude. In this case another advantage is realised in that even for high resolution the clock signal applied to the counter need not have a particularly high repetition frequency.

The second predetermined magnitude is preferably zero but it may not be zero if, for example, the converter is a "triple-slope" converter. The reference signal is advantageously supplied from means which includes positive and negative reference signal sources, the appropriate source being selected in accordance with the output of the second comparator means which indicates the polarity of the integrator output signal.

A further advantage of the converter according to the first aspect of the invention is that it allows an improvement in automatic range selection where the converter forms part of an instrument such as an impedance meter.

For example, where an impedance meter comprises means for deriving analogue signals representative of the in-phase and quadrature components of voltage and current signals in an unknown component, and an analogue to digital converter according to the first aspect of the invention, the meter may also include means for automatically selecting the correct measurement range of the meter by calculating a quantity dependent on at least two of the digital values of the analogue signals provided by the meter. The calculations may be carried out in a microcomputer which forms part of the meter and can allow the meter to be switched directly to the correct range without stepping through other ranges.

Preferably the said predetermined interval is equal to the period of a power supply for the analogue to digital converter or an instrument connected to or incorporating the converter.

According to a second aspect of the present invention there is provided a method of converting analogue signals to digital signals comprising the steps of integrating an analogue signal which is to be converted to a digital signal over a predetermined interval or an integral number of the predetermined intervals until either the result of the integration exceeds a first predetermined magnitude or the number of predetermined intervals reaches a predetermined maximum, providing a digital signal representative of the number of said intervals over which the integration occurs, modifying the result of the integration by substituting a reference signal, of opposite polarity to the analogue signal, as the signal to be integrated either at the end of one of the said intervals after the first predetermined magnitude is exceeded or when the number of intervals reaches a predetermined maximum, continuing integration at least until a second predetermined magnitude is reached, and providing a second digital representative of the time for which the reference signal is integrated.

According to a third aspect of the present invention there is provided a phase sensitive detector circuit comprising first and second input terminals for the detector connected to like input terminals of first and second high gain differential amplifiers, respectively, switch means for alternately coupling the output terminals of the first and second amplifiers to an output terminal of the detector circuit, and means for controlling the frequency of operation of the switch means in accordance with a reference signal applied to a reference signal terminal of the detector circuit.

When the two input terminals are connected accross an impedance, the voltage obtained at the output terminal is, in general, periodic but has a steady unidirectional component dependent on the phase of the voltage across the impedance relative to the reference signal, that is, a phase sensitive detector (PSD) is provided.

Preferably the switch means is coupled by way of an operational amplifier to the detector output terminal and the detector output terminal is connected by means of first and second resistances to ground, the junction of the first and second resistances being connected to the inverting terminals of both the first and second differential amplifiers. The common feedback path thus provided ensures that each path from one input terminal to the output terminal has the same gain as the other path.

An advantage of this arrangement is that a PSD with gain is provided, the gain being accurately defined by the ratio of the resistances and is the same for both channels. High overall feedback is provided giving good linearity.

Phase sensitive detectors according to the third aspect of the invention find particular application in component meters.

For example, a component meter may comprise a source of excitation signals coupled to first and second terminals for the connection of an unknown impedance, the second terminal being connected to the excitation source by way of a standard resistor, the component meter also including a phase sensitive detector circuit according to the third aspect of the invention in which the first and second input terminals are connected to the terminals for connecting the unknown impedance, and third and fourth high gain differential amplifiers are provided with like input terminals connected to different ends, respectively, of the standard resistor, the other like terminals of the third and fourth amplifiers being connected to the said other like terminals of the first and second amplifiers and the output terminals of the third and fourth amplifiers also being connected to the switch means, and the switch means is constructed to carry out a cycle in which, during one interval, the output terminals of the first and second amplifiers are alternately coupled to the output terminal of the detector circuit, and during another interval the output terminals of the third and fourth amplifiers are alternately coupled to the output terminal.

The second and third differential amplifiers may be replaced by a single differential amplifier where the said second terminal is at the same potential as one end of the standard resistor.

The meter mentioned above may also comprise an analogue to digital converter according to the first aspect of the invention which is coupled to the output of the phase sensitive detector. The meter may be controlled by a microprocessor to give a measurement cycle in which the following are measured the in-phase component a of the voltage across the unknown impedance, the quadrature component b of this voltage, the in-phase component c of the current in the unknown impedance and the quadrature component d of this current. The microprocessor may be programmed to calculate from a, b, c and d various quantities such as the resistance, inductive reactance, capacitive reactance and various parameters of equivalent circuits for the unknown impedance.

Certain embodiments of the invention will now be described by way of example, with reference to the accompanying drawings in which: Figure 1 is a block circuit diagram of a component meter incorporating embodiments of the first and third aspects of the present invention, Figure 2 is a block circuit diagram of the ring counter and transversal filter of Figure 1, Figure 3 is a circuit diagram of a signal recovery circuit of a known component meter, Figure 4 is a circuit diagram of a phase sensitive detector according to the third aspect of the present invention as used in Figure 1, Figure 5 is an output versus time graph of a known dual slope converter, Figure 6a and 6b are output versus time graphs of the converter 26 of Figure 1.

Figure 7 is a block diagram of part of a converter according to the first aspect of the present invention used as the converter 26 of Figure 1, Figures 8a and 8b show a flow chart for the control of the converter of Figure 7 by the microprocessor of Figure 1, Figure 9a is a diagram giving voltage and current relationships useful for explaining the choice of ranges.

Figure 9b is a circuit diagram for use in reading Figure 9a, and Figure 10 is a flow chart showing how range selection is achieved in manual and auto modes.

A component meter incorporating the invention will first briefly be described with reference to Figure 1 and then circuits used in Figure 1 will be described in more detail with reference to other figures.

In Figure 1 an alternating current at a selected frequency is passed through an unknown component 10 and real and imaginary components of the voltage across the unknown component are derived by means of a phase sensitive detector (PSD) 1 The current through the unknown component is also passed through a selected one of standard resistors 12 to 1 5 and the real and imaginary components of a voltage proportional to the components of the current passing through the unknown component are determined by the PSD 11.

The a.c. current which is passed through -the unknown component is generated by a waveform synthesizer comprising a twisted ring counter 9, a transversal filter 1 6 which synthesizes a stepped sine wave by adding weighted voltages from the ring counter, and an analogue filter 1 7 which smooths the stepped sine wave. The frequency of operation of the bridge is selected by the operator who uses control and display circuits 1 8 to modify the program of a microprocessor 1 9 which provides control signals for a frequency selection decoder and relay driver circuit 20. The decoder 20 divides a clock signal to provide selected repetition frequencies for the ring counter 9.At the same time the circuit 20 passes signals to the analogue filter 1 7 which uses reed switches to select components in the filter 1 7 to tailor the frequency response of the filter 1 7 to the frequency selected by the operator.

Since the PSD 11 requires, as will be explained later, four reference signals in different relative phases, the ring counter 9 provides a very suitable source of such reference signals, the selection being made by a phase selector circuit 21 which receives control signals from the microprocessor 19.

Since the junction of the unknown component 10 and the standard resistors 12 to 1 5 would not be at earth potential in a simple excitation circuit, signal currents could flow through the predominantly capacitive admittances between the junction and earth in such a circuit creating an error in measured current. To overcome this problem a known technique is used in which the standard resistors are duplicated in resistors 12' to 15' and an operational amplifier 22 is connected across the resistors 12 to 1 5. The inverting input of the operational amplifier is connected to the junction between the unknown component 10 and the standard resistors 12 to 1 5 and the non-inverting input thereof is connected to ground. In this way a virtual earth is generated at the said junction.A range selection circuit 23 is also controlled by the microprocessor 1 9 and itself controls the operation of switches 24 and 24' which connect a selected pair of standard resistors. In one mode the operator can select the range or in another mode the bridge automatically selects the appropriate range.

The two pairs of real and imaginary components of the voltages obtained across the unknown component 1 0 and one of the standard resistors 12 to 1 5 are converted into digital form by means of a converter 26 in the form of a dual slope integrator which has the particularly important feature that it provides its output in mantissa and exponent form. This has the advantages already explained of allowing greater accuracy in A to D conversion to be achieved, providing a very convenient form of output for the calculations carried out at the microprocessor 1 9 and allowing the correct meter range to be selected quickly without the need to step through all ranges. The converter 26 will be described in more detail below but briefly comprises an operational amplifier 27 connected as an integrator and controlled by a control circuit 28.

A brief description of the twisted ring counter 9 and the transversal filter 1 6 is now given with reference to Figure 2. These circuits are based on the paper by A.C. Davies, "Digital Generation of Low Frequency Sine Waves," IEEE Trans. Inst., Meas. Vol. IM 18, pages 97 to 105, June 1969. The twisted ring counter comprises eight D-type flip-fiops connected with each Q output coupled to the D input of the next stage except in the first and last stages where the Q output of the last stage is connected to the D input of the first stage.A clock signal from the circuit 20 is used to clock the flip-flops 30 so that their outputs form a series of eight square waves with delays evenly distributed over 1 80a These delayed square waves (except that from the last flip-flop) are summed by the transversal filter 1 6 which comprises an operational amplifier 31 connected as a summing amplifier by means of a feedback resistor 32 and weighting resistors 33. The weights of these resistors are determined as described by Davies.

As has been mentioned the twisted ring counter 9 provides reference signals for the PSD 11. By also taking outputs from the Q terminals of the flip-flops reference signals are available at 22210 intervals throughout the complete cycle of the stepped sine wave which appears at the output of the transversal filter. Thus the Q and Q outputs of the flip-flops 30 are connected to the phase selector circuit 21 which selects the phase signal required at any particular time by means of four inputs from the microprocessor 19.

In describing the phase sensitive detector 11, reference is first made to Figure 3 where a known circuit is shown in schematic form. The designations Rs and R's correspond to the groups of standard resistors 12 to 1 5 and 12' to 15', respectively, and the designation Zu corresponds to the unknown component 10. The a.c. source S represents a synthesiserformed by the circuits 9, 16, and 17.

The amplifier 22 is the transresistance amplifier which provides the virtual earth at the junction between Zu and Rs.

In the known arrangement the voltage across the unknown Zu is passed to a differential amplifier 34 whose output is passed by way of a switch 35 to a phase sensitive detector 36. The output of this phase sensitive detector is a periodic signal having an unidirectional component with a mean value proportional to that component of the voltage which is in phase with a reference signal applied by way of the connection 37 to the phase sensitive detector. Thus by employing two reference signals in phase quadrature over first and second intervals, output signals proportional to real and imaginary components of the voltage across the unknown Zu are obtained.If, in further third and fourth measurement intervals the switch 35 is operated to connect the differential amplifier 38 to the PSD 36, voltages proportional to the voltage across the standard resistor Rs are obtained at the output of the PSD 36. These latter voltages are proportional to the real and imaginary components of the current in the unknown Zu In other words the action of the half wave switching PSD 36 consists of multiplying the selected input signal by the switching function which is a square wave of the same fundamental frequency as the input signal. Convolution of the spectra of the two signals produces an output component at DC which has a mean level of magnitude proportional to the phase difference between the inputs and represents the phasor component of the input signal resolved against the switching axis.

However, if the input signal contains any d.c. component this too will contribute to the d.c. output of the half wave PSD. The half wave PSD input may contain a d.c. component due to imperfections in the bridge signal handling paths. The input offset voltages of operational amplifiers and the effects of their input current are such imperfections and directly contribute an error to the d.c. output of the half wave PSD. This error can be substantially eliminated by making two measurements of each voltage component, the second measurement being taken with the reference signal shifted by 1 800. The two output signals so obtained are subtracted from one another so that the d.c. offset is eliminated.

The PSD 11 of Figure 1 derives a pair of voltage components and a pair of current components in four separate intervals each with its own reference signal. As mentioned above, each interval is divided into a pair of sub-intervals in which reference signals in anti-phase are used. Thus eight output voltages are obtained in four pairs and after conversion to digital form, the microprocessor subtracts values in each pair to eliminate any d.c. offset.

The circuit of Figure 4 is used and this is based on a four channel programmable amplifier (PRAM -Trade Mark) available from Harris Semiconductor and described in the Harris Integrated Circuits Catalogue 1 973. This integrated circuit is contained in the broken line 40 of Figure 4. In conventional use the integrated PRAM circuit 40 is used as a four channel switchable and selectable amplifier, not as a phase sensitive detector.

In the present invention the four input operational amplifiers 41 to 44 of the circuit 40 are employed as follows: the non-inverting input of the amplifier 41 monitors the voltage channel for. the voltage developed across the unknown Zu, the amplifier 42 monitors the voltage ground at the unknown Zu, the amplifier 43 monitors the current ground at the standard resistor Rs and the amplifier 44 monitors the current channel at the unknown Rs.

(Although "current" is used in the above it will be understood that this refers to the current in the unknown Zu since in fact it is the voltage across the standard resistor Rs which is measured).

The gain of the amplifiers 41 to 44 is controlled by a common feedback network employing resistors 47 and 48.

The differential amplifiers in Figure 3 are replaced by the switch 45 acting as two single pole double throw switches, one corresponding to each amplifier in Figure 3. Two halfwave PSDs are formed by switching between the voltage (or current) channel and the virtual ground synchronously with the alternations of the PSD reference signal. There are two error components at the imperfect virtual earth, a d.c. offset voltage and a small signal voltage due to the finite gain of the amplifier. By switching to the virtual ground rather than true ground this small signal voltage, along with the common mode voltage developed by the excitation signal current across the current lead resistance, is removed just as if a differential amplifier had been used. All d.c. offsets are still effectively removed as mentioned above.

For example, in order to obtain a voltage proportional to the in-phase voltage across the unknown Zu the outputs of amplifiers 41 and 42 are alternately connected by means of switch means 45 to an output amplifier 46. The frequency of alternation is that of the PSD reference signal at that time applied by way of the selector circuit 21. Thus it will be seen that at the output of the amplifier 46 a mean output voltage is developed which is equivalent to the output voltage of the PSD 36 of Figure 3 when the differential amplifier 34 is connected to it.

The current signal is amplified and phase sensitivity rectified by switching between the current channel and current ground1 and the voltage signal by switching between the voltage channel and voltage ground. The inversion of the current signal caused by the virtual earth amplifier is removed by the assignment of the device's channels and decoder logic inputs as shown in Table 2. Hence when the switch means alternately connects the outputs of the amplifiers 43 and 44 to the amplifier 46, a mean output voltage is developed equivalent to the output voltage of the PSD 36 of Figure 3 when the amplifier 38 is connected to it.

Commutation of the analogue switch 45 is controlled by inputs DO and D1 of decoder logic 49 which correspond to reference signal alternations and voltage or current selection, respectively. The effect of these inputs in selecting amplifier outputs is given by Table 1 below.

TABLE 1

D1 DO Amplifier output H L 41 HHL 42 L L 43 L H 44 [Note H and L are abbreviations of high and low, respectively] TABLE 2

Current D1 low Voltage D1 high PSD drive DO low Current ground (43) Voltage channel (41) PSD drive DO high Current channel (44) Voltage ground (42) The use of the PRAM circuit in the way described has the further advantages that a fully buffered configuration is achieved and effectively two differential PSDs are provided within one integrated circuit package.Also the speed of switching is greater than would usually be obtained using field effect transistors (FETs) and equal delays occur in "turning on" and "turning off," in contrast to FETs.

The converter 26 of Figure 1, which empioys a dual slope integrator, is now described in more detail with reference to Figures 5, 6a, 6b and 7.

In the known dual slope integrator an unknown voltage whose magnitude is to be converted into a digital signal is applied to a linear integrator for a fixed time t, (see Figure 5). At the end of the interval t the unknown voltage is disconnected and a reference voltage of opposite polarity is applied to the integrator and at the same time a digital counter is started. The output of the integrator returns to zero under the influence of the reference voltage in a period t2 and the digital counter is stopped when the integrator output voltage returns to zero. Consider two input signals p and q where p is greater than q.

During the interval t, the output of the integrator will increase as shown by the line p while the larger signal is applied to the integrator and, when the reference signal is connected, the digital counter will run for a time t2p Similarly when the signal q is connected to the integrator the output voltage thereof will follow the line q and, when the reference signal is connected, the digital counter will give a digital output t2q Thus it will be seen that the output of the counter is proportional to the magnitude of the applied voltage.

In the dual slope integrator which has now been devised, integration is not carried out for a fixed interval but instead for one or more basic intervals determined as explained below according to the magnitude of the input voltage. At the end of a first basic interval the integrator output is sampled but, if it is less than half the maximum possible integrator output, integration is continued for an additional time equal to the first interval; that is, the integration time is doubled. At the end of the second interval the integrator output voltage is again sampled and should it be below half the maximum possible integrator output, integration is continued for an additional time equal to twice the basic interval; that is, the total integration time is four times the basic interval.This process is continued until either the integrator output exceeds half the maximum possible or until a maximum of 2n basic intervals have elapsed, where n is an integral number, typically three, giving a maximum integration time of 8 basic intervals.

At the end of the integration time, as determined above, in which the sampled output of the integrator becomes greater than half the maximum possible value or when the end of the maximum integration time is reached, the input signal is disconnected and the reference signal is applied. Thus a digital output signal is obtained representative of the integrator output voltage at that time. In this system the output of the converter formed by the integrator is in exponent form and consists of two parts: a mantissa which is the count accumulated in a digital counter while the reference signal is applied and an exponent which is formed from the number of basic integration intervals for which the input signal was integrated. When continually doubled as described above, the reciprocal of this number is the value of a power of two which is the exponent.

This process will now be illustrated with reference to Figures 6a and 6b for three input signals p, q and r in descending order of magnitude. Figure 6a shows the output voltage of the integrator against time during the integration of the unknown signal, the horizontal axis being divided into basic integration periods and the vertical axis showing the maximum possible integrator output voltage Vomax and half this value. When the signal p is applied to the integrator the output voltage rises according to the line designated p and it passes half the maximum output voltage in the first basic integration period.

When the reference signal is applied, the integrator output returns to zero and the output of the converter is then a mantissa proportional to the output voltage reached during integration of the applied voltage and an exponent (to the base 2) of zero, i.e. 20. [Note the exponent for the first period could be any integer m and the exponent for the next period would then be m-1. For convenience m is taken as zero in this example.] When the smaller signal q is applied to the integrator, the output voltage passes half the maximum possible voltage during the second integration period and therefore in this case the exponent is minus 1.The complete output is the mantissa times 2-1. Similarly, when signal r is applied, it is after the third integration period that half the maximum integrator output voltage is passed, but examination takes place after four basic intervals and the exponent is minus 2.

Figure 6b shows the maximum variation of the time (t2) to discharge the integrator using the reference signal and it is apparent that the ratio of maximum to minimum discharge time is 2:1.

An outline circuit for the converter 26 which uses the new dual slope integrator described above is shown in Figure 7. The output from the PSD 11 is applied to a switch 51 and during the period t, the microprocessor 1 9 closes the switch to connect the PSD output to an integrator which is formed by an operational amplifier 52, capacitor 53 and a resistor 54. Comparators 55 and 56 compare the output of the amplifier 52 with reference voltages equal to half the maximum possible positive amplifier output voltage and half the maximum possible negative amplifier output voltage. At the end of the period tithe output from a comparator 57, which has zero voltage as its reference input, is used to determine which of two reference voltage sources 58 and 59 (one positive and one negative) is to be connected by way of a switch 61 or 62! respectively, to the integrator input.

The end of the period t2 is signalled by an output from an EXCLUSIVE-OR gate 63 which receives one input from comparator 57. The other input of gate 63 receives a signal generated by the microprocessor 19 representing the state of the output of comparator 57 at the end of t1. Thus gate 63 always generates a logic signal of one polarity to signal the end of the conversion period t2, irrespective of whether the integrator output voltage V0 approaches zero from a positive or a negative level.

As has been explained, the period t, is, in general, made up of a number of basic integration periods and each of these periods is chosen to be equal to one period of the public electricity supply.

Since the integration of the supply over such a period is theoretically zero any normal mode voltages which appear in the PSD output due to the supply voltage will be eliminated. In this example the mains supply period is assumed to be 20 mS and therefore each of the basic integration periods is equal to this interval.

However, further errors may arise if integration periods are allowed to start randomly, since each basic period will, in general, start at a different voltage in the PSD output, probably introducing asymmetric errors. For this reason, at least the first basic period of integration is started when the switching voltage for the phase sensitive detector changes to the level that selects zero signal output from the phase sensitive detector.

The operation of the circuit of Figure 7 will now be described with reference to the flow chart of Figures 8a and 8b.

When measurement of the output of the phase sensitive detector is to take place a variable I is first set to zero in an operation 64 to indicate the first, or "in phase" measurement of an antiphase signal pair. Then, in order to avoid the above mentioned asymmetric errors, the microprocessor waits until it receives a signal corresponding to the selection of a signal ground by the output from the circuit 21. Since this operation synchronises the integration intervals with the output of the phase sensitive rectifier, this operation 65 is designated Acquisition Period Synchronisation or A.P.S. in Figure 8a.

Two more variables B and C are then set in operation 66; B is used to count the total number of 20 mS integration periods in a conversion, while C lets each extension of the integration time be equal to the previous total time. These two counters ensure that the overall signal integration time continually doubles, as required for floating point AAT conversion.

A switch 67 which resets the integrator in Figure 7 is then opened and the switch 51 is closed in operation 68. A timing sub-routine represented by operation 70 allows the input signal to be applied to the integrator for 20 mS and then the switch 51 is opened again in operation 71.

The variable B is incremented by one and the variable C decremented by one in the next operation, 72.

Since C was set to one in operation 66, a test 73 leads to operation 74 where C is set to the same value as B and at this point another test 75 is carried out to determine whether I equals zero. Again at this stage in the operation of the flow chart I is zero and therefore the test 76 is carried out by examining the outputs of the comparators 55 and 56 to determine whether the output voltage V0 of the amplifier 52 is greater than half the maximum possible magnitude (to/2) of the integrator.

In order to illustrate the operation of Figure 8a it will be assumed that the output of this test is negative and that a test 77 is now carried out to determine whether B (the total number of 20 mS intervals) has reached eight. At this stage B is only one so there is a jump back to operation 68 and a further cycle of integration takes place through operations 68 to 76. Again assuming that the result of the test 76 is negative, test 77 will be carried out and by this time B is equal to two so that there is another jump back to operation 68 when a further cycle of integration takes place up to the test 73.

Since C is now one following operations 74 and 72, test 73 is negative and there is a jump back to operation 68. In this way the variable C is used to double the integration period before the test 76 is again carried out.

Eventually either the test 76 or the test 77 will be positive and a variable Twill be set to the value of C in operation 78. The variable T is later used to set the length of the acquisition period during which the second or "antiphase" measurement is made to the same duration as that of the first.

The end of the acquisition period t, has now been reached and the conversion period t2 begins by setting a variable representing the length of the conversion interval to zero in operation 79.

The microprocessor 19 now tests the'output of the comparator 57 in an operation 80 and closes either the switch 61 (operation 81) or the switch 62 in operation 82 to apply the appropriate polarity of reference voltage to the integrator. One of the counting operations 83 or 84 now takes place within the microprocessor to provide the mantissa of the digital output, and continues until there is an interrupt from the EXCLUSIVE-OR gate 63 which terminates the counting and opens whichever of the switches 61 or 62 is closed and closes the reset switch 67. These actions are carried out in operation 85 which terminates the conversion period t2.

Operation 86 derives the required exponent from the total acquisition period time in B, and a test 87 is carried out to determine whether the variable I is zero. If so then only one measurement of the PSD output voltage has been made and a signal is sent in operation 88 to invert the measurement phase of the signal driving the PSD 11 so that the second measurement can be carried out. Operation 89 is also carried out to store the values obtained for the exponent and mantissa for the first or 'inphase' measurement. In addition, the variable I is set to one in operation 90.

The flow chart of Figures 8a and 8b now jumps back to the A.P.S. operation 65 and then makes the second or antiphase measurement of the PSD output voltage using the same number, T, of basic periods of integration as were used in the in-phase measurement. This same number of basic periods is employed to reduce the possibility of errors due to uncontrollable imbalances in the operation of the integrator. The test 75 which provides a negative output when I is not equal to zero and a test 91 cause integration to continue until the same number of basic periods has elapsed as were employed in the inphase measurement.

When C equals T, the conversion period commences and operation 80 takes place followed by other operations 81 and 83 or operations 82 and 84. Operation 85 follows as before as does operation 86 but operation 87 has a negative output so that the antiphase measurement values are stored in operation 92. The two sets of measurements are subtracted in operation 93 to give the final exponent and mantissa values for the digital version of the output of the PSD 11.

Operations 72 and 68 can be made to take place in approximately 30 microseconds so that the interruption of integration of the PSD signal is small and in any case takes place during the half cycle in which it is zero. However the interruption gradually occurs later in the PSD reference signal cycle and the total delay must not be allowed to exceed a half period of the reference signal. Thus if a reference signal of greater than 1 KHz is used Acquisition Period Synchronisation should be carried out after each 20 mS period, for example by moving operation 65 to a position immediately before operation 68 and after the jumps from tests 73, 77 and 91.An alternative is to change the flow diagram of Figures 8a to 8b to include a chain of timing periods in which each period is followed by a test equivalent to the test 76 and in which the overall integration time, including the time necessary to perform tests 76, still increases accurately in the required steps. In this way the interruption between integration periods can be eliminated.

It will be appreciated that the output signals from the converter 26 appear in four pairs: the first pair when subtracted from one another give the value a representative of the in-phase component of the voltage across the unknown, the second pair when subtracted from one another give the quadrature component b of this voltage (that is the imaginary voltage component), the third voltage pair represent the in-phase component c of the current through the unknown, and the fourth pair when subtracted from one another represent the quadrature component d of this current.

Having carried out the subtractions necessary to form values of a, b, c and dthe microprocessor is able to calculate values for various bridge outputs. In the simplest case when a resistance is measured, the ratio a c is proportional to the resistance of the unknown. In other cases the components of various equivalent circuits can be calculated, as described for example in "Designers' Guide to RCL Measurements," Bob Bato, EDN Magazine, June 5th 1979; and "Electronic Measurements and Instrumentation," B. M. Oliver and J. M. Cage, McGraw Hill 1971.

The AAT converter has the property of maintaining conversion count accuracy over a wide range of input signal levels since, in effect, the signal level measured is normally between the maximum integrator output voltage and half that voltage, the exponent accounting for other differences in the range of input signals. This property has influenced the design of ranges. Considering a purely resistive unknown Ru, when this varies in value from Ras/8 to 8R9, the voltage and current signals developed across the unknown and the standard resistor vary, respeptively, from V 8V and 9 9 8V V when Ru = RV8, to - and 9 o when Ru = 8Rs (see Figures 9a and 9b). Thus if another standard resistor, having a resistance 64 times greater than the first, is selected when Ru = 8Ra then the voltage and current signals again become V 8V - and -.

9 9 Indeed this 64:1 standard resistor switching always results in these signals lying within the same 8:1 dynamic range. In the present embodiment, the AAT converter allows the interval t, to be lengthened to eight basic integration periods each equal to one mains supply period and the 8:1 dynamic range of the signals is fully accommodated to give a 2:1 maximum variation in the mantissa counter over the entire unknown resistance range from 1/8 of the lowest standard resistor to 8 times the highest. A time limit of eight mains periods has been placed on the integration time t1 in order to prevent the measurement cycle from becoming unduly long. When four standard metal film resistors of 4,000 ohms, 256.0 ohms, 16.38 kohms and 1.048 Mohms are employed, the measurement ranges indicated in the table below are obtained.

Range Standard Resistor i Measurement Range 0 4 Q 1/2 Q to 32 Q 1 256 9 32 Q to 2048 Q 2 16.38 K # 2048 Q to 131 K # 3 1.048 M Q 131 K Q to 8 M # The component meter is an impedance measuring instrument and the corresponding inductance and capacitance ranges are defined for XLI or l Xc j in the range Rs/8 to 8Ra.

The microprocessor 19 is programmed to select the correct range for the component meter in accordance with calculations carried out on measurements received from the converter 26. When the unknown component 10 is connected, the control and display circuits 18 prompt the user to type a character R or Z to indicate whether a fast resistance measurement or a complete impedance measurement is required. If mode "R" is selected, the microprocessor assumes that the unknown component is resistive and calculates a/c, where a is the in-phase component of the voltage across the unknown and c is the in-phase component of the current in the unknown. As will be appreciated from the foregoing description of the design of the ranges of the component meter, the ratio of the voltage to current signal is always in the range 1/8 to 8 if the correct range is chosen.Further, the correct range for the bridge can be selected from this ratio. For example, if the ratio is in the range 8 to 512 then measurement should be made one range higher, and if it is in the range 512 to 32768 two ranges higher should be used.

It is convenient to make use of the floating point notation to select the correct range. The floating point representation of 1/8 is 2 x 2-2 when normalised, so that the mantissa M is in the range 0.5 < M < 1.Thevalueof-21x22 M < 1.The value of 3 x 2-2 is represented in the binary notation of the component meter by 0100 0000 0000 0000 1111 1110 or in hexadecimal notation by 4000 FE and 1/8 is the smallest number so expressed with an exponent of -2. The value 8 is represented by 2 X 24 or 4000 04, but is not uniquely identified by its exponent. However, 4000 04 is only one least significant bit greater than 7FFF 03, which is the largest number with an exponent of +3.Thus, if an unknown resistor is measured on the correct range, the binary exponent of the normalised quotient of a c always lies in the range [-2, 3].

When, in the impedance measuring mode, an unknown impedance is measured with the correct standard resistor, the ratio of the moduli of the voltage and current signals always lies in the range 1/8 to 8. This ratio is given by

where the quadrature components of the voltage across, and the current in, the unknown impedance are b and d, respectively. Hence if this ratio is evaluated and normalised the binary exponent is again in the range [-2, 3].

Note: the notation used here which is that of modern systems theory is as follows: a#x < b is [a, b] a Sx < b is[a, b) a < x < b is (a, b) a < xhis(a,h] In other words the [ means that the end value is included, the ( means it is not.

With the standard resistances mentioned above, if the instrument is operated on the lowest range, then the normalised binary exponent of a c will lie in the range [-2,3] for all unknown resistors Ru in the range [0.5, 32) ohm. If the unknown resistor lies in the range [32, 2048) ohm then the ratio of the voltage and current signals will lie in the range [8, 512); the normalised binary exponent will then lie in the range [4, 9] indicating that the measurement should be made one range higher. If the unknown resistor lies in the range [2.048, 131.072) kilohm the ratio of voltage and current signals will lie in the range [512, 32768) ohm. The normalised binary exponent will then lie in the range [1 0, 1 5] indicating that the measurement should be made two ranges higher.Similarly, an exponent greater than 1 5 would indicate that a measurement should be made three ranges higher.

On the basis of these calculations the microprocessor, when operating in the automatic ranging mode, provides control signals for the range selection circuit 23. In view of the dynamic range limitations of practical signal handling circuitry it may be found that the range-finding system described above is reliable only for a maximum jump of two ranges. Nevertheless where there are four or five ranges, if the bridge is programmed to start at one of the two middle ranges, or the middle range, jumps are then made reliably in one direction or another to the correct range after one set of measurements has been taken.

The microprocessor may form part of a single board computer SBC 80/05 manufactured by Intel and described in "SBC 80/05 Single Board Computer Hardware Reference Manual".

The arithmetical calculations carried out by the microprocessor are not further described in this specification since they are a matter of routine programming well known in the programming field.

These remarks also apply broadly to the routines carried out by the microprocessor to control the remainder of the circuits shown in Figure 1.

A flow diagram explaining how the microprocessor 19 carries out auto-ranging is shown in Figure 10.

When the subroutine "RANGE" is called the value a/c or

is available in the microprocessor as a value S. First a test 95 is carried out to determine whether S is less than one eighth and if so a test 96 determines whether the auto-range mode is in operation or not.

When the auto-range mode is operating a first measurement is performed on range 1, the four ranges being numbered 0 to 3. Thus if S is less than one eighth the test 96 will cause a variable N to be set to O in an operation 97 and range 0 to be selected in an operation 98.

It will be seen from Figure 10 that a test 100 together with a test 95 allows the meter to remain in range 1 if S is greater than one eighth but less than 8 while a test 101 allows ranges 2 and 3 to be selected if S is greater than 8 but less than 512 or greater than 512, respectively.

The test 96 together with tests 100 and 103 cause the microprocessor to print the appropriate message in operations 104 or 1 05 when in the manual mode. In this mode, measurement may be started on any range and if S is less than one eighth as a result of this measurement the message "decrease range" is printed out while if S is greater than 8 the message "increase range" is printed.

Only when S is between one eighth and 8 is the test 102 negative and the correct range has been selected. If the meter is already on the lowest range and the message "decrease range" is printed then measurement is under range. Similarly a message "increase range" while on range 3 means that the measurement is over range.

While certain embodiments of the invention have been specificaliy described it will be realised that the invention can be put into practice in many other ways. For example, the excitation signal may be generated using other sources or other synthesisers; other configurations of the unknown and standard resistors may be used and other values chosen for the standard resistors which define the various ranges of the component meter; other configurations of phase sensitive detectors may be used; and other forms of analogue to digital converter may replace the AAT converter 26. Clearly other types of microprocessor may be used. The base of the exponent at the output of the AAT converter need not be binary and indeed some other bases may have advantages.

The AAT converter itself may be used in a wide range of applications, particularly where automatic switching to other ranges is required. Thus the AAT converter may advantageously be used in digital voltmeters or in weighing instruments where the output of the strain gauge is converted to digital form.

In the latter, instead of using a bridge configuration, the resistance of a strain sensitive resistor may be measured directly.

Claims (26)

1. An analogue-to-digital converter comprising: integration means, switching means for applying either an analogue signal which is to be converted to a digital signal, or a reference signal of opposite polarity to the analogue signal to the integration means, first comparator means for indicating when the output signal of the integrator means reaches a predetermined first magnitude when the analogue signal is applied to the integration means, second comparator means for indicating when the output signal of the integrator means reaches a second predetermined magnitude when the reference signal is applied to the integration means, control means for controlling the operation of the switching means to carry out conversion cycles in each of which the analogue signal is applied to the switching means for a predetermined interval or an integral number of the predetermined intervals, the control means applying the reference signal to the integration means at or after the end of one of the said intervals, when the first comparator has indicated that the output signal of the integrator means has reached the first predetermined magnitude, the control means applying the reference signal to the integration means at least until the second comparator indicates that the output signal of the integration means has reached the second predetermined magnitude, and digital means for generating for each conversion cycle a first digital signal representative of the total time for which the analogue signal is applied to the integration means, and for generating for each conversion cycle a second digital signal representative of the total time for which the reference signal is applied to the integration means.

2. An analogue-to-digital converter according to Claim 1 wherein the control means is constructed or adapted to ensure that the total duration of the interval or intervals during which the analogue signal is applied to the integration means is restricted to a set of possible durations in which the possible durations form a geometric progression.

3. An analogue-to-digital converter according to Claim 2 wherein the common multiplier of the geometric progression is two and the first predetermined magnitude is half the maximum possible output of the integration means.

4. An analogue-to-digital converter according to any preceding claim wherein the second predetermined magnitude is zero.

5. An analogue-to-digital converter according to any preceding claim wherein the control means is constructed or adapted to limit the number of predetermined intervals for which the analogue signal can be applied to the integration means to a maximum number, and to apply the reference signal to the integration means at the end of the maximum number of intervals even though the integrator output signal has not reached the first predetermined value.

6. An analogue-to-digital converter according to any preceding claim wherein the digital means comprises timing means, the control means resetting the timing means to zero before the reference signal is first applied in a conversion cycle to the integration means, and the timing means being stopped when the second comparator means indicates that the integrator output signal has reached the second predetermined magnitude.

7. An analogue-to-digital converter according to Claim 6 wherein at least the control means, the digital means and the timing means are formed by a computer.

8. An analogue-to-digital converter according to Claim 7 wherein when the analogue signal is applied to the switching means for more than one predetermined interval, the predetermined intervals are separated by relatively short intervals in which the computer carries out part of its program.

9. An analogue-to-digital converter according to any preceding claim wherein the predetermined interval is equal to the period of the public a.c. power supply of the country in which the converter is to be used.

1 0. A method of converting analogue signals to digital signals comprising the steps of integrating an analogue signal which is to be converted to a digital signal over a predetermined interval or an integral number of the predetermined intervals until either the result of the integration exceeds a first predetermined magnitude or the number of predetermined intervals reaches a predetermined maximum, providing a digital signal representative of the number of said intervals over which integration occurs, modifying the result of the integration by substituting a reference signal of opposite polarity to the analogue signal as the signal to be integrated either at the end of one of the said intervals after the first predetermined magnitude is exceeded or when the number of intervals reaches a predetermined maximum, continuing integration at least until a second predetermined magnitude is reached, and providing a second digital signal representative of the time for which the reference signal is integrated.

11. A method of converting analogue signals to digital signals according to Claim 10 wherein the total duration of the interval or intervals for which the analogue signal is integrated is restricted to a set of possible durations in which the possible durations form a geometric progression.

12. A phase sensitive detector circuit comprising first and second input terminals for the detector connected to like input terminals of first and second high gain amplifiers, respectively, switch means for alternately coupling the output terminals of the first and second amplifiers to an output terminal of the detector circuit, and means for controlling the frequency of operation of the switch means in accordance with a reference signal applied to a reference signal terminal of the detector circuit.

1 3. A phase sensitive detector circuit according to Claim 12 wherein the switch means is coupled by way of an operational amplifier to the detector output terminal and the detector output terminal is connected by means of first and second resistances to ground, the junction of the first and second resistances being connected to the other like terminals of both first and second high gain amplifiers.

14. A component meter comprising a source of excitation signals coupled to terminals for the connection of an unknown impedance, one terminal being connected to the excitation source by way of a standard resistance, a phase sensitive detector according to Claim 12 or 1 3 in which the first and second input terminals are connected to the terminals for connecting the unknown impedance, and third and fourth high gain amplifiers are provided with like input terminals connected to different ends, respectively, of the standard resistor, the other like terminals of the third and fourth amplifiers being connected to the said other like terminals of the first and second amplifiers and the output terminals of the third and fourth amplifiers also being connected to the switch means, and the switch means is constructed to carry out a cycle in which during one interval the output terminals of the first and second amplifiers are alternately coupled to the output terminal of the detector circuit, and during another interval the output terminals of the third and fourth amplifiers are alternately coupled to the output terminal.

1 5. A component meter comprising a source of excitation signals coupled to terminals for the connection of an unknown impedance, one terminal being connected to the excitation source by way of a standard resistance, means for providing first and second analogue signals representative of the voltage between the said terminals and the voltage across the standard resistor, respectively, and an analogue-to-digital converter according to any of Claims 1 to 8 connected to convert the first and second signals separately to digital signals.

1 6. A component meter according to Claim 1 5 wherein the means for providing first and second analogue signals comprises a phase sensitive detector according to Claim 1 2 or 1 3 in which the first and second input terminals are connected to the terminals for connecting the unknown impedance, and third and fourth high gain amplifiers are provided with like input terminals connected to different ends, respectively, of the standard resistor, the other like terminals of the third and fourth'amplifiers being connected to the said other like terminals of the first and second amplifiers and the output terminals of the third and fourth amplifiers also being connected to the switch means, and the switch means is constructed to carry out a cycle in which during one interval the output terminals of the first and second amplifiers are alternately coupled to the output terminal of the detector circuit, and during another interval the output terminals of the third and fourth amplifiers are alternately coupled to the output terminal.

1 7. A component meter according to Claim 1 6 so constructed, or adapted, that the output voltage of one of the first and second amplifiers and one of the third and fourth amplifiers is representative of ground voltage, and at least the first said predetermined interval of each conversion cycle or a group of conversion cycles relating to one pair of said first and second analogue signals begins when one of the voltages representative of ground voltage is applied to the said output terminal of the phase sensitive detector circuit.

18. A component meter according to Claim 1 5 or 1 6 or 1 7 including logic means for generating measurement cycles in which the logic means obtains and stores the in-phase component a of the voltage across the unknown impedance, the quadrature component b of the voltage across the unknown impedance, the in-phase component c of the current in the unknown impedance, and the quadrature component d of the current in the unknown manner.

19. A component meter according to Claim 18 insofar as dependent on Claim 16 so constructed, or adapted that the said one interval and the said other interval are divided into halves, the phase of the alternate connection of the output terminals of the first and second amplifiers and the third and fourth amplifiers to the output terminal of the detector circuit differs by 1 800 in each half, and the values of a, b, c and dare obtained by calculating the difference between signals representative of these values in different halves of the appropriate said one and said other intervals.

20. A component meter according to Claim 1 8 or 19 including range-selection means for automatically selecting the measurement range of the m-eter by varying in selected steps the standard resistance, wherein the logic means calculates: a c or if b and or d are significant,

and the range-selection means selects ranges in accordance with the result of the calculation made.

21. A component meter according to Claim 20 wherein the available steps of the standard resistance are in the ratio 64:1.

22. A component meter according to any of Claims 8 to 21 wherein at least the logic means is formed by a computer.

23. A component meter substantially as hereinbefore described with reference to, and as shown in Figure 1 of the accompanying drawings.

24. A phase sensitive detector substantially as hereinbefore described with reference to, and as shown in Figure 4 of the accompanying drawings.

25. An analogue-to-digital converter substantially as hereinbefore described with reference to, and as shown in Figure 7 of the accompanying drawings.

26. A method of analogue-to-digital conversion substantially as hereinbefore described.