GB2196808A - Oscillation generation - Google Patents

Abstract

A High frequency clocking oscillator arrangement includes a crystal oscillator (1) whose output is applied via a mark space correction circuit (3) to a chain of frequency doublers (5,6,7). All of these circuits are controlled and stabilised by an integrator current generator (4), which is fed from the oscillator (1). The output from the correction circuit and from the doublers are applied as inputs to an output frequency selector (8), which can be controlled to deliver the output from any one of its inputs to any one of a number of outputs. The arrangement is implemented in IC form using merged technology, to provide both bipolar and field effect transistors. <IMAGE>

Description

SPECIFICATION Oscillation generation The present invention relates to an oscillation generation arrangement, usable, for instance, as a high frequency clock generator for electronic equipment.

According to the present invention there is provided an oscillation generation arrangement, which includes a high precision oscillator whose output is applied via a mark-space ratio correction circuit to a frequency doubler chain, current generation means which applies currents of defined values to the correction circuit and to the frequency doublers, and an output frequency selector having a plurality of inputs to which are connected respectively the outputs of the correction circuit and of the frequency doublers, said selection having one or more outputs on each of which can appear either the output of the correction circuit or of any one of said frequency doublers.

An embodiment of the invention will now be described with reference to the accompanying drawings, in which Fig. 1 is a block diagram of a high frequency clocking oscillator embodying the invention.

Fig. 2 shows in somewhat more detail the Integrator Current Generator block of Fig. 1.

Fig. 3 shows in somewhat more detail the Mark-space correction block of Fig. 1.

Fig. 4 shows in somewhat more detail the frequency doubling circuit blocks of Fig. 1.

In the arrangement shown in Fig. 1, there is a crystal oscillator 1, which can be standard crystal oscillator, controlled by an external crystal 2. This oscvillator feeds a mark-space correction circuit 3 which produces a square wave of a defined mark-space ratio from the oscillator output. This correction circuit 3 receives one or more inputs from an integrator current generator 4.

The output of the correction circuit 3.goes to a chain of frequency doublers 5, 6, . . 7, which also have inputs from the integrator current generator 4. The outputs from the doublers and also the output from the correction circuit are applied to an output frequency selector 8. This has frequency select control inputs 9, and one or more outputs 10. It also has an input from the oscillator 1. Signals received on the inputs 9 control the application to the outputs of the frequencies from the doublers, and also from the correction circuit.

Note that with two or more outputs it is possible for those outputs to convey different frequencies to a user system.

As will be seen later, much of the circuitry which forms the various blocks of Fig. 1, uses CMOS transistors, although some of the circuits use bipolar transistors. Hence the chips used for the oscillator arrangement can use the so-called merged technology, in which both bipolar and field effect devices are used.

The use of such technology permits the use of more than one transistor type; since the different transistor types have different parameters, a circuit made in this way can exploit the advantages of both transistor types.

We now refer to Fig. 2, showing the integrator current generation circuitry, which supplies defined currents to the rest of the circuit where the inputs from the generation circuitry are shown as current generators. The circuit shown in Figure 2 provides currents which are a function of the oscillation frequency and of the integrated circuit capacitances, thus allowing the integrator circuits used for other functions to operate with appropriate voltage swings. In this circuit, an initial reference current generated in the switched capacitor formed by the series-connected P and N channel FET s at the input is averaged using one (or more) filter sections, and the output current replicated in NPN and P channel current mirrors such as BT1-FET1 for supply to the respective circuit units.

The switched capacitor causes the generation of an output current from the operational amplifier OA which forms a first filter, defined by VREFC VREpC where C is the value of the capacitor across the N channel device.

The output voltage of the amplifier OA is defined by VOUT = 1R + VD + VOR where R is the value of each of the resistor R in the feedback circuit of OA, D is the diode in that circuit, and VOR is unwanted ripple voltage.

Note that these mirror circuits can supply currents of different values to different ones of the controlled circuits. In the endmost series combination, the two transistors BTe and FETe are directly in series, with the gate of FETe connected to its source.

The amplifier OA also has a feedback circuit, controlled from the reference voltage, to improve its stability, which has also been referred to above.

It will be seen that the N-channel field effect transistor has its source and drain coupled by a capacitor; hence it, with the P-channel device in series with it forms a switched capacitor current generator. This sets the integration currents to be applied to the other parts of the oscillation arrangement to match both the on chip capacitances and the oscillation frequency.

The current sources formed by the P FET current mirrors could be replaced by feed-back type current sources if this is found necessary to ensure adequate P-channel matching.

The mark space ratio correction circuit, Fig.

3, produces a balanced mark space square wave output for driving the frequency doublers. The input from the oscillator is applied to the base of one transistor of a long tailed pair BT2-BT3, the other transistor s base being fed with a reference voltage VREF. The current generator shown connected to the emitters of the long tailed pair is not one of those fed from the integrator current generation circuit of Fig. 2. The relation between the voltage level of the input from the oscillator and the value of the voltage VnEF defines the point at which the conducting conditions of BT2 and BT3 change, and hence the mark space ratios of the output from the collectors.

The outputs from the long tailed pair pass via two pairs of series connected operational amplifiers to a pair of series connected Pchannel/N-channel FET combinations. These are driven from the circuit of Fig. 2, which is represented in Fig. 3 by integrator current generators ICa and ICb. The outputs from these pairs are applied via further amplification to give a balanced mark space ratio connected output.

The output of this circuit can be further corrected in a similar manner if desired.

Fig. 4 shows one of the frequency doublers, whose input comes from the preceding stage, which is either the mark space ratio correction circuit, or one of the frequency doublers, and its output from the transistors BT4-BT5 provides the output of the doubler. The balanced inputs go to a bistable mode from CMOS transistors FET10 to FET14, powered from the Integrator current generation circuit, Fig. 2.

The outputs from the bistable are capacitively coupled to further amplification circuitry, which uses bipolar transistors, to give balanced outputs at the doubled frequency.

As already mentioned, since the circuits described herein use a mix of bipolar transistors and field effect transistors, it is convenient when these circuits are impiemented in integrated circuit form to use merged technology.

In this, the same chip has produced in it both CMOS-type field effect transistors and bipolar transistors. Certain circuit components such as capacitors and inductors can conveniently be realised using integrated circuit techniques.

Claims (10)

1. An oscillation generation arrangement, which includes a high precision oscillator whose output is applied via a mark-space ratio correction circuit to a frequency doubler chain.

2. An oscillation generation arrangement, which includes a high precision oscillator whose output is applied via a mark-space ratio correction circuit to a frequency doubler chain, current generation means which applies currents of defined values to the correction circuit and to the frequency doublers, and an output frequency selector having a plurality of inputs to which are connected respectively the outputs of the correction circuit and cf the frequency doublers, said selection having one or more outputs on each of which can appear either the output of the correction circuit or of any one of said frequency doublers.

3. An arrangement as claimed in claim 2, in which the current generation circuit has an input from the oscillator which is coupled via amplification means to a number of current mirrors, in which each said current mirror includes a bipolar transistor connected in series with field effect transistors, with a user circuit connected between the collector of its bipolar transistor and the source of its field effect transistor.

4. An arrangement as claimed in claim 3, in which said amplification means includes an operational amplifier having the oscillator output coupled to one input and a reference voltage coupled to its other input.

5. An arrangement as claimed in claim 4, in which said operational amplifier has a feed back circuit connected between its output and its said one input, which feed back circuit includes a diode biassed by a voltage proportioned to the reference voltage.

6. An arrangement as claimed in claim 4 or 5, in which the oscillator output is coupled to the operational amplifier input via a series connected combination of a P-channel and an Nchannel field effect transistor which forms a switched capacitor, said oscillator output being applied to the gates of the field effect transistors, and the drain of the P-channel transistor being connected to the operational amplifier, and in which a capacitor is connected between the source and the drain of the N-channel transistor.

7. An arrangement as claimed in claim 1, 2, 3, 4, 5 or 6, in which the mark space correction circuit includes a long tailed pair with the oscillator output connected to the base of one of the transistors and a reference voltage connected to the base of the other transistor, and in which the collector of the transistors of the long tailed pair are connected via current stabilisation circuitry to the output of the correction circuit.

8. An arrangement as claimed in claim 1, 2, 3, 4, 5, 6 or 7, in which each said frequency doubler includes a bistable circuit whose operations are stabilised from the integrator current generation circuitry.

9. An arrangement as claimed in any one of the preceding claims, and which is implemented in integrated circuit form using both bipolar and field effect transistors.

10. An oscillation generation arrangement, substantially as described with reference to the accompanying drawing.