GB2190221A - Signal transforming device - Google Patents

Abstract

The signal transforming device 10 is suitable, inter alia, for producing a Fourier transform. A clock- activated counter 16 selects a cosine function and a sine function value at each of a set of frequencies. The function values are stored in a counter-addressed memory 22. Each value is multiplied in a respective multiplier 20R,20I by a signal sample from buffer 12. The products are added to the contents of respective registers 30R and 30I, in which products involving each function are added to the contents of a respective location. A further signal sample is multiplied by a further value of each of the functions and augments register contents. The register contents are constrained to decay by the application of a decrement factor implemented by memories 28R and 28I. The result is that the invention simulates a bank of filters each with bandwidth governed by the decrement factor and centre frequency set by the corresponding stored function. The invention may be arranged for individual filter centre frequency agility and/or individual filter bandwidth agility. It generalises to arbitrary filters or functions, and provides an elegantly simple means for decomposing a signal into a set of functions and corresponding amplitude coefficients. <IMAGE>

Description

SPECIFICATION Signal transforming device This invention relates to a signal transforming device for transforming a signal into a set of functions each with a respective amplitude coefficient.

The most common form of signal transforming device is that for implementing a Fourier transform. Such a device is commonly used in radar and sonar signal processing. It typically consists of a computer, possibly a microcomputer, programmed to input a signal as a series of sample values and to implement an algorithm to decompose the signal into frequency components. Considerable attention has been given to the production of algorithms which reduce the computing time necessary to produce a transform. Despite advances in computing speed and algorithm manipulation, this form of transforming device suffers from the disadvantage that one must first sample a signal and then wait for the transform to be produced. Furthermore, the algorithm and corresponding computer programme is specific to a particular function set or frequency space.If it is required to change the function set the computer must be reprogrammed.

The present invention provides an alternative form of signal transforming device.

The present invention provides a signal transforming device for transforming a signal, the device including sampling means arranged to sample the signal sufficiently to define it, and a signal processing channel including both multiplying means for multiplying each signal sample by a respective value of every function in a function set to produce function amplitude contributions and accumulating means for accumulating function amplitude contributions to provide a signal decomposition in terms of coefficients of the function set.

In the case of a Fourier transforming device providing a signal spectrum involving decomposition into sinusoidal functions, the sampling means is arranged to operate at least at the Nyquist rate for the highest frequency in the signal spectrum.

The invention provides the advantage that it is not restricted to a particular transform algorithm and function set, nor does it require operation of a computer programme before a transform is obtained. The functions may be stored in a memory and value addressed cyclically, or may be generated electronically from clock signals. Thus any set of functions may be employed, and change between function sets may be implemented simply by altering stored values or generated signals. Furthermore, the contents of the accumulating means may be examined at anss time, so that the signal decomposition is continuously available subject only to addressing constraints and the time required for an initial decomposition to build up in the accumulating means.

In a preferred embodiment, the processing channel includes means for applying a time window function to accumulating amplitude contributions. Such means may be arranged to decrement the accumulating amplitude contributions. Decrementing may be implemented in a manner appropriate to effect exponential decay of the accumulating amplitude contributions, and the function set may be a set of the digital equivalents of circular functions at different frequencies. In this embodiment the invention simulates a bank of finite bandwidth filters, each filter having a centre frequency corresponding to that of a respective function and a bandwidth determined from the rate at which corresponding amplitude contributions decay.

The invention may include two signal processing channels for accumulating real and imaginary components of signal spectrum amplitudes. Each channel has a respective multiplying means and accumulating means. One channel implements multiplication by a set of cosine functions and the other by a set of sine functions at like frequencies. The invention may include means for summing the squares of the real and imaginary components as a function of frequency to provide a power spectrum. The power spectrum may be processed to identify a strong feature and thereby determine the position of a required signal of unknown frequency. This is particular advantageous for rapid location of telecommunications signals having a carrier wave frequency uncertainty for example.Each accumulating amplitude coefficient of the signal spectrum may be decremented by a constant fraction on each occasion that a signal sample is taken. The fraction may be the same for all amplitude coefficients, or each may have a respective decrement fraction. The decrement may be implemented by a storage device which, for any input address signal, outputs a value corresponding to that address decremented.

The sampling means may be arranged to provide one-bit signal samples and the multiplying means to multiply by one-bit function values. The accumulating means may be arranged to accumulate quantities corresponding to positive and negative values. Amplitudes may be decremented in a storage device which is also arranged to provide for subtraction from accumulating means contents. Such subtration provides for accumulating means contents to change by positive or negative increments according to whether the multiplying means produces a high or a low multiplication result magnitude.

In order that the invention might be more fully understood, embodiments thereof will now be described, with reference to the accompanying drawings, in which: Figure 1 is a schematic block diagragm of a signal transforming device of the invention; Figure 2 schematically shows in more detail a clock incorporated in the Fig. 1 device; Figure 3 provides clock signal waveforms produces by the Fig. 2 clock; Figure 4 schematically shows a single pole recursive filter simulated by parts of the Fig. 1 device; Figure 5 illustrates the response of a device of the invention at three adjacent frequencies; Figure 6 is a schematic block diagram illustrating the use of the Fig. 1 device for power spectrum searching; Figure 7 is a schematic block diagram of part of a variable decrement signal transforming device; and Figure 8 is a schematic block diagram of a function memory for a variable function signal transforming device.

Referring to Fig. 1, there is shown a schematic block diagram of a signal transforming device of the invention indicated generally by 10. The device 10 comprises an input signal buffer and digitiser 12 incorporating a one-bit edge-triggered latch (not shown). This latch is triggered by the one-bit signal on a line 14, which is connected to the ninth most significant bit (9MSB) of value 26x(x=0 or 1) of a fifteen bit synchronous counter 16. The counter 16 is clocked by the rising edge of a first phase clock signal 0, from a 3.072 MHz clock 18. The clock 18 is arranged to generate three clock signals of the same frequency but differing phase as will be described later.

The one-bit output from the buffer 12 is fed as a first input to each of two one-bit multipliers 20R and 201 implemented as EX-NOR gates. A 32Kx2 function memory 22 has two 32Kx 1 sections 22R and 221 which furnish second inputs to the multipliers 20R and 201 respectively.

The function memory 22 comprises eight 8Kx 1 memories together with a 2x4 bit multiplexer (not shown) arranged in a known manner and having an operating speed of 150 nsec. The fifteen bit counter output is fed via a bus 24 to the memory 22 to address its contents for output to the multipliers 20R and 201.

The multipliers 20R and 201 are the initial or input elements of two identical signal channels providing real and imaginary contributions to a required signal transformation. Elements in the real channel suffixed R will now be described. Equivalent elements in the imaginary channel are illustrated with like reference numerals suffixed I, but are not described to avoid unnecessarily duplicated description.

Multiplier 20R provides a one bit output signal fed as a second least significant bit (2LSB) to a first input of a four bit full adder 26R. The adder 26R receives as a second input the four higher order bits (4 Hi) of an eight bit output from a 256 x 8 bit decrement memory 28R of 150 nsec operating speed. The adder 26R provides an output connected to the four higher order inputs (4 Hi) of a 128x8 bit register 30R consisting of a 35 nsec RAM. The four lower order output bits (4 Lo) of the decrement memory 28R are connected to the corresponding inputs of the register 30R. The contents of the register 30R are addressed by the seven lower order output bits (7 Lo) of the counter 16. Input to the register 30R is triggered by logic 0 or WE (not write enable) pulses generated as a second phase signal 02 by the clock 18.

The eight bit output from register 30R is fed to two eight bit latches 32R and 34R. The latch 32R is triggered by a third phase signal 03 from the clock 18, and provides input to the decrement memory 28R. The latch 34R is triggered by one bit output signal from a seven bit comparator 36. The comparator 36 receives a first comparison input of the seven lower order output bits (7 Lo) of the counter 16, and a second comparison input signal via a frequency address bus 38. The one-bit comparator output is also fed to a signal availability indicator output 40, from which for example an interrupt signal is available to initiate further signal processing by a microcomputer (not shown). The comparator 36 together with its associated address bus 38 and indicator output 40 are arranged to co-operate with the imaginary or I channel in an equivalent manner.

Except where indicated earlier to the contrary, the circuit of Fig. 1 may be constructed of 74LS or 74F TTL components.

The memory half 22R contains 128 cosine functions each stored as 256 one-bit digital values.

The nth cosine function has a frequency fn given by 12n kHz kHz (n = 1(n-i to 128) (1) 128 Equation (1) defines 128 functions with equal spacing between adjacent frequencies. The function storage arrangements are as follows. The memory half 22R stores 128 zeroth cosine values at successive addresses followed by 128 first values, 128 second values and so on. The pth value of the nth cosine function is stored at a memory address which is the binary equivalent of (128p+n- 1) where p=0 to 255. The first cosine function with frequency 12/128 kHz is accordingly stored at the addresses which are the binary equivalents of 0, 128, 256....

128r.... (r=0 to 255), and consists of one cycle stored in 256 locations, or 128 logic 1 values followed by 128 logic 0 values. Other functions are represented by corresponding bit patterns of 1s and Os simulating the appropriate frequency in each case. The nth function has n stored cycles. The effect of this storage scheme is that the seven lower order bits of the counter 16 specify the cosine function and the eight higher order bits the function value or phase.

The decrement memory 28R contains 256 eight bit stored values each derived from its address, the address being provided in each case by the contents of register 30R addressed at any instant and held in latch 32R. The effect is that a value in register 30R generates an output from decrement memory 28R which is a digital approximation to the register value multiplied by a decrement factor 0.98773 with subsequent subtraction of 00010000. The decrement factor may be written as (1be), where e=0.012272. As will be described, the multiplication provides for successive inputs to register 30R to decay to 1/e of their initial values after about 81 subsequent samples have been taken, or about 10,368 clock cycles later (--3.4 msec).Moreover, the subtraction provides for adder 26R to implement the equivalent of addition and substraction of 1 from register values according to whether the output of multiplier 20R is 1 or 0 respectively.

The register 30R contains 128 values each in the range 0 to 255. The values are each treated as equivalent to being in the range +127.5 to -127.5 for the purposes of interpreting output from the device 10. This interpretation allows the device 10 to accommodate positive and negative signal values while operating with all positive digital quantities. Register values 00000000 to 01111111 correspond to -127.5 to ~0.5, and 10000000 to 11111111 to +0.5 to +127.5 respectively. There is no provisiion for zero to preserve uniform discretisation.

Register values equivalent to positive and negative quantities are required to decay towards 10000000 (+0.5) and. 01111111 (-0.5) respectively. This requires the stored binary quantities to decrease in the former case but increase in the latter.

Addition and subtraction at adder 26R arises as follows. Multiplier 20R provides an input to the 3MSB of adder 26R for addition to the four higher order bits output from decrement memory 28R. Adder 26R therefore receives a 2 or 0 input according to whether or not multiplier 20R receives two 1 inputs. The adder 26R also receives the four higher order bits output from decrement memory 28R, these being prearranged to correspond to 1 subtracted from the 4MSB of the corresponding address provided by the addressed value in register 30R.

Adding 2 or 0 to one less than a given value is equivalent to adding or subtracting 1 from that value. This accordingly implements addition and subtraction at adder 26R. Minor exceptions occur for register values less than 00010000 and insufficient for subtraction. These are reduced to 00000000. In addition, if the input signals to adder 26R sum to more than 1111, the adder is arranged to output 1111 by use of the carry output bit in conjunction with known gating means (not shown).

The foregoing arrangements provide for the register contents to undergo exponential decay, and to be incremented or decremented by 1 in the 4MSB on each clock cycle according to whether the output from multiplier 20R is high or low.

Referring now to Fig. 2, there is shown in more detail the internal circuitry of the clock 18, which produces clock signals 0" 4)2 and 03 of differing phases. The clock 18 comprises a single phase clock signal generator 50 producing a 3.072 MHz signal fO. Output from the generator 50 is fed to two Schmitt trigger circuits 52a and 54a. The output from Schmitt trigger 52a passes via a delay network R,C1 to a third Schmitt trigger 52b and thence to an output 56 providing 0,.

Similarly, the output from Schmitt trigger 54a passes via a second delay network R3C3 to a fourth Schmitt trigger circuit 54b and thence to an output #58 providing 03. Th generator signal fO is ORed at 60 with 4)3 to produce 4)2 to an output 62.

The delay networks are arranged to produce clock signal delays T, and T3 given by T,=R,C,=30 nsec (2.1) T3--R3C3=75 nsec (2.2) Referring now to Fig. 3, graphs of O to 4)2 are plotted against time. The signals X, and 03 are equivalent to O with a relative delays of T, and T3 respectively. The signal 4)2 however goes high in phase with çfO but low in phase with 02. It is accordingly asymmetric, being high for a period (2/F+T,+T3) but low for (2/F-T1-T3), where F is the frequency of generator 50.As has been indicated earlier, the signals illustrated in Fig. 3 are employed as follows: st, (rising edge) operates counter 16, 4)2 provides "Write" signals to effect input to register 30R, and 03 operates latch 32R.

The arrangement described with reference to Figs. 1 to 3 operates as follows. A change in 00 from low to high at time t, (see Fig. 3) produces a like and substantially simultaneous change in 02. The WE input of register 30R is consequently held high so that no new input can be loaded into it. At time t2 after a delay of T1, ie 30 nsec or about one tenth of the 00 period (325 nsec), 0, changes from low to high producing a change in the least significant bit output of counter 16.

The counter 16 requires a short time to settle and change address lines to register 30R, which in turn requires 35 nsec to respond by outputtng the address contents. T3 is arranged to be longer than the sum of these time intervals. At time t3, where t3=t1+T3, 4)#, changes to high operating latch 32R to latch the value addressed in register 30R. At time t4, where t4=t3+ 150 nsec, decrement memory 28R (addressed by the latched value) responds by outputting one less than an exponentially decayed version of its current address input. The decrement memory output is divided into upper and lower four-bit bytes and passed to adder 26R and register 30R respectively.

The cosine memory half 22R responds to the change in the output of counter 16 at time tS, where t5=t1+T1+1SO nsec+counter settling time+line charging time, ie t5=t1+190 nsec, allowing 10 nsec for settling and charging times.

The lower seven bits of the counter 16 select the cosine function or frequency stored in memory half 22R, and the upper eight bits the function value. Since the output latch of buffer 12 is triggered by a negative edge at the 9MSB output of conter 16, it provides a new one-bit signal sample every 128 cycles very shortly (--10 nsec) after a positive-going change in the 0, counter drive signal. Each signal sample remains at the buffer output for 128 clock cycles, and is 1 or 0 according to whether the corresponding sampled output to buffer 12 was positive or negative.

When at time t5 a cosine functio value from memory half 22R arrives at multiplier 20R, it is multiplied by the current signal sample and the result passes to adder 26R. Here the result is added to the upper four bits from decrement memory 28R, whose lower four bits join the adder output at the input to register 30R. Accordingly, very shortly after t5, at least by 10 nsec later, the input to register 30R has settled.

At time t6=t1+2/F+T3=t,+240 nsec (F=clock frequency), 4)3 goes low allowing the input to register 30R to overwrite the current value addressed by the output of counter 16. The effect of this is that the addressed location in register 20R receives its previous value reduced by an exponential decay factor (1WE) and incremented or decremented by 1 in the 4MSB according to whether the output of multiplier 20R is 1 or 0 respectively.

At time t7=t1+1/F, the positive edge of 4)2 latches the settled input into the register 30R, and a new positive going edge of 00 restarts the foregoing procedure. The mode of operation follows a "Lock-Step" principle. Early in any clock cycle, latch 32R holds the current contents of register 30R while other parts of the device 10 operate to update it. Towards the end of each clock cycle the updated value overwrites that currently held in the register 30R. On the next clock cycle, the output of counter 16 increments by 1 addressing the next location in register 3OR. Accordingly, the value stored in the next register location becomes updated in the same way but by the next cosine function.

Consider now a clock signal 01 occurring at a time rO appropriate to change all fifteen bits of the counter 16 output to 0. This addresses the zeroth value of the first cosine function in memory half 22R, and also the zeorth location in register 30R. Moreover, in view of the change in the 9MSB output of counter 16, a new signal sample appears at the output of buffer 12. This sample is multiplied by the zeroth value of the first cosine function (frequency 12/128 kHz) at multiplier 20R, and the result updates the zeroth location in register 30R. On the next clock cycle, the same signal sample is multiplied by the zeroth value of the second cosine function (24/128 kHz), and the result updates the first register location.On the qth clock cycle (q=O to 127), the zeroth value of the (q+ 1)th cosine function multiplies the signal sample to update the qth register location.

When 128 clock cycles have elapsed after lo, at T128 say, a new signal example appears at the output of buffer 12 by virtue of the counter 9MSB change from 1 to 0. Moreoever, the counter output comprises an 8MSB of 1 together with 05 elsewhere. In analogous manner to that described previously, on the next 128 clock cycles beginning at T128 to T255 respectively, the frst value of each stored cosine function is multiplied by the new signal sample and the result updates the respective location in register 30R associated with the relevant cosine frequency in each case. After 256 signal samples or 256x 128 (32768) clock cycles, all values of all cosine functions have been employed to provide contributions to the contents of register 30R, and each location is associated with a respective frequency Over a period of time, the register 30R builds up a transform of the input signal to buffer 12 in terms of a set of cosine functions. The transform is weighted in favour of more recent signal samples by being determined via an exponential time window providing for amplitude decay. The cosine transform at any time is the respective value stored in registers 30R, and this may be read out or addressed by presenting the input of comparator 36 with the function number or register address on bus 38.The lower seven bits of the counter 16 are compared at 36 with the read-out address, and when these are equal a pulse passes to latch 34R. The latch 34R incorporates a delay (not shown) so that it does not operate until the register 30R has responded to the new count or address input. At this point the register value or frequency amplitude is latched at 34R. The comparator output pulse also passes to the signal availability output 40, which provides an indication that the amplitude of the addressed frequency is available to be read.

The imaginary or I channel comprising elements 201 to 341 operates in exactly the same way as the real channel of elements 20R to 34R. Memory half 201 contains sine functions instead of cosine functions. Register 301 consequently builds up a sine transform of the input signal simultaneously with a cosine transform formation in register 30R. Each sine function amplitude is available to be read from latch 341 simultaneously with the respective cosine function of the same frequency. The signal transforming device of the invention accordingly provides a signal transform into a set of frequencies with both real and imaginary amplitude coefficients.Equation (1) expresses the set of frequencies, which can be expressed as co, 2w, ... nw .... where w is the lowest angular frequency, ie that of the first cosine or sine function. There is no DC or zero frequency term.

Whereas the foregoing analysis assumed for convenience a starting point of zero for the output of counter 16, this is not in fact a requirement. In addition, the order in which register contents are updated is unimportant. The exponential decay of the contents of the registers 301 and 30R ensures that any initial register value decorrelates as sampling progresses. Moreover, the minimum sampling or Nyquist rate for any frequency spectrum is twice the maximum frequency (12 kHz in the foregoing example) to avoid aliasing. The sampling rate is accordingly 24x 103 per second, and each sample requires 128 clock cycles for multiplying by sine and cosine functions. This dictates the clock frequency of 24x 103x 128 Hz or 3.072 MHz previously stated.

The device 10 produces a signal transformation related to a Fourier transform as follows. A Fourier transform carried out over an infinite length of time produces amplitude coefficients for each frequency, and the frequencies are discrete. In other words the bandwidth at each frequency is infinitely narrow. A Fourier transform carried out over a finite length of time produces finite bandwidths related inversely to the length of time. If the device 10 did not employ a decrement factor (1-#) to produce exponential decay, the amplitude coefficients built up in registers 20R and 201 would also correspond to infinitely narrow bandwidths. The effect of introducing exponential decay is to broaden the bandwidth at each frequency to a degree proportional to e.

The device 10 samples a signal represented by a function of time f(t) at time intervals T where: T#/wmax (3) Equation (3) represents Nyquist sampling for angular frequencies cs in the range: O#W(Wmax (4) It is a precondition that f(t) has no angular frequency components outside the range specified in (4). At each sampling time t=k#/Wmax past sample values of f(t) are viewed through a window function (exponential in the foregoing example).

The device 10 produces the cosine and sine transforms, Fc((0n,#,k) and Fs(ct)n,A,k) of f(t) at an angular frequency w, given by

where: n= 1 to 128, and COn is the angular frequency of the nth sine or cosine function; A is the exponential decay constant; 9 is an integer.

Equations (5.1) and (5.2) may be rewritten:

Equations (6.1) and (6.2) illustrate the recursive nature of the transform implemented in digital form by means of the invention. Each successive transform value at an angular frequency #n is equal to the respective immediately preceding value multiplied by a decrement factor e-# or (1-#) and incremented by the product of the update signal sample with the corresponding cosine or sine function of that frequency.

Equation (6.1) is illustrated diagrammatically in Fig. 4, which is a special case of a one pole recursive filter. Fig. 4 has the same reference numerals as corresponding parts of Fig. 1 and will not be described.

It can be shown that an input signal of angular frequency Co and average energy per sample E(#) will produce a response R(#,#n) in a filter having an Equation (6.1) oe Fig. 4 characteristics and centred on the angular frequency #n, where E(#) R(#,#n)=----[ 1+(1-#)-2(1-#) cos(#-#n)]T]-1 (7) 4 where T is the signal sampling interval and E is as previously defined.The parameters e and A are related by: e@=1-# (8) ie #=-loge(1-#) (9) Equation (7) has a maximum value of E(#)/4#, ie for E(#) = 1, and the filter response is half maximum at angular frequencies # given by |#-#n|T## (10) (to which there are two solutions) If the input signal is part of a spectrum having a maximum frequency fmax (##max/2#) sampled at the Nyquist rate of 2fmax, and the full width of the filter band at half power is Af, then: |#-#n|=.2##f (11) T=fmax (12) Combining (10), (11) and (12): : # 2#fmax #f # ---=---- (13) #T # and it Af C - - (14) 2 fmax e is accordingly directly proportional to the filter bandwidth to a fair approximation.

The device 10 simulates a bank of filters of angular centre frequencies con given by multiplying Equation (1) by 2it, ie: 12n con=27r x 103 radians sec-l (15) 128 where n=1 to 128.

The spacing between adjacent filter frequencies is 93.75 Hz. It is convenient to arrange that an input signal frequency component midway between fn and fn+1 produces equal responses in filters centred at each of these frequencies. Putting #f=93.75 Hz and fmax=12 kHz in Equation (14): # 93.75 # # --- . ----------- = 1.2272 x 10-2 (16) 2 120 x 103 This value of e provides for decay to 1/e after about 81 sampling intervals, or 10,368 clock cycles (--3.4 msec).

Rewriting Equation (7) in terms of frequencies in Hz and fmax and substituting the Equation (16) value of e:

Referring now to Fig. 5, Equation (17) is shown plotted against frequency for three adjacent frequencies fn-1, fn and fn+1, where: fn+1-fn=fn-fn-1=#f=93.75 Hz.

This provides three graphs 70, 72 and 74 of fractional response against frequency, each graph intersecting the or each adjacent graph at the half maximum point. Each graph has a maximum value of 1/4:2 or 1.66 x 103. The device 10 is equivalent to 128 filters with centre frequency spacing and bandwidth as shown in Fig. 4.

The device 10 simulates 128 LCR tuned circuits which ring in response to an applied signal and whose oscillations decay with time by virtue of the damping resistor. The O of the nth simulated tuned circuit or filter of frequency fn is fn/#f=Qn say, given from Equations (1) and (13) by: # # Qn=---- ~ -----fmax 2#fmax 128 nit ie Qn= (n=1 to 128.) (18) 5126 The filters are accordingly of equal bandwidth and linearly increasing Q, both these parameters being variable by varying e. However, if Qn is increased by reducing the value of e, there are two consequences.Firstly, the contents of registers 30R and 301 will tend to build up to larger values since their rate of decay is reduced. Secondly, the decrement factor (1-:) on each cycle is smaller and the decrement memories 28R and 281 must accommodate smaller differences.

This may be dealt with by increasing the width of storage to 16 bits for example in both the registers and the memories.

Referring now to Fig. 6, there is illustrated an application of the device 10 to the acquisition of a telecommunications signal of unknown frequency within the band 0 to 12 kHz. The device 10 is connected to a microprocessor 80, which supplies input to a digital to analogue (D/A) converter 82. The D/A converter supplies an analogue signal to a voltage controlled oscillator (not shown) incorporated within a modem 84.

The Fig. 6 arrangement operates as follows. Referring now also to Fig. 1, the microprocessor 80 places the address 00000000 on frequency address bus 38. When the seven lower order bits of counter 16 are all zero, comparator 36 outputs a pulse. This becomes an interrupt signal to the microprocessor 80, and also a trigger signal to operate latches 34R and 341 and latch the contents of registers 30R and 301 respectively. The real and imaginary amplitude values at the first frequency (12/128 kHz) are read by the microprocessor 80 from the latches 34R and 341.

The microprocessor 80 is programmed to subtract 127.5 from the values read to convert them to values in the range +127.5 to -127.5 as discussed earlier. Referring to these converted values as R, and Ii, the microprocessor computes the response P1 at the first frequency, where P,=R2+12, (18) In the general case, the microprocessor 82 generates the response Pn at the nth frequency from: Pn=R2n+l2n (19) The microprocessor 80 is arranged to read the contents of latches 34R and 341 once every 64 signal samples. The microprocessor 80 is only required to read the latch contents at intervals in the order of the decorrelation time of the stored spectrum, this being the time for amplitudes to decay by a factor 1 /e or about 81 signal sample intervals.A read interval of 64 signal sample intervals satisfies this. For convenience, the order in which the frequencies are read is preferably 0, 64, 1, 65 m, m+64 (m=O to 63), where (m+63)=n in Equation (1).

This requires the microprocessor 80 to read the latch contents every 64x 128-:3.072:': 106 sec, ie 2.67 msec, a factor of 8x 103 slower than the rate of the clock 18.

The microprocessor 80 is arranged to identify the frequency at which the maximum signal power is detected. The program required for this is elementary and will not be described. The binary code corresponding to the frequency number or value of n in Equation (1) is then output to the D/A converter 82 for conversion to an analogue voltage. This voltage controls the operating frequency of the modem 84, which accordingly becomes turned to the frequency band of maximum signal power.

The arrangement of Figs. 1 and 6 may be employed to reduce the frequency ambiguity of low bit rate signals (eg 50 bits/sec) occurring in satellite communications. After heterodyne downconversion from microwave to audio frequencies, these signals are characterised by a frequency ambiguity of O to 12 kHz arising from Doppler frequency shift due to satellite motion and inaccuracies between transmisssion and reception oscillator frequencies. The device 10 is capable of reducing the frequency ambiguity of a signal with a typical signal/noise ratio by a factor of 128 in less than 0.1 sec. A conventional modem could be expected to lock to a carrier signal in a further 0.3 sec, giving a total of 0.4 sec for acquisition. This is comparable with systems of very much greater complexity, and up to 100 times faster than techniques of equivalent or somewhat greater complexity.

The device 10 of Fig. 1 employs adders 26R and 261 and registers 30R and 301 giving high outputs when they overflow, as has been said. This is adequate for the purposes of the previous example of detecting a low bit rate telecommunications signal in a band of frequency ambiguity, since it is only necessary to identify a strong spectral component in the presence of weaker components. The absolute magnitude and phase of the frequency components given by their sine and cosine amplitudes is not important in that instance. For applications of the device 10 such as spectral analysis, where both absolute magnitudes and phases of spectral components are important, the bit lengths of the adders 26R and 261 and registers 30R and 301 are chosen so that overflow does not occur.

For some applications of the invention, one-bit signal samples and cosine and sine functions may provide insufficient accuracy. The device 10 is easily adapted to accommodate multibit signal sampling and multibit cosine and sine functions. The buffer 12 is replaced by an A/D converter, the memory 22 becomes extended as appropriate to the function value bit length, and multipliers 22R and 221 become multi-bit. Other circuit components also increase in bit capacity.

The penalty for this is increased complexity and possibly reduced operating speed. Multipliers 20R and 201 for example implemented as EX-NOR gates are extremely fast, whereas multibit equivalents are much slower. It is of course possible to employ a memory arranged as a look-up table to implement multiplication, which is a faster alternative.

Referring now to Fig. 7, there is schematically shown a part of a further embodiment of the invention arranged for variable or agile bandwidth filter operation. Fig. 7 shows a signal amplitude accumulator 90 which is arranged to act in a manner similar to the combination of adder 26R, decrement memory 28R, register 30R and latch 32R in Fig. 1. A second accumulator 90 (not shown) replaces the equivalent parts of the I channel in Fig. 1.

The amplitude accumulator 90 comprises a register 92 having N locations or addresses each of B bits. The register 92 receives input from a summer 94 and from a decrement memory 96, and supplies output to a tristate latch 98. The decrement memory 96 has an input/output port l/O B bits wide connected to the output of a second tristate latch 100. The I lower order bits (I Lo) of the memory 96 1/O port are connected to the I Lo inputs of the register 92, and the B-l higher order bits (B-l Hi) of the I/O port to the adder 94. The memory 96 has a lower order address input AL B bits in width connected to the latch 98 and also to a third tristate latch 102.

A higher order address input AH of the memory 96 is N bits in width and is connected to the output of an N bit multiplexer 104. The multiplexer 104 receives two inputs each N bits wide, one input being from the N lower order bits of a counter 105 and the other from a fourth tristate latch 106. The counter 105 also addresses locations in the register 92. A mode selector 108 is arranged to provide enable signals at E to all four latches 98, 100, 102 and 106, and also latch triggering signals at L to all but latch 98 of these. Latch 98 receives triggering signals from a clock (not shown), the clock also providing write enable signals (WE) to the register 92.

The mode selector 108 provides enable and read/write signals to the memory 96 at E and R/W, and controls output from the multiplexer 104.

The latches 100, 102 and 106 receive input from a common bus 110 connected to a microprocessor 112. The microprocessor 112 also controls operation of the mode selector 108 and receives the B-H higher order bits (B-H Hi) output from the register 92.

The decrement memory 96 has a capacity of 2BxBxN; ie it contains 2B locations for each of the N locations in registers 92, and each decrement memory location is B bits in width. The memory 96 is equivalent to a separate decrement memory 28R for each location in register 92.

The amplitude accumulator 90 operates as follows. The microprocessor 112 controls the mode selector 108 to disable latch 98, enable memory 96 and latches 100, 102 and 106 and connect the decrement memory address input AH via multiplexer 104 to latch 106. The microprocessor 112 then places a lower order memory address on bus 110, and latch 102 latches this on receipt of a latch trigger pulse from mode selector 108. A higher order memory address is then placed on bus 110 by the microprocessor 112, and latch 106 latches this on receipt of a latch trigger pulse. The microprocessor 112 then places a data word B bits in width on bus 110, and latch 110 latches this on receipt of a latch trigger pulse.The decrement memory R/W input is then pulsed low, and the decrement memory 96 consequently reads the contents of latch 100 via the l/O port into the Ication AHA, addressed by the contents of latches 106 and 102. The microprocessor 112 then pulses the memory R/W line high, increments the contents of latch 102 by 1, and supplies a new data word to latch 106. The decrement memory R/W input is pulsed low once more so that the next location in the decrement memory 96 is assigned a data word. This procedure is repeated until the microprocessor 112 has cycled through the lower order address space of the decrement memory 96. The higher order address in latch 106 is then incremented by 1, and the lower order addresses are all assigned data words once more. This continues until the decrement memory 96 contains data at all addresses.

The data in the memory 96 is arranged to correspond to a respective set of decrement values for each location in register 92, each set corresponding to a respective decrement factor. The nth location in register 92 is assigned a set of values in memory 96 corresponding to a decrement factor (1~yen), where n=O to N-1.

After the decrement memory 96 has been loaded, the microprocessor controls mode selector 108 to disable 100, 102 and 106, enable latch 98 and switch multiplexer 104 to supply the decrement memory higher order address AH from the counter 105.

The operation of the signal amplitude accumulator subsequently proceeds similarly to that described for the real processing channel of the device 10 of Fig. 1. The circuit timing will therefore not be described in detail. As the counter 105 counts from 0 to 2N~1, each location in register 92 becomes updated and decremented during each sample interval. There are however three differences. Firstly, each location is associated with its own decrement factor (1~en), and accordingly the bandwidths Af=2enfmax/r associated with the simulated filter centre frequencies need not be equal. A signal spectrum may accordingly be analysed by filters which are broadband in some regions and narrowband in others. Furthermore, the bandwidth is variable or agile.The microprocessor 112 may be employed to change the contents of the decrement memory 96 and reconfigure filter bandwidths as required. The second difference arises from the use of B-l register higher order bits for incrementing and the I lower order bits for decrementing, where B-l need not be equal to I. B-l may be made large enough to avoid overflow at adder 94, and I large enough to implement very small decrement factors. Thirdly, only the B-H higher order output bits from the register 92 are read by the microprocessor 112, where H is not necessarily equal to I. The reason for this is that the H lower order bits of the register output decorrelate between successive input signal samples, and provide no useful information.These bits are accordingly ignored to reduce the capacity required in subsequent signal processing.

Referring now to Fig. 8, there is shown a function memory 120 arranged to replace the memory 22 in Fig. 1 and provide frequency and/or function agility or variation. The function memory 120 comprises a random access memory or RAM 122 addressed via a multiplexer 124 either by a clock-driven counter 126 or by a microprocessor 128. The multiplexer has a switch signal input SW connected to a mode selector 130, which also controls read/write and write enable inputs R/W and WE of the RAM 122. The microprocessor 128 controls both the mode selector 130 and input to the RAM 122 via an input/output port l/O two bits wide.

Functions are loaded into the RAM 122 by switching the multiplexer 124 to allow the microprocessor 128 to control the RAM address. The R/W and WE RAM inputs are appropriately pulsed, and the microprocessor cycles through RAM addresses assigning them appropriate function values. When the RAM address space has been filled with function values, the R/W input is pulsed high and the multiplexer 124 is switched to allow RAM address control by the counter 126. The RAM l/O port then provides a two bit output for successive pairs of one-bit multiplications at multipliers such as 20R and 201 in Fig. 1. The function memory 120 is however programmable, ie the function set may be changed. This allows for example adaptive spectral analysis. A first spectral analysis may be performed employing broadband functions equispaced in frequency in the band of interest.A second spectral analysis may then be performed with narrowband, narrowly spaced functions concentrated in a particular region of the band of interest. This requires a combination of the apparatus shown in Fig. 7 and 8 together with the equivalent of the co-operating parts of Fig. 1.

As an alternative to the use of a memory 22 or 120 to store transform functions, the functions may be synthesised electronically from clock signals. Frequency synthesis from clock signals is well known in digital electronics and will not be described.

Whereas the invention has been described in terms of application of a decrement factor to produce an exponential time window on a signal spectrum, it is possible to employ a different form of window or even to dispense with the window entirely. If no window if employed, the invention simulates a bank of filters of inifinitely narrow bandwidth or infinite Q. As signal sampling proceeds, the spectrum or register contents build up without limit. This requires the register to be read and reset periodically before overflow, which corresponds to a time window of constant amplitude with an abrupt cut-off. Alternatively, the contents of decrement memories 28R and 281 or 96 may be arranged to generate other window functions.

Claims (12)

1. A signal transforming device for transforming a signal, the device including sampling means arranged to sample the signal sufficiently to define it, and a signal processing channel including both multiplying means for multiplying each signal sample by a respective value of every function in a function set to produce function amplitude contributions and accumulating means for accumulating function amplitude contributions to provide a signal spectrum in terms of coefficients of the function set.

2. A device according to Claim 1 wherein the signal processing channel includes means for applying a time window function to accumulating amplitude contributions.

3. A device according to Claim 2 wherein the signal processing channel includes means for decrementing the accumulating amplitude contributions to implement an exponential time window.

4. A device according to Claim 1, 2 or 3 wherein the set of functions comprises the digital equivalents of circular functions each having a respective frequency.

5. A device according to any preceding claim having two signal processing channels arranged to produce real and imaginary spectrum amplitude coefficients.

6. A device according to any preceding claim wherein the or each signal processing channel contains accumulating means including an adder arranged to receive input from the multiplying means and to provide an output to an amplitude storage device having a respective storage location for each of the set of functions, and a decrementing device arranged to receive input from the amplitude storage device and to provide output divided between the adder and the amplitude storage device, the arrangement being such that amplitude contributions to a respective function accumulate in each storage location to produce values which are both fractionally decremented and reduced in the decrementing device as appropriate to implement exponential decay of storage location contents and their increase or decrease in response to higher or lower magnitude signals from the multiplying means.

7. A device according to Claim 6 wherein the decrementing device is programmable and is arranged to implement a respective decrement factor for the contents of each location in the amplitude storage device.

8. A device according to any preceding claim wherein the or each multiplying means includes a function storage device for storing function values, the storing device being addressed by a clock activated counter device arranged to select each location in the amplitude storage device to receive contributions comprising products involving values of a respective function.

9. A device according to Claim 8 wherein the function storage device is arranged to have programmable contents.

10. A device according to any preceding claim including means for obtaining a power spectrum from accumulated amplitude contributions.

11. A device according to Claim 10 wherein the means for obtaining a power spectrum is arranged to identify at least the highest intensity spectral component.

12. A signal transforming device substantially as herein described with reference to the accompanying Figs. 1 to 4, or with reference to those drawings as modified in accordance with Fig. 7 and/or 8.