GB2185327A - A method of testing an electrical chip - Google Patents

Abstract

A method of testing an electrical chip during manufacture of the chip comprises testing the chip at a metal contact stage and a metallization stage, the testing comprising 1 aligning one or more test beams on the metal surfaces for establishing appropriate electrical continuity in each and every surface layer, and 2 aligning one or more of the test beams on transistors in the chip to establish the presence or absence of physical faults in the transistors, the test beams being such that they are able to sustain a measurable electrical current. The electrical current or a value thereof in the test beams is measured on input and output to provide an indication of the electrical continuity or the physical faults in the transistors. The beams may be electron, laser or alpha particle beams. In Figure 6, metal contacts are marked as small dots. <IMAGE>

Description

SPECIFICATION A method oftesting an electrical chip This invention relates to a method oftesting an electrical chip.

The provision of integrated circuits on electrical chips is well known. As is also well known, the manufacture ofthe chips involvesthe deposition ina predetermined layout of a diffusion material, a diffusion implant, polysilicon and a metal, all on a substrate such for example as pure silicon. The various materials are deposited using carefully controlled masking processes. The entire masking processes may involve the provision of perhaps five or six stageswhich are called levels. The particulartype of material laid down during the manufacture of a chip has to be consistent with the level involved. There are only one ortwotypes of material usually laid down at each level of masking. Different types of masks are used at each level.Correct alignment of the masks is usually effected underthe control of a computer. Electrical contact between the materials laid down and between different levels is achieved by contacts such for example as through contacts or buried contacts.

Itwill be seen from the above that the manufacture ofthe chips is a complex business and manufacturing problems during the various stages of the manufacture ofthe chips often result in circuit breaks, meaning thatthefinally produced chip is defective.

It is an aim ofthe present invention to provide a method oftesting the chips which enables defective chips simply and easily to be detected at an early stage in their manufacture.

Accordingly, this invention provides a method of testing an electrical chip during manufacture ofthe chip, which method comprises testing the chip at a metal contact stage and a metallization stage in the manufacture of the chip, the testing comprising (1 ) an electrical continuitytest comprising aligning one or more test beams on the metal surfaces for establishing appropriate electrical continuity in each and every surface layer, and (2) a transistor action test comprising aligning one or more ofthe test beams on transistors in the chip to establish the presence or absence of physical faults in the transistors, the test beams being such thatthey are able to sustain a measurable electrical current, and the method being such that the electrical currentora valuethereofinthetest beams is measured on input and output to provide an indication ofthe electrical continuity orthe physical faults in thetransistors.

The amount of electrical current in the test beams is very small. The precise amountofelectri- cal current is determined by the focus of the test beams. Generally,thesmallerthefocus,thenthe less currentthetest beams will carry. Generally, the current carried by the test beams may be from 0.01 micro-amps to 10 micro-amps.

The test beams are non-destructive and they do not impose any mechanical loading on the chips.

In testing the action ofthetransistors, the current voltage potentials will usually be established on all bus layers and input contacts, and the correct output potentials will then need to be observed on a 11 the transistor output contacts in order to establish that there are none of the physical faults present.

The metal surfaces may be metal contacts or metal lines.

The method ofthe invention enables the electrical continuity to be tested as early as possible during the manufacture of the chips and this may be effective to reduce considerably production and other related costs. Electric or electro-optic continuity between test beams and relevant layers may be established, without the intermediate use of metal contacts, using surface waves.

Thus continuity tests may be carried out after each and every level of masking, including the first level. At low levels of masking, process defects would clearly be located at very early stages in the overall manufacture of the chips. If desired, the test- ing can be left until that stage of the chip manufacture when the metal contacts are laid down and in this case the electrical contact will be between the test beams and the relevant layers by means of the metal contacts. The method of the invention lends itself very well to providing any desired number of electrical continuity tests in parallel. All that is required is an appropriate number of parallel test beams.

Preferably, the method of the invention is such that switching ofthetest beams is done automatically.

Preferably, the automatic switching ofthetest beams is done in a programmed sequence. This programmed sequential switching may be effected in a variety of ways, for example using an appropriate computer program.

The method ofthe invention may be one in which the electrical cu rrent or a va I ue thereof in the test beams is measured on input and output by a logic level analyserwhich detects unacceptable voltages which do not correspond to defined expected logic levels. It will be appreciated that the electrical current, the voltage or other appropriate parameters can be measured to give indica tionsoftheinputand outputcurrentsinthetest beams.

The test beams may be electron beams, laser beams, or alpha particle beams. Where such beams are employed, they may be used with focussing down to 0.1 micron. If electron beams are employed in a voltage contrast mode, then electronic alignment may be possiblewithoutthe inherent loading imposed by a mechanical probe.

The chips tested using the method ofthe present invention may be any desired known type of chipssuchforexampleasthoseknown as silicon chips, silicon-on-sapphire chips, and gallium arsenide chips. The method of the invention may also be used to test hybrid chips which use organic molecular layers.

The metal employed in the chips will usually be aluminium but other metals such for example as gold may be used if desired.

An embodiment of the invention will now be described solely byway of example and with reference to the accompanying drawings in which: Figure 1 illustrates some masking steps in the method of manufacturing an integrated circuit chip; Figure2 shows the masking steps required for pro- ducing a typical CMOS gate array; Figure3showsthe mask sequence for NMOS; Figure4showsthevariouslevelsforthe NMOSas shown in Figure 3, superimposed one upon the other; Figure 5shows a layout of a simple NMOS inverter; and Figure 6shows the metal contacts in a stick diagram for a sequence detector.

Referring to Figure 1 ,there is illustrated known masking steps in the production of an integrated circuit silicon chip. Starting atthetop of Figure 1, it will be seen that a silicon slice 2 is provided with a thin silicon dioxide layer 4. The silicon dioxide layer 4 is coated with a layerof photoresist 6. The layer of photoresist 6 is exposed to ultra-violet light8through a photo mask 10.

Unexposed photoresist 6 is removed in the areas 12.

The silicon dioxide layer 4 is etched away also in the areas 12 using photoresist as a barrier.

Appropriate impurities are diffused or implanted in the areas 14 and then the silicon dioxide layer4 is regrown in the areas 12 to coverthe otherwise exposed surfaces ofthe silicon slice 2. During the production, if the photo mask loins laterally mis-alig ned, then the silicon dioxide layer is etched in the wrong places, thereby rendering thefinished chip useless.

Referring now to Figure 2, there are shown in a self-explanatory mannerthe masking steps required for a typical CMOS gate array process. It will be noted that the metal contact stage and the metallization stage occurtowards the end ofthe process.

Figure3 shows in six parts the mask sequence for the production of a NMOS device (4:1 ratioed inverterwith a buried contact). Figure 3(a) shows mask level 1, diffusion. Figure 3(b) shows mask level 2, depletion implant. Figure 3(c) shows mask level BC, buried contacts. Figure 3(d) shows mask level 3, polysilicon. Figure 3(e) shows mask level 4, contacts. Figure 3(f) shows mask levelS, metal.

Referring now to Figure 4, there is shown in an overlaid mannerthevarious mask levels illustrated in Figure 3. In Figure 4 it will be seen that there is a buried contact 16, a depletion implant 18, and polysilicon layers 20 and 22. The contacts are shown as contacts 24, 26. The input and output are as illustrated together with the drains, gates and sources.

Figure 5 is similarto Figure 4 as can be seenfrom the key provided on the left side of Figure 5.

The top parts of Figure 5 ill ustrate the electrical con- nection paths and the contacts in side on fashion.

All ofthe integrated circuit chips andtheirmanufac- ture illustrated in Figures 1 to 5 are known.

The method oftesting of the present invention can be used with any ofthe illustrated chips. More specifically, the method of testing will com prise test- ing the chips atthe metal contact stage and the metallization stage in the manufacture ofthe chips.The testing will comprise (1) an electrical continuity test comprising aligning one or more test beams onthe metal surfaces forestablishing appropriate electrical continuity in each and every layer between contacts, and (2) a transistor action test comprising aligning one or more ofthe test beams on transistors inthe chipsto establish the presence or absence of physical faults in the transistors. The test beams will be such thatthey are able to sustain a measurable electrical current.The method will be such that the electrical current, or a valuethereof, inthetest beams will be measured on input and outputto provide an indication ofthe electrical continuity orthe physical faults in the transistors.

The switching ofthe test beams will be done in a programmed sequence using an appropriate programmed computer (not shown).

The electrical current or a value thereof in the test beamswill be measured on input and output by a logic level analyser (not shown). The logic level analyserwill detect u naccepta ble vo Itag es which do not correspond to defined expected logic levels.

The test beams will usually be an electron beam, a laser beam, or an alpha particle beam.

Figure 6 illustrates how, during the metal contact level of masking, particletestbeam guns are aligned above metal contacts. The metal contacts are shown in Figure 5 as the various small dots.

Preferably, the particle test beam guns will be driven directly from a computer aided design database containing the required topological layout data. Metal contacts may serve as inter-or intra-layer connections.

It is to be appreciated that the embodiment ofthe invention described above has been given by way of example only and that modifications may be effected. Thus, for example, the integrated circuits may be on a base otherthan a silicon base.

They may thus be on a silicon-on-sapphire base oron a gallium arsenide base. The chips tested by the method ofthe present invention may also be hybrid chips which use organic molecular layers. Although the illustrated metal for the contacts has been shown to be aluminium, other metals such for example as gold may be em ployedifdesired. In addition, thetest beams may be driven in a modulated fashion to facilitate the appropriate test or tests, i.e. it may be necessary to superimpose information in the beams.

Also metal lines may be considered to be thin films on a dielectric material in the case of gallium arsenide technology. Continuity may of course be tested in such lines using the beam methods described above.

Claims (1)

1. A method of testing an electrical chip during manufacture ofthe chip, which method comprises testing the chip ata metal contact stage and a metallization stage in the manufacture ofthe chip,thetesting comprising (1) an electrical continuity test comprising aligning one or more test beams on the metal surfaces for establishing appropriate electrical continuity in each and every surface layer, and (2) a transistor action test comprising aligning one or more ofthe test beams on transistors in the chip to establish the presence or absence of physical faults in the transistors, thetest beams being such that they are able to sustain a measurable electrical current, and the method being such that the electrical currentora value thereof in the test beams is measured on input and outputto provide an indication of the electrical continuity orthe physical faults in the transistors.

2. A method according to claim 1 in which the metal surfaces are metal contacts or metal lines.

3. A method according to claim 1 orclaim 2 in which the current carried bythetest beams is from 0.01 micro-ampsto 10 micro-amps.

4. A method according to any one ofthe preceding claims in which, in the transistor action test, the current voltage potentials are established on all bus layers and input contacts, and the correct output potentials are then observed on all the transistor output contacts in order to establish that there are none of the physical faults present.

5. A method according to any one ofthe preceding claims in which switching ofthetest beams is done automatically.

6. A method according to claim 5 in which the automatic switching of the test beams is done in a programmed sequence.

7. A method according to any one of the preceding claims in which the electrical current or a value thereof in the test beams is measured on input and output by a logic level analyser which detects unacceptable voltages which do not correspond to defined expected logic levels.

8. A method according to any one ofthe preceding claims in which the test beams are electron beams, laser beams, or alpha particle beams.

9. A method according to claim 8 in which the test beams are used with focusing down to 0.1 micron.

10. A method according to any one ofthe preceding claims in which the chip is a silicon chip, a silicon-on-sapphire chip, or a gallium arsenide chip.

11. A method according to any one ofthe preceding claims in which the metal employed on the chip is aluminium or gold.

13. A method oftesting an electrical chip during manufacture ofthe chip according to claim 1 and substantially as herein described with reference to the accompanying drawings.