GB2183907A - Reducing radiation effects on integrated circuits - Google Patents
Reducing radiation effects on integrated circuits Download PDFInfo
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- GB2183907A GB2183907A GB08627267A GB8627267A GB2183907A GB 2183907 A GB2183907 A GB 2183907A GB 08627267 A GB08627267 A GB 08627267A GB 8627267 A GB8627267 A GB 8627267A GB 2183907 A GB2183907 A GB 2183907A
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- 230000000191 radiation effect Effects 0.000 title description 3
- 239000000758 substrate Substances 0.000 claims abstract description 117
- 239000004065 semiconductor Substances 0.000 claims abstract description 103
- 239000002019 doping agent Substances 0.000 claims abstract description 45
- 238000009792 diffusion process Methods 0.000 claims abstract description 34
- 230000005855 radiation Effects 0.000 claims abstract description 21
- 230000004044 response Effects 0.000 claims abstract description 7
- 230000000694 effects Effects 0.000 claims abstract description 5
- 239000000463 material Substances 0.000 claims description 47
- 238000002955 isolation Methods 0.000 claims description 46
- 238000000034 method Methods 0.000 claims description 11
- 238000004519 manufacturing process Methods 0.000 claims description 9
- 230000006335 response to radiation Effects 0.000 claims description 2
- 230000003247 decreasing effect Effects 0.000 abstract description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 22
- 108091006146 Channels Proteins 0.000 description 20
- 239000000969 carrier Substances 0.000 description 12
- 235000012239 silicon dioxide Nutrition 0.000 description 11
- 239000000377 silicon dioxide Substances 0.000 description 11
- 229910052710 silicon Inorganic materials 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 230000008569 process Effects 0.000 description 6
- 230000015556 catabolic process Effects 0.000 description 5
- ZXEYZECDXFPJRJ-UHFFFAOYSA-N $l^{3}-silane;platinum Chemical compound [SiH3].[Pt] ZXEYZECDXFPJRJ-UHFFFAOYSA-N 0.000 description 3
- 239000012777 electrically insulating material Substances 0.000 description 3
- 230000005251 gamma ray Effects 0.000 description 3
- 229910021339 platinum silicide Inorganic materials 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 239000000615 nonconductor Substances 0.000 description 2
- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- 230000035945 sensitivity Effects 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000005513 bias potential Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000005389 semiconductor device fabrication Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/761—PN junctions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0214—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L
- H01L27/0229—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L of bipolar structures
- H01L27/0233—Integrated injection logic structures [I2L]
- H01L27/0237—Integrated injection logic structures [I2L] using vertical injector structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/082—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only
- H01L27/0821—Combination of lateral and vertical transistors only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Element Separation (AREA)
- Bipolar Integrated Circuits (AREA)
Abstract
A semiconductor structure 100 has a bulk semiconductor substrate 112 having a first-type conductivity in a first dopant concentration, on which is epitaxially formed a first semiconductor layer 113 having a first-type conductivity but in a second dopant concentration lower than the first concentration, on which is epitaxially formed a second semiconductor layer 114 having a second-type conductivity opposite to the first-type conductivity and thereby forming a P-N junction with the first layer 113. The thickness of the first layer 113 is greater than the diffusion lengths of electron-hole pairs emitted by the bulk substrate 112 in response to incident radiation so that electron-hole pairs emitted by the substrate 112 are substantially prevented from reaching the P-N junction between the first and second layers 113 and 114, and few electron-hole pairs are emitted by the first layer 113, due to its small thickness, thereby decreasing the effects of incident radiation on active devices formed in the semiconductor structure 100. <IMAGE>
Description
SPECIFICATION
Semiconductor device
This invention relates generally to semiconductor structures and more particularly to semiconductor structures having reversed-biased junctions to provide isolation between active devices and which are adapted to operate in a radiation environment.
As is known in the art, one technique used to form an integrated circuit is to provide a semiconductor substrate with an epitaxial layer grown thereon, the substrate and the epitaxial having opposite-type conductivities. The substrate is moderately doped to provide a suitable breakdown voltage for active devices formed in the epitaxial layer. Active devices formed in the epitaxial layer are typically electrically isolated from one another by isolation regions extending vertically through the epitaxial layer to the substrate. Such isolation regions may comprise semiconductor material having the same conductivity type as that of the substrate. Alternately, the isolation regions may further comprise an electrical insulator disposed on semiconductor material of the same conductivity type as the substrate.Electrical isolation is achieved by applying a reverse-bias between the substrate and the epitaxial layer.
With such type of isolation, however, when the structure is exposed to radiation, such as x-ray or gamma ray radiation, electron-hole pairs (i.e. majority and minority carriers) having relatively long lifetimes and diffusion lengths are generated in the moderately-doped substrate material. Those relatively-long-diffusionlength carriers which reach the reverse-biased junction between the substrate and the epitaxial layer produce an electrical current which, in addition to the reverse-bias leakage current produced at such reverse-biased junction, reduces the electrical isolation between active devices formed on different regions of the epitexial layer.Such increased current at such reverse-biased junction also may produce "logic upset", that is, slight conduction of an "OFF" active device in an amount sufficient to prevent an "ON" active device coupled thereto from further conducting, thus turning such device "OFF".
One technique used to reduce the effect of radiation is to use a dielectric material as the substrate. One such material is sapphire, a relatively expensive material, on which it may be difficult to form an epitaxial layer. Another is polycrystaline-silicon, with a silicon epitaxial layer. Generally, however, there are manufacturing difficulties with using an insulating substrate.
In accordance with the present invention, a semiconductor structure is provided comprising: a substrate of semiconductor material having a first-type doping conductivity; a first layer of semiconductor material epitaxially formed on the substrate, such first layer having the first-type doping conductivity; and, a second layer of semiconductor material epitaxially formed on the first layer, such second layer having a second-type doping conductivity opposite to the first-type doping conductivity.
The first layer and the second layer form a P
N junction, which is typically reverse biased to provide isolation between devices formed in such semiconductor structure. The concentration of dopant in the first layer is less than that in the substrate, and the thickness of the first layer is selected to be greater than the diffusion length of electron-hole pairs (i.e. majority and minority carriers) emitted by the substrate in response to incident radiation and substantially less than the substrate thickness.
With such arrangement, the number of radiation-produced carriers which reach the P-N junction between the first and second layers and contribute to the reverse-bias leakage current at such junction is greatly reduced, thereby decreasing the effects of incident radiation on the isolation between active devices formed in the second layer.
In a preferred embodiment of the present invention, means, formed in the second layer, are further included for providing additional electrical isolation between active devices formed in different regions of the second layer of semiconductor material. In one embodiment, such means comprises a region comprising semiconductor material having the firsttype doping conductivity, the region being disposed through the thickness of the second layer and extending a predetermined distance into the first layer, thereby forming a reversebiased junction between said region and the second layer. In another embodiment, the region further comprises electrically insulating material, such as silicon dioxide.
The present invention also provides a method of fabricating a semiconductor structure, comprising the steps of: providing a substrate of semiconductor material having a firsttype doping conductivity; epitaxially forming on the substrate a first layer of semiconductor material having the first-type doping conductivity in a concentration lower than a concentration of dopant in the substrate; and, epitaxially forming on the first layer a second layer of semiconductor material having a second-type doping conductivity opposite the first-type doping conductivity.
Brief Description of the Drawings
The foregoing features of the present invention and the advantages thereof may be fully understood from the following detailed description read in conjunction with the accompanying drawings wherein:
FIG. 1A is a cross-sectional view of a semiconductor device structure of the prior art;
FIG. 1B is a cross-sectional view of the semiconductor device structure of the present invention;
FIG. 1C is a schematic diagram of the semiconductor structures of FIG. 1A and FIG. 1B; and
FIG. 2 is a cross-sectional view of a second embodiment of the semiconductor device structure of the present invention.
Description of the Preferred Embodiments
Referring now to FIG. 1A, shown is a crosssection of a semiconductor device structure 10 of the prior art implementing the ISL (integrated Schottky logic) circuit shown schematically in FIG. 1C. The fabrication process for structure 10 is described in detail in U.S. Patent No. 4,512,076, entitled "Semiconductor
Device Fabrication Process" and assigned to the present assignee. Semiconductor structure 10 comprises bulk substrate 12, here comprising p-type silicon having a surface in the #100 > crystalgraphic plane and a resistivity of about 2 ohm-cm. Bulk substrate 12 is of conventional thickness, here approximately 450-640 micrometers (z m) depending on the diameter of the wafer in which structure 10 is embodied.Epitaxial layer 14 of n-type conductivity silicon is grown in a conventional manner over the upper surface of bulk substrate 12, and nt-type subcollector region 16 is formed by diffusion and is disposed as shown in an upper region of substrate 12 and a lower region of epitaxial layer 14. Here, n-type epitaxial layer is 2.7 to 3.3 micrometers (zm) thick and has a resistivity of between 0.25 and 0.35 ohm-cm. A pair of p-type conductivity isolation channels 18 are formed in epitaxial layer 14 by diffusing suitable p-type conductivity dopant into epitaxial layer 14. A pair of p-type conductivity regions 20, 22 are formed by diffusion in epitaxial layer 14 and driven by heat to a predetermined depth in epitaxial layer 14, as described in the aboveidentified patent.It is noted that p-diffusion region 20 extends both into epitaxial layer 14 and isolation channel 18, as discussed in a article entitled, "ISL, A Fast and Dense Low
Power Logic, Made in a Standard Schottky
Process", by jan Lohstroh and published in the IEEE Journal of Solid State Circuits, Vol.
SC-14, No. 3, June 1979, pages 585-590.
An n'-type conductivity emitter region 24 is diffused into p-diffusion region 22. Schottky contact layers 26a, 26b, here comprising platinum silicide, are formed in surface regions of epitaxial layer 14 in the manner described in the above-identified patent. It is noted that during the above-described fabrication process, several insulating layers 27a, 27b, 27c, 27d are formed over the upper surface of epitaxial layer 14. The formation of such insulating layers is fully described in the above-identified U.S. Patent No. 4,512,076. Here, layers 27a, 27b and 27d comprise silicon dioxide, while layer 27c comprises silicon nitride. Suitable metal contact electrodes 28, 30, 32a, 32b are provided in any conventional manner to provide the ISL circuit 11 shown in FIG.
1C. It is noted that base contact electrode 28 provides the input to the ISL gate and that emitter contact electrode 30 is adapted for coupling to ground, as shown in FIG. 1C. The
Schottky platinum silicide regions 26a, 26b provide, together with output electrodes 32a, 32b, a pair of Schottky diodes, 34a, 34b, the anodes therof being coupled to such output electrodes 32a, 32b, as shown.
In operation, a bias potential is typically applied to p-type conductivity substrate 12 by means not shown, such bias being sufficient to produce a reverse-bias at the P-N junction between substrate 12 and n-type conductivity epitaxial layer 14 and at the P-N junction between p-type conductivity isolation channels 18 (in electrical contact with substrate 12) and epitaxial layer 14. The reversebiased junction between substrate 12 and epitaxial layer 14 provides vertical electrical isolation between ISL circuit 11 and other devices, such as adjacent ISL circuits, formed on substrate 12, and the reverse-biased junction between channels 18 and epitaxial layer 14 provides horizontal electrical isolation between ISL circuit 11 and such other devices.As is known, however, a certain amount of reversebias leakage current unavoidably flows at such reverse biased junctions, leading to decreased isolation between active devices formed on substrate 12, such as adjacent ISL circuits. As is also known, when semiconductor structure 10 is exposed to radiation, such as x-ray or gamma ray radiation, electron-hole pairs are generated in the moderately-doped (e.g. 2 ohm-cm-resistivity) substrate 12. Those electron-hole pairs which are generated within one diffusion length of the reverse-biased vertical and horizontal P-N isolation junctions add to the above-discussed reverse-bias leakage current, thus further reducing the electrical isolation between active devices, such as adjacent
ISL circuits, formed on substrate 12. Such increased reversebias leakage current may become large enough to produce "logic upset", that is, slight conduction of an "OFF" (i.e.
otherwise nonconducting) active device in an amount sufficient to prevent an "ON" (i.e.
otherwise conducting) active device coupled thereto from further conducting, thus turning such device "OFF".
Referring now to FIG. 1B, the semiconductor device structure 100 of the present invention is shown. Semiconductor device structure 100 solves the above-identified radiationinduced problems by providing: a bulk substrate 112 having a very high dopant concentration of a first-type dopant conductivity (here, of p-type dopant) and hence a very low resistivity (here, on the order of 0.01 ohm-cm); and, a pair of epitaxial layers 113, 114, first epitaxial layer 113 having the same first-type dopant con ductivity (here, p-type) as bulk substrate 112, but having a much lower dopant concentration and hence a resistivity greater, here on the order of two orders of magnitude greater, than that of substrate 112. The second epitaxial layer 114 has a second-type dopant conductivity opposite that of the first-type dopant conductivity (here, n-type).An active circuit, such as ISL circuit 11 (FIG. 1C) is then formed over first epitaxial layer 113, rather than directly over bulk substrate 112, by a suitable process, such as that described briefly above and in detail in the above-identified U.S.
Patent No. 4,512,076. First epitaxial layer 113 has a thickness selected to be as small as possible while still providing sufficient breakdown voltage for active devices formed in second epitaxial layer 114 and being thicker than the diffusion length of electron-hole pairs emitted by substrate 112 in response to incident radiation, as will be described.
Referring with more particularity to FIG. 1B, bulk substrate 112 comprises highly doped (here, with p-type dopant) silicon having a resistivity on the order of 0.01 ohm-cm. It is noted that the resistivity of substrate 112 is two orders of magnitude less than the resistivity of prior art substrate 12 (FIG. 1A). Bulk substrate 112 is of conventional thickness, such thickness here being about 450 to 640 tm, depending on the diameter of the wafer embodying structure 100 (as per SEMI standards). Grown over substrate 112 is first epitaxial layer 113 of the same type dopant conductivity as substrate 112 (here, p-type) but having a significantly lower dopant concentration than substrate 112. Here, the dopant concentration of first epitaxial layer 113 is selected to yield a resistivity of about 2 ohm-cm for such layer 113.It has been found that a resistivity of 2 ohm-cm for first epitaxial layer 113 optimizes the structure of the vertical
PNP transistor included in ISL circuit 11. Different resistivities may be used for devices other than ISL devices formed on semiconductor body 100. It is noted that the resistivity of first epitaxial layer 113 is of the same order of magnitude as the resistivity of bulk substrate 12 (FIG. 1A) of prior art semiconductor device structure 10. First epitaxial layer 113 here has a thickness of between 10 and 12 micrometers brum), although the precise thickness of first epitaxial layer 113 may be varied depending on the application, as will be discussed. It is noted that the selected thickness of first epitaxial layer 113 is much less than that of bulk substrate 112.
Grown over first epitaxial layer 113 in a conventional manner is second epitaxial layer 114, such second epitaxial layer 114 having a second-type dopant conductivity (here ntype) oppposite to that of first epitaxial layer 113 and bulk substrate 112. Second epitaxial layer 114 is substantially equivalent in dopant concentration end thickness to epitaxial layer 14 (FIG. 1A) of prior art structure 10. Thus, here second epitaxial layer 114 is approximately 2.7 to 3.3 m thick and has a resistivity of about 0.25 to 0.5 ohm-cm. It is understood that if other than ISL circuitry is formed on body 100, second epitaxial layer 114 may be given a different thickness and dopant concentration (and hence resistivity).Subcollector region 116, here an nt-type diffusion region, is formed in a well-known manner in an upper portion of first epitaxial layer 113 and a lower portion of second epitaxial layer 114, as shown. Isolation channels 118, here comprising highly doped p±type diffusion regions, are formed as described above in second epitaxial layer 114. Here, such isolation regions 118 extend from the upper surface of second epitaxial layer 114 through such layer 114 and into upper regions of first epitaxial layer 113 by a predetermined amount. Such intrusion is made in order to compensate for small, unavoidable variations in the thickness of second epitaxial layer 114. That is, second epitaxial layer 114 may, when formed, be thicker in some regions than in others by a small amount.By extending isolation regions 118 deeper than the nominal thickness of second epitaxial layer 114, assurance is made that such p -type isolation channels 118 reach ptype first epitaxial layer 113. If channels 118 were not to reach first epitaxial layer 113 (or to just barely contact it), the leakage current at the reverse-biased P-N junctions formed by isolation channels 118 and first epitaxial layer 113 with second epitaxial layer 114 would be increased, thereby reducing the threshold of such P-N junctions and decreasing the vertical and horizontal electrical isolation provided by such reverse-biased junctions. Here, the depth of intrusion of isolation channels 118 into first epitaxial layer 113 is selected to be 10% to 20% of the thickness of such layer 113.
The remainder of ISL circuit 11 (FIG. 1C) is formed in n-type second epitaxial layer 114 in substantially the same fashion as such circuit is formed in epitaxial layer 14 (FIG. 1A) of prior art structure 10 and as described above.
Thus, p-type diffusion regions 120, 122 are formed in second epitaxial layer 114 and driven to a predetermined depth therein by heating structure 100. Again, it is noted that p-type base diffusion region 120 extends into both second epitaxial layer 114 and isolation channel 118. The n -type emitter region 124 is diffused into p-diffusion region 122.
Schottky contact layers 126a, 126b, here comprising platinum silicide, are formed in upper surface regions of second epitaxial layer 114 in the manner described in the aboveidentified U.S. Patent No. 4,512,076. Insulating layers 127a, 127b, 127c, 127d are formed during fabrication of semiconductor device structure 100, as discussed above.
Here, layers 127a, 127b and 127d comprise silicon dioxide, while layer 1 27c comprises sil icon nitride. Metal contact electrodes 28, 30, 32a, 32b (so numbered to be consistent with
FIG. 1C) are formed to provide the ISL circuit 11 shown in FIG. 1C.
The ISL circuit 11 provided by semiconductor device structure 100 is substantially electrically equivalent to that provided by prior art semiconductor device structure 10 (FIG. 1A).
As stated, the thickness of second epitaxial layer 114 is here selected to be 2.7-3.3 im, but such thickness may be varied depending on the application of semiconductor device structure 100. Second epitaxial layer 114 must be maintained sufficiently thick, however, to provide space for depletion widths associated with a reverse-biased collector (such as the collector region formed by second epitaxial layer 114 between isolation channels 118) and subcollector (such as subcollector 116) of an active device formed over such second epitaxial layer 114.
In operation, when semiconductor device structure 100 is exposed to radiation, such as x-ray or gamma ray radiation, the total amount of electron-hole pair current generated in semiconductor device structure 100 is substantially reduced over the amount of electron-hole pair current generated in prior art structure 10 (FIG. 1A). Such reduction is in part due to heavily doping bulk substrate 112 to have a resistivity much lower than that of bulk substrates of the prior art, such as substrate 12 of FIG. 1A. Here, bulk substrate 112 is heavily doped with pt-type dopant to have a resistivity of approximately 0.01 ohm-cm. This is to be compared with prior art substrate 12, which has a resistivity on the order of 2 ohmcm resulting from lighter doping.The heavy doping of bulk substrate 112 reduces both the lifetime and the diffusion length of electron-hole pairs (i.e., the minority and majority carriers, respectively in p±type substrate 112) emitted by substrate 112 in response to radiation incident on substrate 112. For example, minority carrier lifetime in the heavily-doped, 0.01 ohm-cm resisitivity substrate 112 is 6 x 10 9 seconds, much shorter than the 3.4 x 10 6 seconds minority carrier lifetime in moderately-doped substrates having a resistivity on the order of 2 ohm-cm, such as substrate 12 of prior art structure 10 (FIG. 1A). To put it another way, the recombination rate of separated (for example by incident radiation) electron-hole pairs is much higher in substrate 112 than in prior art substrate 12, due to the lower minority carrier lifetime of the former.
Additionally, minority carrier diffusion length in heavily-doped, 0.01 ohm-cm resistivity substrate 112 is approximately 1.5 ,um, as opposed to a diffusion length of approximately 98 ,am for minority carriers in moderatelydoped, 2 ohm-cm resistivity prior art substrate 12. Since the thickness of first epitaxial layer 113 here is selected to be between 10 ,um and 12 Am, few, if any, of the carriers emitted by substrate 112 can reach the reverse biased P-N isolation junctions of semiconductor body 100.A little thought reveals that the reverse-biased P-N isolation junctions of semiconductor body 100 comprise the junctions between: (1) first epitaxial layer 113 and second epitaxial layer 114; (2) first epitaxial layer 113 and subcollector region 116; and (3) isolation channels 118 and second epitaxial layer 114. Reverse-biased junctions (1) and (2) provide vertical electrical isolation for the devices of ISL circuit 11 from adjacent devices formed on semiconductor body 100, while reversebiased junction (3) provides horizontal electrical isolation for ISL circuit 11 from such adjacent devices.Therefore, the majority and minority carriers which are emitted by highlydoped substrate 112 are substantially prevented from reaching such reverse-biased junctions, since, as discussed below, the thickness of first epitaxial layer 113 is selected to be greater than the relatively short diffusion length of such carriers emitted by such substrate 112.
As discussed, first epitaxial layer 113 is doped with the same type conductivity dopant (here, p-type) as bulk substrate 112 but with a lower concentration thereof to provide a resistivity for first epitaxial layer 113 of about 2 ohm-cm. First epitaxial layer 113 provides a region of sufficiently lightly doped material (and thus of sufficient resistivity) to minimize incremental collector junction capacitance of transistors formed in structure 100 while providing sufficient breakdown voltages for such transistors.First epitaxial layer 113, being moderately doped, will emit in response to incident radiation electron-hole pairs (i.e. minority and majority carriers in p-type layer 113) having relatively long lifetimes (approximately 3.4 x 10 6 sec.) and diffusion lengths (about 98 Am) as compared to the electronhole pairs emitted by highly-doped bulk substrate 112. However, the thickness of first epitaxial layer 113 is selected to be substantially smaller than that of substrate 112 yet larger than the diffusion length of electron-hole pairs emitted by bulk substrate 112 and of sufficient thickness to provide sufficient breakdown voltage for active devices formed in second epitaxial layer 114. Here, the thickness of first epitaxial layer is 113 selected to be between 10 ,am and 12 #m. Therefore, the available volume of relatively moderatelydoped, high resistivity (i.e. 2 ohm-cm) material present in structure 100 is quite small. To put it another way, while electron-hole pairs generated in first epitaxial layer 113 in response to incident radiation will have sufficiently long lifetimes and diffusion lengths to reach the above-identified reverse-biased junctions of structure 100, the volume of first epitaxial layer 113 is sufficiently small so that few long-lifetime, long-diffusion-length electron-hole pairs are generated in such layer 113. The number of electron-hole pairs generated in first epitaxial layer 113 may be reduced even further by reducing the thickness, and hence the volume, of layer 113.However, first epitaxial layer 113 must be maintained sufficiently thick to provide a suitable breakdown voltage for transistors formed in structure 100.
To summarize, the double-epitaxial layer semiconductor device structure 100 of the present invention produces significantly reduced amounts of radiation-induced electronhole pair current at the above-identified reverse-biased P-N isolation junctions thereof by a combination of two effects: (1) highlydoped, low resistivity bulk substrate 112 emitting electron-hole pairs having relatively short diffusion lengths and lifetimes; and, (2) more moderately-doped, higher-resistivity first epitaxial layer 113 of the same dopant conductivity type as substrate 112 providing reduced volume (substantially smaller than that of bulk substrate 112) from which electron-hole pairs of sufficient lifetime and diffusion length to reach the reverse biased P-N isolation junctions are generated, while further providing sufficient thickness to prevent the short-diffusion-length electron-hole pairs emitted by highly-doped substrate 112 from reaching such reverse-biased P-N junctions. With such arrangement, a semiconductor device structure 100 with a decreased sensitivity to incident radiation is provided and may be fabricated using available fabrication processes, such as that described in the above-identified U.S. Patent No. 4,512,076.Thus, there is no need to fabricate the bulk substrate from dielectric material, such as sapphire or polycrystaline silicon, which are expensive materials and present fabrication difficulties.
It should be noted here that it is not necessary to maintain a two order-of-magnitude difference between the resistivities of bulk substrate 112 and first epitaxial layer 113 in order to achieve decreased sensitivity to radiation effects. For example, bulk substrate 112 may be doped less heavily than discussed above to have a resistivity of 0.1 ohm-cm, for example. Electron-hole pairs generated in substrate 112 would still exhibit decreased lifetimes (2.7 ,l 10 8 sec.) and diffusion lengths (about 5 ,lem) over the high resistivity (on the order of 2 ohm-cm) bulk substrate 12 used in prior art structure 10 (and having carrier lifetimes and diffusion lengths of 3.4 x 10 6 sec. and 98,um, respectively).The diffusion length of the carriers in a 0.1 ohm-cm resistivity substrate 112 is seen to still be less than the selected thickness (10-12 Am) of first epitaxial layer 113. Thus, few, if any, of such carriers reach the reverse-biased P-N isolation junctions of structure 100. The dopant concentration difference between bulk substrate 112 and first epitaxial layer 113, and hence the resistivity ratio therebetween, will depend on the amount of radiation hardness desired, as well as on the electrical parameters of the devices formed on semiconductor structure 100.
Referring now to FIG. 2, a second embodiment of the semiconductor device structure 100 of the present invention is shown using electrically insulating regions 130, here comprising silicon dioxide (SiO2), and p±type channel stop regions 132 in place of p±type diffusion isolation channels 118 (FIG. 1B). Alternately, regions 130 may comprise other suitable dielectric media, such as amorphous silicon. As shown, SiO2 regions 130 extend from the upper surface of second epitaxial layer 114 and terminate at a predetermined depth of layer 114. That is, SiO2 regions 130 do not extend completely through second epitaxial layer 114. SiO2 regions 130 terminate at upper regions of p±type channel stops 132, which are formed in a conventional manner, such as by diffusion.As shown, p±type channel stops 132 extend from upper regions of first epitaxial layer 113 into overlaying lower regions of second epitaxial layer 114 for the reasons discussed above regarding isolation channels 118. Thus, it may be appreciated that p'-type channel stops help provide an increased-threshold-reverse-biased P-N junction bewteen adjacent circuits, such as ISL circuits 11 (FIG. 1C), formed in semiconductor device structure 100. It is noted that when insulating regions 130 are used to provide dielectric horizontal isolation (rather than the junction horizontal isolation provided by isolation channels 118 of FIG. 1B), the thickness of second epitaxial layer 114 may be reduced. Here, such thickness is decreased to between about 1.1 item and 1.7 ,ism.
Alternately, SiO2 regions 130 may be extended into p-type first epitaxial layer 113. In such case, p -type channel stops 132 need not be formed below SiO2 regions 130 if the p-type dopant concentration of first epitaxial layer 113 is sufficiently high. In yet another embodiment, insulating regions 130 may be extended completely through second epitaxial layer 114 and first epitaxial layer 113 and into p -type substrate 112. Due to the high dopant concentration of p'-type substrate 112, p+type channel stops 130 need not be formed in such case.
Having described preferred embodiments of the present invention, other embodiments may become apparent to those skilled in the art.
For example, bulk substrate 112 could be fabricated using n±type silicon, in which case first epitaxial layer 113 would also be doped with n-type dopant and second epitaxial layer
114 doped with p-type dopant. Further, the present invention may be utilized with circuitry types, such as TTL, ECL, etc, other than ISL.
In addition, the present invention may be applied to reduce radiation effects in circuits made using semiconductor material other than silicon, such as gallium-arsenide. Finally, field effect, as well as bipolar, transistors may be formed in semiconductor device structures of the present invention. Accordingly, it is understood that the scope of the present invention is to be limited only by the scope of the appended claims.
CLAIMS
1. A semiconductor structure comprising:
a substrate comprising semiconductor material having a first-type doping conductivity;
a first layer of semiconductor material epitaxially formed on the substrate, said first layer having the first-type doping conductivity and a dopant concentration lower than a dopant concentration in the substrate; and
a second layer of semiconductor material epitaxially formed on the first layer of semiconductor material, said second layer having a second-type doping conductivity opposite to the first-type doping conductivity.
2. The semiconductor structure of Claim 1 wherein the dopant concentration in the substrate is substantially two orders of magnitude greater than the dopant concentration in the first layer.
3. The semiconductor structure of Claim 1 wherein the first and second layers form a P
N junction.
4. The semiconductor structure of Claim 1 further comprising:
means, disposed in the second layer, for providing electrical isolation between different regions of the second layer.
5. The semiconductor structure of Claim 4 wherein the electrical isolation providing means comprises a region of the second layer doped with the first-type doping conductivity.
6. The semiconductor structure of Claim 4 wherein the electrical isolation providing means extends completely through the second layer and into the first layer by a predetermined distance.
7. A semiconductor structure comprising:
a substrate having a first thickness, said substrate comprising semiconductor material having a first-type doping conductivity and a first dopant concentration, said semiconductor material comprising means for emitting, in response to incident radiation, electron-hole pairs having a predetermined diffusion length;
a first semiconductor layer disposed over the substrate, said first layer having the firsttype doping conductivity and having a second thickness greater than the diffusion length of the electron-hole pairs emitted by the substrate and substantially less the first thickness; and
a second layer of semiconductor material disposed over the first layer, said second layer having a second-type doping conductivity opposite to the first-type doping conductivity.
8. The semiconductor structure of Claim 7 wherein the substrate has a first resistivity and the first layer has a second resistivity, the first resistivity being less than the second resistivity.
9. The semiconductor structure of Claim 8 wherein the first and second layers form a P
N junction.
10. A semiconductor structure comprising:
a substrate comprising semiconductor materian having a first-type doping conductivity in a first dopant concentration,
a first layer of semiconductor material epitaxially formed on the substrate, said first layer having the first-type doping conductivity in a second dopant concentration lower than the first dopant concentration;
a second layer of semiconductor material epitaxially formed on the first layer, said second layer having a second-type doping conductivity opposite to the first-type doping conductivity and forming a P-N junction with the first layer; and
means, formed in the second layer, for providing electrical isolation bewteen active devices formed in different regions of the second layer of semiconductor material.
11. The semiconductor structure of Claim 10 wherein the electrical isolation providing means comprises a region disposed through the entire thickness of the second layer and extending a predetermined distance into the first layer.
12. The semiconductor structure of Claim 11 wherein said predetermined distance is approximately 20% of the thickness of the first layer.
13. The semiconductor structure of Claim 11 wherein said region comprises semiconductor material having the first-type doping conductivity in a dopant concentration higher than the dopant concentration of the first layer.
14. The semiconductor structure of Claim 13 wherein a portion of said region comprises an electrically insulating material.
15. The semiconductor structure of Claim 14 wherein the electrically insulating material comprises silicon dioxide.
16. The semiconductor structure of Claim 13 wherein the first-type and second-type doping conductivities provide a P-N junction between: the first layer and the region; and, the second layer.
17. The semiconductor structure of Claim 10 wherein the semiconductor material comprises silicon.
18. A method of fabricating a semiconductor structure, comprising the steps of:
providing a substrate of semiconductor material having a first-type doping conductivity;
epitaxially forming on the substrate a first layer of semiconductor material having the first-type doping conductivity in a concentration lower than a concentration of dopant in the substrate; and
epitaxially forming on the first layer a second layer of semiconductor material having a second-type doping conductivity opposite to the first-type doping conductivity.
19. The method of Claim 18 further comprising the step of:
forming a region in the second layer extending a predetermined distance into the first layer, the region comprising semicondcutor material having the first-type doping conductivity in a concentration higher than the concentration of dopant in the first layer.
20. The method of Claim 19 further comprising the step of:
depositing an electrical insulator in a portion of said region.
Claims (1)
- Amendments to the claims have been filed, and have the following effect: Claims 1, 7, 10, 18 above have been deleted or textually amended.New or textually amended claims have been filed as follows:1. A semiconductor structure comprising: a substrate comprising semiconductor material having a first-type doping conductivity and a first predetermined thickness; a first layer of semiconductor material disposed on the substrate, said first layer having the first-type doping conductivity and a dopant concentration lower than a dopant concentration in the substrate, said first layer having a second predetermined thickness substantially less than the first predetermined thickness of the substrate; and a second layer of semiconductor material disposed on the first layer of semiconductor material, said second layer having a secondtype doping conductivity opposite to the firsttype doping conductivity.7. A semiconductor structure comprising: a substrate having a first thickness, said substrate comprising semiconductor material having a first-type doping conductivity, said semiconductor material comprising means for emitting, in response to incident radiation, electron-hole pairs having a predetermined diffusion length; a first semiconductor layer disposed over the substrate, said first layer having the firsttype doping conductivity and having a second thickness, said second thickness being selected to be greater than the diffusion length of the electron-hole pairs emitted by the substrate and substantially less the first thickness; and a second layer of semiconductor material disposed over the first layer, said second layer having a second-type doping conductivity opposite to the first-type doping conductivity.10. A semiconductor structure comprising: a substrate comprising semiconductor material having a first-type doping conductivity in a first dopant concentration, said substrate having a predetermined thickness; a first layer of semiconductor material epitaxially formed on the substrate, said first layer having the first-type doping conductivity in a second dopant concentration lower than the first dopant concentration, said first layer having a thickness substantially less than the predetermined thickness of the substrate; a second layer of semiconductor material epitaxially formed on the first layer, said second layer having a second-type doping conductivity opposite to the first-type doping conductivity and forming a P-N junction with the first layer; and means, formed in the second layer, for providing electrical isolation between active devices formed in different regions of the second layer of semiconductor material.18. A method of fabricating a semiconductor structure, comprising the steps of: providing s substrate of semiconductor material having a first predetermined thickness snd a first-type doping conductivity, the substrate emitting electron-hole pairs having a predetermined diffusion length in response to radiation incident on the substrate; epitaxially forming on the substrate a first layer of semiconductor material having a second predetermined thickness substantially less than the first predetermined thickness and greater than the predetermined diffusion length, the first layer also having the first-type doping conductivity; and epitaxially forming on the first layer a second layer of semiconductor material having a second-type doping conductivity opposite to the first-type doping conductivity.21. The method of claim 18, wherein the first layer forming step epitaxially forms the first layer with a doping concentration substantially lower than a concentration of dopant in the substrate.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US80239785A | 1985-11-27 | 1985-11-27 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB8627267D0 GB8627267D0 (en) | 1986-12-17 |
| GB2183907A true GB2183907A (en) | 1987-06-10 |
| GB2183907B GB2183907B (en) | 1989-10-04 |
Family
ID=25183590
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB8627267A Expired GB2183907B (en) | 1985-11-27 | 1986-11-14 | Semiconductor device |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JPS62132355A (en) |
| DE (1) | DE3640438A1 (en) |
| FR (1) | FR2595869B1 (en) |
| GB (1) | GB2183907B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0351331A1 (en) * | 1988-07-13 | 1990-01-17 | STMicroelectronics S.A. | Integrated-circuit structure for the isolation between components |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1450293A (en) * | 1973-05-14 | 1976-09-22 | Sony Corp | Semiconductor integrated circuits |
| GB1450626A (en) * | 1973-02-02 | 1976-09-22 | Philips Electronic Associated | Semiconductor devices |
| GB1450749A (en) * | 1973-09-26 | 1976-09-29 | Rca Corp | Semiconductor darlington circuit |
| GB1488958A (en) * | 1975-03-25 | 1977-10-19 | Texas Instruments Ltd | Fast switching darlington circuit |
| GB1498531A (en) * | 1974-04-26 | 1978-01-18 | Western Electric Co | Semiconductor integrated injection logic cell |
| GB1539426A (en) * | 1975-04-04 | 1979-01-31 | Hitachi Ltd | Power transistor device |
| GB2018511A (en) * | 1978-04-07 | 1979-10-17 | Philips Nv | Semiconductor device |
| EP0022687A1 (en) * | 1979-06-12 | 1981-01-21 | Thomson-Csf | Integrated monolithic circuit equivalent to a transistor associated with three antisaturation diodes, and method for making it |
| EP0138517A1 (en) * | 1983-10-11 | 1985-04-24 | AT&T Corp. | Semiconductor integrated circuits containing complementary metal oxide semiconductor devices |
| EP0139371A1 (en) * | 1983-08-12 | 1985-05-02 | Tektronix, Inc. | Process for manufacturing a MOS integrated circuit employing a method of forming refractory metal silicide areas |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4216489A (en) * | 1979-01-22 | 1980-08-05 | Bell Telephone Laboratories, Incorporated | MOS Dynamic memory in a diffusion current limited semiconductor structure |
| DE2952318C2 (en) * | 1979-12-24 | 1986-09-18 | Telefunken electronic GmbH, 7100 Heilbronn | Integrated circuit arrangement and method for making it |
| US4512076A (en) * | 1982-12-20 | 1985-04-23 | Raytheon Company | Semiconductor device fabrication process |
-
1986
- 1986-11-14 GB GB8627267A patent/GB2183907B/en not_active Expired
- 1986-11-27 DE DE19863640438 patent/DE3640438A1/en not_active Ceased
- 1986-11-27 FR FR8616565A patent/FR2595869B1/en not_active Expired - Fee Related
- 1986-11-27 JP JP61283036A patent/JPS62132355A/en active Pending
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1450626A (en) * | 1973-02-02 | 1976-09-22 | Philips Electronic Associated | Semiconductor devices |
| GB1450293A (en) * | 1973-05-14 | 1976-09-22 | Sony Corp | Semiconductor integrated circuits |
| GB1450749A (en) * | 1973-09-26 | 1976-09-29 | Rca Corp | Semiconductor darlington circuit |
| GB1498531A (en) * | 1974-04-26 | 1978-01-18 | Western Electric Co | Semiconductor integrated injection logic cell |
| GB1488958A (en) * | 1975-03-25 | 1977-10-19 | Texas Instruments Ltd | Fast switching darlington circuit |
| GB1539426A (en) * | 1975-04-04 | 1979-01-31 | Hitachi Ltd | Power transistor device |
| GB2018511A (en) * | 1978-04-07 | 1979-10-17 | Philips Nv | Semiconductor device |
| US4288807A (en) * | 1978-04-07 | 1981-09-08 | U.S. Philips Corporation | Darlington circuit having an improved diode drain |
| EP0022687A1 (en) * | 1979-06-12 | 1981-01-21 | Thomson-Csf | Integrated monolithic circuit equivalent to a transistor associated with three antisaturation diodes, and method for making it |
| EP0139371A1 (en) * | 1983-08-12 | 1985-05-02 | Tektronix, Inc. | Process for manufacturing a MOS integrated circuit employing a method of forming refractory metal silicide areas |
| EP0138517A1 (en) * | 1983-10-11 | 1985-04-24 | AT&T Corp. | Semiconductor integrated circuits containing complementary metal oxide semiconductor devices |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0351331A1 (en) * | 1988-07-13 | 1990-01-17 | STMicroelectronics S.A. | Integrated-circuit structure for the isolation between components |
| FR2634321A1 (en) * | 1988-07-13 | 1990-01-19 | Sgs Thomson Microelectronics | INTEGRATED CIRCUIT STRUCTURE IMPROVING ISOLATION BETWEEN COMPONENTS |
Also Published As
| Publication number | Publication date |
|---|---|
| GB2183907B (en) | 1989-10-04 |
| GB8627267D0 (en) | 1986-12-17 |
| FR2595869A1 (en) | 1987-09-18 |
| JPS62132355A (en) | 1987-06-15 |
| FR2595869B1 (en) | 1991-04-19 |
| DE3640438A1 (en) | 1987-07-02 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 19941114 |