GB2178542A - Signature analysis test circuits - Google Patents

Abstract

A signature analysis circuit provides delays (22, 24) in data and/or clock signal paths in order to change the relative timing of the clock and data signals, thus to eliminate race conditions between transitions in the two signals. Additionally, (Figs. 5-7 not shown) to use signature analysis for high- frequency signals, and to assure that short duration data events are detected a signature generator is triggered to accept data a plurality of times during each clock cycle, eg being triggered both by the rising and the falling transitions of the clock signal. <IMAGE>

Description

SPECIFICATION Improved signature analysis device for electronic circuits This invention relates to systems for testing electrical circuits, and more specifically to improvements in signature analysis devices utilized in such systems.

Known systems of testing digital circuits include signature analysis devices. Such devices convert a digital signal or bit stream detected at a node of a unit under test (hereinafter UUT) into a digital signature representative of the detected digital signal, typically utilizing a feedback shift register for that purpose.

A typical signature analysis device utilizes a shift register implemented state machine for combining, at clocked intervals, each bit of an input digital signal or bit stream with various bits in the register representing the present digital state thereof. More particulary, such a shift register is provided with proper feedback connections so that the bits at the various cells thereof are combined with the input bits according to rules of binary arithmetic. As a result, there is provided a combination of bits of the digital signal with selected ones of the preceding bits, to form a "signature" representative of the response of the UUT, at the node being examined, to a particular input sequence.

A signature analysis device thus generates a word or signature which accurately characterizes a data stream. Such signatures, obtained at various test points or nodes in a UUT, may be identified and characterized for testing purposes. Signatures from properly operating nodes are recorded for subsequent comparison with signatures of signals obtained from nodes of a UUT. The comparison of the observed and previously recorded signatures permits a user of the system to determine whether the UUT is or is not operating properly and to locate any faulty circuits or nodes in the UUT.

Typical of signature analysis devices is a configuration wherein the feedback register used in a signature generator is triggered to receive digital data at predetermined clocked intervals. However, in the prior art use of signature analysis devices signature generators are typically prevented from responding to signals of short duration by the frequency of the synchronizing clock signal. More particularly, prior art signal generators are triggered to accept data by rising edges of a clock pulse signal. Alternatively, such generators are triggered by falling edges of a clock signal.

Such signature generators are thus reliable only in situations where data level changes occur at a frequency sufficiently low to be detected at the clock frequency. Thus, signals changing at higher frequencies may not be detected reliably.

Accordingly, there is a need in the prior art for improvement of signature analysis devices to permit detection of higher frequency signals and, more particularly, to permit detection of rapidly changing signals without expensive modification and revision of the test system.

Moreover, because the prior art test systems operate on a clocked acceptance and analysis of the data signal, it is possible that unreliable data may be obtained in situations wherein the data undergoes transitions substantially simultaneously with, or in the time proximity of, transitions of the clock signal used to trigger the signature generator.

Such simultaneous or near-simultaneous transitions of two signals typically leads to race conditions in which the outcome is indeterminate and is dependent on which of the two signals is first completed or is first detected at a particular circuit point. In view of aging of components, and further in view of variation of temperature and other environmental conditions, it is thus possible that a signature analysis in which a race condition exists may provide one result under one test condition and may provide a contrary result in a second test condition, while the UUT functions at the same level of performance in both conditions.

There is thus a further need in the prior art to provide an improved signature analysis device which avoids the introduction of race conditions between clock and data signals in order to provide repeatable and reliable results of a circuit test.

Accordingly, it is an object of the present invention to provide a test system for electronic circuits utilizing a signature analysis device overcoming the difficulties of the prior art.

It is a more specific object of one form of the invention to provide a signature analysis device in which incoming data is accepted for analysis at a higher frequency than the frequency of a clock signal.

It is another object of this form of the invention to provide a signature analysis device in which the incoming data is accepted and analyzed at a rate double the frequency of a clock signal.

It is still a further object of this form of the invention to provide a test system for electronic digital circuits in which a signature analysis device is triggered to receive incoming data signals on rising edges and on falling edges of a clock signal applied thereto.

It is an object of another form of the invention to provide a test system for digital electronic circuits in which race conditions be tween incoming data and a clock signal are overcome.

A more specific object of this form of the invention is to provide a structural arrange ment for eliminating races between a clock signal and a data signal incoming to a signa ture generator by providing a user variable delay in a signal path of one or both of the clock and data signals.

Additional objects of the invention will be set forth in part in the description which follows and in part will become apparent to those skilled in the art upon examination of the following, or may be learned with the practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the appended claims.

To achieve the foregoing and other objects, and in accordance with the purpose of the present invention, as embodied and broadly described herein, there is provided in one embodiment a test apparatus including a signature means for comparison of a signal observed at a circuit node of an electronic circuit under test with a response at that node expected for a predetermined input to the circuit. The improved test apparatus includes a means for eliminating race conditions between a a clock signal and a data signal input to the signature means. Additionally, means is provided to permit adjustment of the race eliminating means.

In a more particular aspect of the invention, the adjusting means includes a user controlled delay connected in a signal path associated with the signature means. The delay is preferably a user controlled variable delay connected in one or both of the clock or data signal paths, in order to provide a user controlled adjustment of relative timing between the clock and data signals.

The means for eliminating race conditions between the clock and data signals input to the signature means may be provided in addition to an internal race eliminating means provided within the signature means. Such an internal race eliminating means eliminates race conditions caused by internal circuit configurations of the signature means. The improvement of the present invention thus eliminates the race conditions generated by external conditions affecting clock and signal data.

Another feature of the present invention provides structure for increasing the amount of information input to the signature means during a given interval of the clock signal for analysis.

One aspect of the invention provides such an increase in conjunction with the race eliminating arrangement. Another aspect combines the means for increasing information provided to the signature means with means for triggering the signature means to accept data a number of times during a clocked interval.

Preferably, the triggering means includes first and second means for triggering the signature means at first and second predetermined times, respectively, during the clock interval.

In accordance with one aspect of the invention the first and second means may be used to trigger the signature means on rising and falling edges of a clock pulse signal.

Other objects, features and advantages of the present invention will become readily apparent to those skilled in the art from the from the following description wherein there is shown and described a preferred embodiment of the invention, simply by way of illustration and not of limitation of one of the best modes (and alternative embodiments) suited to carry out the invention. As will be realized upon examination of the specification and from practice of the same, the present invention is capable of still other, different, embodiments and its several details are capable of modifications in various obvious aspects, all without departing from the invention. Accordingly, the drawings and the descriptions provided herein are to be regarded as illustrative in nature and not as restrictive of the invention.

In the drawings: Figure 1 illustrates an aspect of a typical test device of the prior art incorporating a signature generating device; Figure 2 shows clock and data wave forms illustrating difficulties of the prior art and correction thereof in accordance with the present invention; Figures 3(a), 3(b) and 3(c) provide block diagrams of circuit embodiments incorporating the inventive concept for corrections of the difficulties of Fig. 2; Figure 4 shows wave forms illustrating yet another difficulty in the prior art; Figure 5 shows a block diagram of a circuit arrangement for eliminating the difficulty shown in Fig. 4; Figure 6 shows a specific embodiment of the improvement of Fig. 5; Figure 7 illustrates an arrangement combining the improvements of Figs. 3(c) and Fig. 6.

Referring now to Fig. 1, there is illustrated a portion of a typical prior art electronic test apparatus 10 utilizing a signature generator 12. As is known in the prior art, such devices are utilized for testing digital circuits by determination of response sequences at particular nodes of the circuit to a specified sequence of input digital signals.

Since such devices are well known in the art, and do not form a part of the present invention, further description of the same is unnecessary and is accordingly omitted. However, it is noted that a signature generator illustrated at 12 in Fig. 1 typically includes a shift register.

The signature generator, as shown in Fig. 1, receives a clock signal at input 14 thereof.

The clock signal may be specifically generated for use by the signature generator 12 or may be generated within the unit under test (UUT).

A second input 16 receives a digital data sig nal from the UUT. Additional inputs 18 and 20 are provided to receive appropriate signals to start and stop the generation of a signature by selecting a particular time window for examining the node response in accordance with any known or desired criteria.

Generation of the start and stop signals and of the clock signals provided to the signature generator does not form part of the present invention. Rather, it is the relationship between clock and data signals at inputs 14 and 16 to the signature generator which is the primary focus of the present invention, along with an improvement in the ability of signature generator 12 to discern the various data levels and transitions provided at input 16 at specified intervals defined by the clock signal on input 14. Particularly, the shift register of signature generator 12 accepts the data on input 16 at time intervals defined by clock signal 14. Typically, as is known in the art the signature generator 12 will examine the data signals at times corresponding to the rising pulse edges of the clock signal shown at wave form a a in Fig. 2.Alternatively, the signature generator may examine the data at the falling edges of the clock pulses.

A problem solved by the present invention relates to a situation in which the data signal may be changing on or about a time of transition of the clock signal provided to the signature generator. Accordingly, the actual signature generated by generator 12 may be unstable and may change in response to minor environmental variations affecting the timing of either the clock signal or the data signal. Typically, such a situation is identified as a "race condition" in which a race exists between arrival of the data transition or the clock transition at the signature generator, the outcome of such a race determining the resultant signature.

Referring specifically to Fig. 2, there is illustrated at waveform b a data signal having four transitions. For illustrative purposes, transitions 2 and 3 of the data signal are seen to occur in the immediate vicinity of positive transitions of the clock signal in wave form a while transitions 1 and 4 are seen to be in the vicinity of negative transitions of clock signal waveform a.

Thus, for a situation in which the signal generator is triggered to examine the data signal at negative transitions of the clock, data transitions 1 and 4 may or may not be detected, depending on which of the transitions wins the "race". Independently of quality of operation of the UUT, the signature generated by signature generator 12 may thus indicate proper or improper functioning of the unit for reasons totally unrelated to proper operation of the same. Alternatively, for a signature generator responding to positive transitions of the clock signal for examining the data, the transitions 2 and 3 might be missed or detected depending on minor variations in timing, settling time, environmental conditions or the like.

Thus, whether utilizing positive or negative triggering, it is seen that a relationship between the clock and data signals may lead to unstable results in that a particular signature may be generated and may vary independently of proper or improper operation of the UUT. It should also be noted that the above described difficulties are not caused by improper operation of the signature generator which properly examines data arriving at its input terminal 16.

Instead, the instabilities of the signature provided by generator 12 relate merely to coincidence or near-coincidence of data and clock signal transitions.

In accordance with the present invention there are shown three arrangements in Figs.

3(a)-3(c) for overcoming the above described difficulties. As is seen therein, in accordance with the present invention adjustable relative delays are introduced between the clock and data signals. Thus, there may be provided an adjustable relative delay 22 for the clock signal, as seen in Figs. 3(a) and 3(c). An adjustable delay may be provided for the data signal as shown at 24 in Figs. 3(b) and 3(c). Delays may be provided for both the clock and data signals as illustrated at Fig. 3(c).

By setting any of the delays in Figs.

3(a)-3(c) to an arbitrary or nominal value, a predetermined relationship, such as shown at waveforms a and b of Fig. 2, may be established between the clock and delay signals.

Where race conditions exist, adjustment of the delay by the user may eliminate the race conditions and enhance the stability of the generated signature, thus increasing the reliability of the test device incorporating the signature analysis tool therein.

For example, as shown at wave form c in Fig. 2, the data signal may be advanced slightly relative to the clock signal. The advance may be obtained in the embodiment of Fig. 3(a) by increasing the delay provided by delay 22 for the clock signal. In Fig. 3(b) advance of the data signal may be obtained by decreasing the delay provided by delay 24.

The arrangement of Fig. 3(c) provides for either increasing the delay provided by unit 22, decreasing the delay provided by unit 24, or providing a combined adjustment of delays 22 and 24 whereby the net relative delay change is such as to provide added delay for the clock signal relative to the data signal. As seen in the waveform c in Fig. 2, transitions 1 and 4 are advanced relative to the negative transitions of the clock signal so that the race condition between the two is eliminated. In that regard, it is also seen that the race condi- tion between the transition 3 and the positive transition of the clock signal is eliminated. The race between transition 2 and the positive transition of the clock signal remains, how ever.Nonetheless, for a negatively triggered signature generator, the race condition at tran, sition 2 is of no significance.

For a positively triggered signature generator the relative adjustment of delays illustrated by the waveform c is of little consequence. Although the race at transition 3 is eliminated, the race at transition 2 remains, so that stability of the resultant signature and reliability of the test remains subject to question, although both the unit under test and the signature generating test device may be functioning properly. Accordingly, a delay adjustment in the opposite direction, wherein the data signal is delayed relative to the clock signal, may be attempted by the user. As seen at waveform d, such a delay applied to the data signal in fact corrects the races between data transitions and positive transitions of the clock signal. For a positively triggered signature generator the resulting race between transition 2 and a negative going clock signal transition is of no consequence.

In order to attain the delayed signal of waveform d, the delay provided by unit 22 may be reduced from its nominal value thus to advance the clock signal relative to the data signal. Alternatively, the delay provided by unit 24 may be increased, or a combination of adjustments may be provided for the embodiment of Fig. 3(c) resulting in a net increase in relative delay between the data signal and the clock signal.

There has thus been shown a method and apparatus for user controlled adjustment of signal delays to overcome instability of operation of a test system utilizing a signature analysis tool and to enhance reliability of the results thereof.

The variable delay provided in accordance with the invention permits a user to shift a relationship between clock and data signals in order to achieve a good quality signature having an improved stability. Such an arrangement permits design of a signature analysis tool for operation at higher frequencies, where propagation delay becomes significant relative to clock signal intervals and where it is necessary to consider skew of signal and clock transitions to assure that the two transitions do not interfere with one another. Because the present invention permits adjustment of delay to be made during a test, interference or race conditions between the two signals can be avoided.

In that regard, it is noted that in order to achieve the desired relationship between clock and data signals in which a stable and reliable signature is obtained it may be necessary to perform a number of tests. In each test the amount of delay between the clock and data signals may be adjusted, and the stability of the resulting signature may be observed after a number of seconds or a number of hours and after possible variations in environmental conditions. Since the stability of the signature may be electronically detected, such as by obtaining a practical number of signatures and determining variations of signature response values, adjustment of the delay in Figs.

3(a)-3(c) may be mechanized. A test control ler may be programmed to vary the delays incrementally and to obtain signature readings over a range of delays. The readings having the greatest stability would be electronically determined to identify an optimal delay, preferably in the middle of the range of stable delays, to provide a signature of increased reliabilty.

As hereinabove described, the present invention permits operation of a signature analysis tool at higher clock frequencies. However, in addition to the race conditions illustrated in Fig. 2, a timing relationship between clock and data signals may exist which prevents the signature generator from responding to particular data transitions. Such a relationship is illustrated in the wave forms of Fig. 4, wherein a clock signal is illustrated at waveform a and a data signal is illustrated at waveform b. Positive clock transition times are indicated by chain-dot lines while negative clock transition times are indicated by dotted lines, similarly to Fig. 2.

As illustrated therein, a condition may arise wherein a sufficiently high-frequency data event occurs and is not detected by the signature generator. Specifically, it is noted that a signature generator triggered by the positive going clock pulse transitions will not detect, accept or observe the data transitions 1 and 2; and that a signature generator triggered by negative going clock pulse transitions will not detect, accept or observe the data transitions identified at 3 and 4. Thus, although a prior art device triggered by positive going transitions of the clock signal will detect the data pulse between transitions 3 and 4, such a generator will not detect the data pulse occurring between transitions 1 and 2.Similarly, a prior art signature generator triggered to accept data by negative going clock pulse transitions will detect the data event between transitions 1 and 2 but will not accept data between transitions 3 and 4.

The present invention overcomes this deficiency of the prior art by providing apparatus for triggering a signature generator to accept data a number of times during a clock pulse cycle. In the presently preferred embodiment the improvement provides a double clocking of data, that is, a circuit arrangement for accepting of data twice within a clock interval, as shown at Fig. 5. The embodiment of Fig. 5 receives the clock signal on input 14 and generates therefrom a double clocking signal in circuit 26. Thus, during each clock interval a plurality of triggers are generated by the circuit 26 to cause signal generator 12 to accept data a plurality of times (specifically, 2 times) during each clock cycle.Preferably, the plural triggers are generated at uniform intervals within the clock cycle so that the signature generator is capable of detecting a data event of a particular duration regardless of the cycle interval in which the event occurs. Although the timing of the plural triggers generated by circuit 26 may be arbitrary, for a square wave clock signal the triggers are preferably generated in accordance with the rising and falling transitions of the same, since these transitions divide the clock cycle into equal intervals.

Thus, the improved signature generator accepts input data at a multiple of the clock frequency.

A circuit for providing double trigger pulses from the clock signal is shown in Fig. 6. A delay 28 receives the input clock signal and an exclusive OR gate 30 receives the output of delay 28 and the clock signal. As will be appreciated, during any portion of the clock cycle when the output of delay 28 is at the same level as the clock signal itself, the output of exclusive OR gate 30 is zero. When the clock signal changes, whether positively or negatively, the two inputs to exclusive OR gate 30 are different and thus the output thereof changes to a logic 1 or a high level.

After expiration of the delay provided by delay circuit 28, the two inputs to gate 30 are again identical and the output drops to a low level.

Thus, the circuit 26 generates a positive and a negative transition in response to each transition of the clock signal shown in waveform a of Fig. 4, provided that the delay generated by delay circuit 28 is less than the duration of a clock pulse in waveform a. A positive transition is output by circuit 26 in coincidence with each of the clock transitions and a negative transition is output by circuit 26 delayed by an amount set by circuit 28 from the transition of the clock signal.

Accordingly, signature generator 12 receives both positive and negative trigger inputs for each clock transition. Thus, for a positively triggered signature generator there will be received a triggering pulse between transitions 1 and 2 of the data signals shown at waveform b in Fig. 4, and the event characterized by transitions 1 and 2 (as well as that characterized by transitions 3 and 4) will be accepted and used in forming the appropriate signature.

Similarly, for negatively triggered signature generators there will be a negative trigger provided between transitions 3 and 4 of the data signal so that both the data events will be accepted for forming the proper signature.

It is thus seen that by providing a plurality of trigger pulses during each clock cycle additional information is utilized to form the signature. Clocking on both edges of a clock pulse doubles the amount of information input to the register of the signature generator. Thus, reliability of a signature is increased for an arrangement as illustrated in Figs. 5 and 6.

In Fig. 7 there is illustrated an arrangement incorporating an adjustable relative delay provided between clock and data signals by delay circuits 22 and 24, and the arrangement for triggering the signature generator twice during each clock cycle. Accordingly, the embodiment of Fig. 7 may be used to eliminate race conditions as well as to detect data events of short duration.

The foregoing description qf the preferred embodiment of the invention has been presented for purposes of illustration and description and is not intended to be exhaustive or to limit the invention to the precise forms disclosed, since many obvious modifications and variations are possible in the light of the above teaching. The embodiment was chosen and described in order best to explain the principles of the invention and its practical application, thereby to enable others skilled in the art best to utilize the invention in various embodiments and with various embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims appended hereto, when interpreted in accordance with the full breadth to which they are fairly and legally entitled.

Claims (14)

1. In a test apparatus for an electronic circuit including signature means for comparison of a dynamic pulsed signal, observed at a circuit node in response to an application of a predetermined dynamic pulsed input signal to the circuit, with a correct response to said pulsed input signal observed at a corresponding circuit node of a properly functioning circuit, the improvement comprising: race eliminating means for eliminating race conditions between a clock signal and a data signal input to said signature means, and adjusting means for permitting adjustment of said race eliminating means.

2. An improved test apparatus as recited in claim 1 wherein said adjusting means comprises user controlled delay means connected in a signal path associated with said signature means.

3. An improved test apparatus as recited in claim 2 wherein said user controlled delay means includes a variable delay means connected in a clock signal path to provide timing adjustment of a clock signal received at said signature means for triggering operation of said signature means on data present on a data signal path, thereby providing user controlled adjustment of relative timing between said clock signal and said data signal to eliminate a race condition therebetween.

4. An improved test apparatus as recited in claim 3 wherein said user controlled delay means comprises further variable delay means connected in a data signal path to provide timing adjustment of a data signal received at said signature means for analysis thereby at a time determined by said clock signal, thereby providing further adjustment of relative timing between said clock signal and said data signal.

5. An improved test apparatus as recited in claim 2 wherein said user controlled delay means comprises variable delay means connected in a data signal path to provide timing adjustment of a data signal received at said signature means for analysis thereby at a time determined by said clock signal, thereby providing adjustment of relative timing between said clock signal and said data signal to eliminate a race condition therebetween.

6. An improved test apparatus as recited in claim 1 wherein said signature means further includes means for eliminating internal race conditions therein caused by internal circuit configurations.

7. An improved test apparatus as recited in claim 1 comprising means for increasing an amount of information input to said signature means during a given cycle of said clock signal.

8. An improved test apparatus as recited in claim 7 wherein said increasing means comprises means for triggering operation of said signature means on rising and falling transitions of said clock signal thereby providing input data to said signature means twice for each occurrence of a clock pulse.

9. In a test apparatus for an electronic circuit including signature means for comparison of a dynamic pulsed signal, observed at clocked intervals at a circuit node in response to an application of a predetermined dynamic pulsed input signal to the circuit, with a correct response to said pulsed input signal observed at a corresponding circuit node of a properly functioning circuit, the improvement comprising: means for increasing an amount of information input to said signature means in said clocked intervals including means for triggering said signature means to accept the signal from said node a plurality of times during a clocked interval.

10. An improved test apparatus as recited in claim 9 wherein said means for triggering includes first means for triggering said signature means at a first predetermined time in said clock interval and second means for triggering said signature means at a second predetermined time in said clock interval.

11. An improved test apparatus as recited in claim 10 wherein said first means comprises means for triggering said signature means on a rising edge of a clock pulse and said second means comprises means for triggering said signature means on a falling edge of a clock pulse.

12. An improved test apparatus as recited in claim 9 further comprising race eliminating means for eliminating race conditions between a clock signal defining said clocked intervals and a data signal input to said signature means, said race eliminating means comprising user controlled variable delay means connected in a clock signal path to provide timing adjustment of a clock signal received at said signature means for triggering operation of said signature means on data present on a data signal path, thereby providing user controlled adjustment of relative timing between said clock signal and said data signal to eliminate a race condition therebetween.

13. An improved test apparatus including as recited in claim 9 further comprising race eliminating means for eliminating race conditions between a clock signal defining said clocked intervals and a data signal input to said signature means, said race eliminating means comprising user controlled variable delay means connected in a data signal path to provide timing adjustment of a data signal received at said signature means for analysis thereby at a time determined by said clock signal, thereby providing adjustment of relative timing between said clock signal and said data signal to eliminate a race condition therebetween.

14. Test apparatus for an electronic circuit, substantially as hereinbefore described with reference to and as shown in Figs. 3a), 3b), 3c), 5, 6 or 7.