GB2177559A - Speed control of motors - Google Patents

Abstract

A free-running oscillator (147) produces triangular pulses to a comparator (COM6) to whose other input is applied a speed controlling signal (REG) so as to provide an open loop pulse width modulated control output, useable for a brushless d.c. motor. The speed controlling signal (REG) is biassed so that there is an active range operative to provide pulse width speed control of the motor, which may drive a ceiling mounted fan, and below the active range, an inactive range where the motor is stopped. The device may be in an integrated circuit with the minimum number of control connections. <IMAGE>

Description

GIB 2 177559 A 1

SPECIFICATION

Electronically commutated motors This invention relates in general to domestic appli- ances powered by an electronically commutated motor (ECM), a method of operating an ECM, and more particularly to a control circuit for an ECM.

The invention further relates to control circuits for EC Ms suited to fabrication in solid state electronic form to a large degree utilizing monolithic inte- grated circuitry, to integrated circuits having application to such control circuits for ECM motor powered appliances, and to an ECM powered vari- able speed fan incorporating such control circuitry.

Control circuits for electronically commutated motors have hitherto been fabricated using dis- crete electronic components, and yet the desirability of fabricating such control circuits in solid state electronic form, to a large degree utilizing mono- lithic integrated circuitry, is widely honored in dis- cussions among electrical industry spokesmen if not by an equally wide presence of products incor- porating such monolithic integrated circuitry in the actual market place.

The electronically commutated motors for which such control circuitry would have application is ex- emplified by those EC Ms disclosed in U S Patent Nos 4,005,347 and 4,169,990 to David M Erdman, and U S Patent No 4,162,435 to Floyd H Wright.

These motors are characterized by having a multis- tage winding assembly, and a magnetic assembly, the two arranged for mutual relative rotation, the motor in a given state of a multistate energization sequence, having an unenergized winding stage in which an induced back emf appears, which when integrated over time to a predetermined value indi- cates the instant at which the mutual relative angu- lar position has been attained suitable for commutation to the next state In the most com- mon examples, the multistage winding assembly is stationary, with the magnetic assembly arranged within the winding assembly, and arranged to ro- tate with respect to the immediate environment by means of bearings attached to a frame, mechani- cally common with the winding assembly The me- chanically opposite arrangement in which the winding asembly rotates within the magnetic as- sembly is less common, but makes many of the same requirements of the control circuitry, and in general the control circuitry has equal application to such motors In addition, the more common, magnetic assembly in such motors is a permanent magnetic assembly However, an arrangement in which the magnetic assembly is electromagnetic makes many of the same requirements of the con- trol circuitry, and in general, the control circuitry has equal application to such motors.

The common requirements of the control circui- try for electronically commutated motors, may be divided into four categories, which in a sense, place differing requirements upon their fabrication.

The appliance is installed in the house, and con- trols located when practical in the appliance, and when not practical, located at wall locations conve- nient to the user In the practical case of a com- bined ceiling fan, lighting fixture, which is the practical product exemplified herein, the "fan" in- cludes a motor, a light and user operated controls for the same The controls are both integral with the lighting fixture and remote The remote control may be located upon a convenient wall location and it may embody largely duplicate user operated controls The usual functions of the user operated controls include turning on or turning off the fan or light, regulating the intensity of the light, regulat- ing the speed of rotation, or direction of rotation of the fan.

The user operated controls, particularly those on the wall controls, are themselves constructed simi- larly to other wiring devices used in the he 5 me, and they are interconnected by electrical cable typical of the customary 110 AC house wiring In general, the requirement placed upon such "control sys- tems" is that the interconnections be minimal, and if possible not require additional special wiring.

Ideally, the wiring installation would permit com- plete communication within the "control systems" by the minimum two wire cable Ideally, the user operated control circuitry exemplified herein should require no more than two wires between the wall control, the fixture, and the house wiring for minimum installation expense In this category, the control circuit is fabricated in the form typical of house wiring systems.

A second category of electrical control circuit fabrication is utilized within the enclosure of the ceiling fixture or of the wall control This usually is "point to point" wiring, and the electrical connec- tions are made with mechanical bonds, including solder, rivets, or electrical terminals Here, the stress is often upon compactness, and ease of on- site assembly.

A third category of electrical control circuit fabri- cation, which is often practiced in the fixture itself or in the wall control, is that which is usually per- formed in the factory, and which is called "printed circuit board" (PCB) wiring This wiring is of mod- erate density, and allows for ampere level currents, voltages in excess of the customary house level voltages ( 120 240, etc), and heat dissipation lev- els comparable to the needs of the customary home appliances This wiring is used to intercon- nect by a factory process, discrete electronic components, such as resistors, capacitors, induc- tors, discrete solid state devices, such as transis- tors, diodes, diacs, triacs, SC Rs, etc on the printed circuit board.

When the control application of the control cir- cuitry is as complicated as the provision of elec- tronic commutation of an ECM motor and the imposition of user operated controls, and auto- matic protection functions incidental to user oper- ated controls, then the complexity of the control function required of the control circuitry tends to transcend the practical limits of fabrication by the assembly of discrete electrical components upon a printed circuit board In the printed circuit mode of fabrication for such control circuitry, the volume weight, and costs of printed circuit fabrication are 2 GB 2177559 A greater by a factor of at least a hundred, and often by a factor of a thousand times the comparable measure of a circuit of monolithic integrated circuit fabrication of like complexity.

The thrust of these practical considerations upon control circuit fabrication is to perform all of the control functions that can be performed, taking into account the limitations on allowable current levels, voltage levels and power dissipations, with monolithic integrated circuitry.

Present day limitations upon the application of integrated circuitry are less restrictive than some time ago, and more restrictive than one would ex- pect some time in the future In general, circuitry complexity required for the control function herein contemplated can be handled with MSI (Medium Scale Integration) or LSI (Large Scale Integration).

In the usual case, the component count of the mo- tor control system is on the order of 102 to 103.

The current, voltage and power dissipations ordi- narily dictate special interfacing circuits between the monolithic integrated circuit and the user oper- ated controls, the motor, the light and the power mains In general, this dictates that voltages ap- plied to the IC not exceed the voltage rating of the integrated circuit process, typically from 5 to 40 volts, that currents should not exceed tens of mil- liamperes and that power dissipation not exceed S of milliwatts Because of voltage limitations, it is necessary to use voltage dividers coupled to the winding stages of the motors to reduce the back emf sensed on the winding stages to several volts (e.g about 3 volts) before application to the inte- grated circuit Similarly, the control of power to the winding stages of the motor requires current and power dissipation levels that can only be per- formed by discrete solid state switches The inte- grated circuit, accordingly, has terminal pads supplied by internal drivers, with the power to con- trol either directly or through additional buffers, the solid state power switches energizing the wind- ing stages of the motor A similar practical prob- lem relates to the non-integrable components, which are primarily large capacitors, inductors, and the user operated controls These may usually be coupled to the pads of the monolithic integrated circuit with no other transition than the terminal pads of the integrated circuit and a demountable 16 pin connection on the printed circuit board.

There is a need to use a standard package with I Cs in order to keep the cost minimum This is typi- cally 16 pins There is also a need to keep outboard of the IC, components which control parameters which may change from product to product such as the inertia of the fan blades In other words, the IC must be able to adapt to ex- pected changes and must use a standard low cost package Some components which could be inte- grated are sometimes not put in the IC for these good engineering reasons.

To date, "maximally" monolithically integrated control circuits for electronically commutated mo- tors are not in common use in the market place.

Summary of the invention

Accordingly, it is an object of the present inven- tion to provide a maximally monolithically inte- grated control circuit for an electronically commutated motor.

It is another object of the invention to provide an improved control circuit for an electronically com- mutated motor.

It is still another object of the invention to pro- vide a control circuit for an electronically commu- tated motor with improved commutation.

It is an additional object of the invention to pro- vide a control circuit for an electronically commu- tated motor with improved speed or torque control.

It is a further object of the invention to provide a control circuit for an electronically commutated motor with improved reversing.

It is another object of the invention to provide a control circuit for an electronically commutated motor with improved starting performance.

It is an additional object of the invention to pro- vide a control circuit for an electronically commu- tated motor in which the commutation timing circuitry is improved.

It is a further object of the invention to provide a control circuit for an electronically commutated motor in which starting performance is improved.

It is another object of the invention to provide in a control circuit for an electronically commutated motor, a commutation timing circuit that is self balancing.

It is an additional object of the invention to pro- vide an improved control circuit for an electroni- cally commutated motor combining reversal of the motor with speed/torque control.

It is another object of the invention to provide a circuit for reversing an electronically commutated motor providing means for protecting the power switches during reversal.

It is another object of the invention to provide an improved integrated control circuit for an electroni- cally commutated motor.

It is still another object of the invention to pro- vide an integrated control circuit for an electroni- cally commutated motor with improved commutation.

It is an additional object of the invention to pro- vide an integrated control circuit for an electroni- cally commutated motor with improved speed or torque control.

It is a further object of the invention to provide an integrated control circuit for an electronically commutated motor with improved reversing.

It is another object of the invention to provide an integrated control circuit for an electronically com- mutated motor with improved starting performance.

It is an additional object of the present invention to provide a maximally integrated control circuit for an electronically commutated motor, providing economical remote control.

It is a further object of the invention to provide an improved method of operating an electronically commutated motor.

It is an additional object of the invention to pro- GB 2177559 A 3 vide an improved method of timing the commuta- tion of an electronically commutated motor.

It is another object of the invention to provide a method of improving the starting operation of an electronically commutated motor.

It is a further object of the invention to provide an improved method of controlling the speed or torque of an electronically commutated motor.

It is another object of the invention to provide an improved method of remotely controlling the speed or torque of an electronically commutated motor.

It is a further object of the invention to provide an improved method of reversing an electronically commutated motor.

It is another object of the invention to provide an improved method of control of an electronically commutated motor combining reversing with speed/torque control.

These as well as other objects of the invention will be dealt with in the description which follows.

They are achieved in a control circuit for an elec- tronically commutated motor adapted to be ener- gized from a DC power source, the motor having a three stage winding assembly, and a magnetic as- sembly, the two arranged for mutual relative rota- tion In a given state of a six state energization sequence causing relative rotation, the motor has one winding stage energized in one sense, a sec- ond winding stage energized in an opposite sense and serially connected with the first winding stage, and a third winding stage unenergized.

The inventive combination comprises input ter- minal means for connection to the winding stages and to the neutral motor connection or equivalent for deriving the back emf induced in successive unenergized winding stages, input switching means for selecting an unenergized winding stage responsive to an unenergized winding-stage selec- tion signal; a two input, differential transconsduct- ance amplifier means for conversion of the voltage supplied to a corresponding current; capacitive in- tegration means for providing a voltage substan- tially proportional to the integral of the back emf; and timing comparison means for comparing the voltage at the integration means to a value suitable for commutation, and upon sensing equality gen- erating a timing signal at the instant for commutation.

Continuing, the inventive combination includes control logic means for generating winding stage selection signals in a first six state sequence for forward motor rotation, and in a second six state sequence for reverse rotation, in each state of which a signal is generated for selecting one wind- ing stage for energization in one sense, a signal is generated for selecting one winding stage for ener- gization in the other sense, and a signal is gener- ated for selecting an unenergized winding stage for selecting an unenergized winding stage for sensing the induced back emf, the motor energization state changing in response to the timing signal at the in- stant for commutation to the next state in the se- quence The control logic means is responsive to a direction control signal for selection of the first or second energization sequence and to an energy control signal in a form including periodic pulse width modulated (PW Med) pulses, having a repeti- tion rate which is high in relation to the commuta- tion rate, winding stage energization occurring only during the active on time of the pulse of the energy control signals.

The inventive combination also includes a three- fold plurality of power switching means responsive to the winding stage energization signals for ap- propriately sensed energization of the winding stages in the multi-state sequences.

In accordance with another facet of the invention means are provided for periodically resetting the integration means to an initial state suitable for ini- tiating the succeeding integration; and for periodi- cally nulling the output current of the amplifier means, the nulling being timed to occur after the instant for commutation, but prior to reset The nulling means comprising means for incrementing an offset current at the input of the amplifier means to a value which corrects imbalance in the output current, and means for sustaining the cor- rective offset current until nulling again occurs.

Typically the nulling occurs once per commutation.

The input to the differential amplifier is coupled from the individual winding stages and the neutral connection by means of a four part voltage divider for scaling down the induced back emf to a value that the control circuitry can accommodate.

In accordance with a facet of the invention, con- trol logic means comprises counting means having one count for each of the ( 6) states of the motor energization sequence (e g, 0-1; 1-2; 2-3; 3-4; 4-5; 5-0; 0-1; etc) and at a constant rate of rotation al- locates equal time for each count in a repeating se- quence The counting means comprises a minimum number of flip-flops for defining the states, the flip-flops being positive (or negative) edge triggered flip-flops; which are clocked simultaneously by the timing signal.

The duration of the timing signal is long in rela- tion to the propagation delays in the control logic means, and is long enough to null the amplifier means and reset the integration means.

The winding stage selection signals are derived from the states of the counting means The input switching means to which the unenergized winding selection signals are applied, consists of a six-fold plurality of gates Accordingly, the control logic means includes a first rank of six gates connected to the outputs of the (three) flip-flops, and a sec- ond rank of six gates connected to the outputs of said first rank of gates.

The first rank of gates produces a first succes- sion of six equal duration pulses having an active period equal to the duration of one motor energi- zation state, and are used for operation of the in- put switching means.

The second rank of gates produces a second succession of six equal duration pulses having an active period equal to the duration of two motor energization states, the second succession occur- ring in an overlapping sequence The double dura- tion signals are used for operation of the power 4 GB 2177559 A switching means.

As earlier noted, the control logic is responsive to direction control signals and to energy control signals, having three ranks of gates for that pur- pose The 6-fold plurality of gates, responsive to direction and energy control signals, consists of two ranks of three input gates, one rank of gates for transmission of the forward multistate se- quence, one rank of gates for transmission of the reverse multistate sequence, and a third rank of two input gates for "oring" the outputs of said for- ward and reverse ranks of gates One input of each of the forward and reverse ranks of gates is cou- pled to an output of the second rank of gates, a second input of each of the forward and reverse ranks of gates is for application of the PW Med en- ergy control signal.

In accordance with another facet of the inven- tion, the control logic means includes means re- sponsive to the timing signal to apply the PW Med energy control signal at the beginning of the first half of the energization period of a winding stage for the duration of said timing signal, and at the beginning of the second half of the energization period of a winding stage, delaying for the dura- tion of said timing signal, before applying said PW Med energy control signal, for the remainder of the energization period.

At the output of the control logic means, six out- put drivers are provided for coupling the energized winding stage selection signals to the power switching means Three of the output drivers are for control of power switches connecting individual winding stages to one terminal (e g positive) of the power source; and three of said output drivers are for control of power switches connecting indi- vidual winding stages to the other terminal (e g.

negative) of the power source.

In accordance with a further facet of the inven- tion, the control circuit is provided with a power on reset circuit for producing an active output respon- sive to the voltage of the low voltage DC supply of the control circuit for gating off the drivers when the voltage has been below a first value when power is turned on or below a second value when power is turned off The voltage values being set such that normal circuit operation is assured at supply voltages exceeding the first and second val- ues.

In operation, the protective circuit gates off the drivers when power is turned on for a period of time required for stabilization of the operation of the control circuit It is accomplished by generating.

an artificial timing signal when power is turned on, signalling an artificial instant for commutation, nulling the amplifier means and causing the gener- ation of at least a partial sequence of winding stage selection signals and nulling before the driv- ers are gated on.

According to another aspect of the invention, the above objects are achieved in a control circuit for an electronically commutated motor adapted to be energized from a DC power source, the motor hav- ing a multistage winding assembly, and a mag- netic assembly, the two arranged for mutual relative rotation In a given state of a multistate energization sequence, the motor has an unener- gized winding stage in which induced back emf ap- pears which when integrated over time to a pre- determined value indicates the instant at which the mutual relative angular position has been attained suitable for commutation to the next state An inventive combination in the control circuit com- prises a solid state transconductance amplifier means adapted to be coupled to an unenergized winding stage in the motor for converting the volt- age appearing in the winding stage to a corre- sponding output current, integration means coupled to the output of the amplifier means for integrating the output current to obtain an output voltage substantially proportional to an integral of the voltage appearing in the winding stage, and comparison means for comparing the output volt- age of the integration means to a value corre- sponding to the mutual relative angular position suitable for commutation, and upon sensing equal- ity generating a timing signal at the instant for commutation.

In accordance with one facet of the invention the transconductance amplifier means has current se- ries feedback to stabilize amplifier transconduct- ance.

In the principal embodiment, the motor has a multistage winding arrangement with a neutral connection The transconductance amplifier means is, accordingly, a two input differential amplifier means, with one input adapted to be coupled to an uneriergized winding stage and the other input adapted to be coupled to the neutral connection or the equivalent The input stage of the amplifier means, is a differential input stage, which deter- mines the transconductance of the amplifier means, with significant current series feedback being provided for stabilizing this parameter in that stage.

The subsequent stages of the transconductance amplifier means are arranged to exhibit unity cur- rent gain and a first and a second solid state current mirror are included The output current from one transistor in the input stage is coupled to one current mirror and the output current from the other transistor in the input stage is coupled to the second current mirror The transconductance am- plifier means is completed with a first and a sec- ond solid state buffer amplifier, and a third, polarity inverting, current mirror.

More particularly, the first buffer amplifier com- prises a third transistor having the control elec- trode common and a first principal electrode coupled to the output of the first current mirror, and the second principal electrode coupled to the input of the polarity inverting current mirror The second buffer amplifier comprises a fourth transis- tor having the control electrode common and a first principal electrode coupled to the output of the second current mirror The third current mirror comprises a fifth, output transistor having its con- trol electrode coupled to the second principal elec- trode of the third transistor and a first principal electrode thereof connected to the second principal GB 2 177559 A 5 electrode of the fourth transistor, the fourth and fifth transistors being connected to provide a push- pull output in which output current is either sup- plied or withdrawn.

In accordance with a further aspect of the inven- tion, means are provided for periodically resetting the integration means to an initial state suitable for initiating the succeeding integration In addition, means are provided for periodically nulling the output current of the transconductance amplifier means, the nulling being timed to occur after the instant for commutation, but prior to resetting the integration means The nulling means comprises means for incrementing the offset current of the current mirror to a value which corrects imbalance and sustains the corrective offset current until null- ing again occurs.

More particularly, the nulling means comprises means for zeroing the differential input voltage ap- plied between the inputs of the transconductance amplifier means and for establishing a desired out- put current level in the first and second transistors of the input stage amplifier, output switching means for disconnecting the output of the tran- sconductance amplifier means from the integration means during the nulling interval, and a nulling comparator coupled to the output of the transcon- ductance amplifier means for detecting a change in sense of the output current, as the amplifier goes through balance to terminate the incrementing process and initiate resetting the integration means.

More particularly, the offset current incrementing means comprises means for supplying a clocking single (e g 20 Khz) having a period which is short in relation to the commutation period and a nulling counter counting at the rate of the clocking signal.

The state of the nulling counter controls the sum of the increments of offset current, and is preset in response to the timing signal Subsequent count- ing during nulling adjusts the current offset toward balance until a null is detected by the nulling com- parator.

In accordance with a further aspect of the inven- tion, a low voltage DC supply is provided suitable for operation of the control circuit, the voltage of the supply changing at a finite rate when power i's turned on or turned off A protection circuit is pro- vided for producing an active output responsive to the voltage of the low voltage DC supply for holding at least a portion of the control circuit in an in- active state when the voltage is below a first value when power is turned on or below a second value when power is turned off When the voltage has exceeded the first value as power is turned on, the circuit portion is released q a predetermined state.

The voltage values are set such that normal circuit operation is assured at supply voltages exceeding the first and second values.

Preferably, the protection circuit, upon termina- tion of the active output as power is turned on, re- leases the circuit "portion" in a state to null the amplifier means to insure balance of the output current of the amplifier means before integration of its output current The protection circuit during.

said active-output, presets the nulling counter, and upon termination of the active output, as power is turned on, releases the circuit portion in a state for nulling the amplifier means The state for nulling comprises activation of the zeroing means at the input of the tranconductance amplifier means, acti- vation of the amplifier output switching means for disconnection, and the release of the nulling counter.

The protection circuit further comprises means to cause a starting offsetin the output current of the amplifier means to insure integration of the output current to a voltage sufficient for generating the commutation timing signal, the starting offset current, except during said nulling interval(s) ex- tending over a sufficient period after power is ap- plied to allow for control circuit stabilization This period is typically five commutation periods.

In accordance with a further aspect of the inven- tion a novel method of timing the commutation of an electronically commutated motor is disclosed, the principal steps of which comprise converting the differential voltage appearing in the unener- gized winding stage to a corresponding bidirectional output current by means of a two input solid state differential transconductance amplifier means, integraging the output current to obtain an output voltage substantially proportional to an in- tegral of the differential voltage; and comparing the output voltage of the integration means to a value corresponding to the angular position of the rotor suitable for commutation, and upon sensing equality, generating a timing signal at the instant for commutation.

Subsequent steps of the timing method com- prise resetting the integration means to an initial state suitable for initiating the succeeding integration subsequent of each timing signal, and periodi- cally nulling the output current of the transconductance amplifier means.

In a preferred method of operating an electroni- cally commutated motor, in which a differential transconductance amplifier is used for timing the instant for commutation, the steps comprise null- ing the amplifier means upon turning on power for the control circuit prior to turning power on for the motor Then the differential voltage appearing in the unenergized winding stage is converted to a corresponding bidirectional output current, inte- grated to obtain an output voltage, and compared to a stored value for generating a timing signal at the instant suitable for commutation After a delay, power is applied to the motor in response to the next or a subsequent timing signal, selected to al- low adequate time for the control circuit to stabi- lize Next the integration means are reset to an initial state suitable for initiating the succeeding integration, which occurs subsequent to each timing signal Thereafter the output current of the tran- sconductance amplifier means is periodically nulled.

According to a further aspect of the invention, the above objects are achieved in a motor speed or torque control circuit for an electronically commu- tated motor adapted to be energized from a power 6 GB 2177559 A source, the motor having a multistage winding as- sembly, and a magnetic assembly, the two ar- ranged for mutual relative rotation, the motor in a given state of a multistate energization sequence having an unenergized winding stage in which an induced back emf is integrated over time to deter- mine the instant at which the mutual relative angu- lar position has been attained suitable for commutation to the next state, and wherein in said given state, at least one other winding stage is en- ergized in the appropriate sense to cause relative rotation.

An inventive combination in the control circuit comprised power input terminals for connection to a supply suitable for motor operation; a waveform generator for supplying a repetitive low voltage waveform of substantially constant repetition rate, amplitude and configuration, the characteristics being substantially free of dependence on said mo- tor, the waveform having a first slope of a first du- ration and a second slope of a second duration and of opposite sense to said first slope, and a repetition rate which is high in relation to the com- mutation rate; means for producing a substantially smooth adjustable control voltage; a modulating comparator having a first input to which said re- petitive voltage waveform is supplied and a second input to which said adjustable control voltage is supplied, to produce output pulses when intersec- tions occur between said inputs said output pulses occurring at said constant repetition rate, having an "active" on time equal to the interval between alternate pairs of intersections; and control logic means responsive to the "active" on time of said modulator pulses for providing pulse width modu- lated signals for control of the energization of the winding stages in the multistage energization se- quence In operation, adjustment of the control voltage, adjusts the active on time of each pulse and thereby the rate at which electrical energy is supplied to the motor for determination of the mo- tor speed or torque.

The repetitive voltage waveform is preferably a saw tooth waveform, having a repetition rate above 20 Khz The adjustable voltage is smooth in relation to the motor commutation rate and in rela- tion to the repetition rate of the repetitive voltage waveform The inputs supplied to the modulating comparator are selected in the preferred case to produce an output waveform which at one limit of adjustment is substantially always on, at the other limit is substantially always off, and at intermedi- ate adjustments is pulsed rectangular waveform of variable width.

A second means of variable speed or torque control is provided by an adjustable voltage reduc- tion means serially connecting the motor to the power supply This voltage reduction means in the power circuit is preferably used in concert with the adjustable control voltage affecting the active on time of the pulse width modulation pulses used to control the application of power to the motor.

In a preferred embodiment, the adjustable volt- age reduction means, is independent of the adjust- able control voltage to produce a first reduction in motor speed or torque, but for further reductions, means are provided to make the adjustable control voltage applicable to the pulse modulator depend- ent upon its reduced voltage for powering the mo- tor This brings about a joint reduction in both the voltage and duty cycle of the PW Med energy sup- plied to the motor This permits a full range of speed or torque control down to stalling speed, with a smaller reduction in motor voltage, and per- mits the reduced voltage to remain large enough at all times to sufficiently power the control circuit.

In accordance with a further aspect of the inven- tion, a novel method of controlling the speed or torque of an electronically commutated motor is disclosed The steps entail providing a variable output voltage suitable for variable speed or varia- ble torque motor operation by means of an adjust- able voltage reduction means serially connecting the motor to the power source, generating a repet- itive low voltage sawtooth waveform of substan- tially constant parameters; providing an adjustable substantially smooth control voltage for motor speed or torque controls comparing the repetitive voltage waveform to said adjustable control volt- age in a modulator to produce output pulses when intersections occur between said inputs, the output pulses occurring at the repetition rate of the sawtooth waveform and having an "active" on time equal to the interval between alternate pairs of in- tersections; applying energy from the power source to the motor during the active on time of the modulator pulses, and adjusting only the varia- ble output voltage for a small reduction in motor speed or torque, and for a further reduction simul- taneously adjusting the variable output voltage and the control voltage for motor speed or torque con- trol.

According to still another aspect of the invention, the above objects are achieved in a motor control circuit for an electronically commutated motor adapted to be energized from a power source, said motor having a multistage winding assembly and a magnetic assembly, the two arranged for mutual relative rotation In a given state of a multistate energization sequence, the motor has an unener- gized winding stage in which an induced back emf is integrated over time to determine the instant at which the mutual relative angular position has been attained suitable for commutation to the next state of the sequence In each state of the sequence at least one other winding stage is ener- gized in the appropriate sense to cause relative rotation In the practical example herein treated, one sequence is designed for clockwise operation and a second sequence for counter clockwise oper- ation.

The control circuit combines a first adjustable voltage reduction means for serially connecting the motor to the power supply to provide a variable output voltage suitable for variable speed or torque operation; with means for producing a sub- stantially smooth control voltage, dependent on the variable output voltage The control voltage, upon passing through an intermediate value corre- sponding to a useful limit of the adjustable means, GB 2177559 A 7 continues monotonically toward a final value.

Means are provided responsive to a value of said control voltage between the intermediate and final values for generating a signal for control of the di- rection of motor rotation.

Preferably, the intermediate value of control volt- age corresponds to the desired minimum motor speed or torque, typically when the motor stalls in a ceiling fan application, and the change in direc- tion occurs past stalling toward the minimum out- put voltage.

In accordance with a further facet of the inven- tion, the rate of downward adjustment of energy per unit change in output voltage is enhanced by means of a pulse width modulator also responsive to the control voltage The pulse width modulator produces output pulses of constant rep-tition rate, the repetition rate being high in relation to the commutation rate, but with variable on times un- der the control of the control voltage The energy, which is supplied to the motor during the active on times of the pulses, is thus reduced when a reduc- tion in output voltage occurs, both by virtue of the voltage reduction, and by virtue of a reduction in the average time that the voltage is applied (i e, the width of the PW Med pulses controlling energy supplied to the motor are concurrently reduced).

In effecting the desired range of speed or torque control, with a higher voltage at the minimum de, sired setting (i e, the motor stall setting) it be- comes possible to energize the control circuit through a voltage dropping network connected in parallel with the motor circuit This then facilitates remote control operation, in that a simple wall control can achieve full range control of the motor speed or torque, and at the minimum setting effect a reversal also remote.

In the preferred embodiment, the motor direction control logic has two outputs, one for facilitating forward operation (clockwise rotation) by means of an active high in the output state, and the other fa- cilitating reverse operation (counter clockwise rotp- tion) by means of an active high in the output state The internal logic precludes the output states from being active simultaneously, and when a state is changed, delaying the appearance of the new active state, after discontinuance of the prior active state, by a time long enough to protect the power switches This period is typically in excess of the period of one pulse of the modulator.

The motor direction may be controlled by a switch coupled to the direction control logic, and normally on the fixture incorporating the fan This switch, in accordance with a further facet of the in- vention functions with a protective circuit active during power up and power down to determine the motor direction when power comes back on after an interruption.

In accordance with a further aspect of the inven- tion, a novel mothod of controlling an electroni- cally commutated motor is disclosed The steps entail reducing the output voltage supplied to the motor through a range of values suitable for varia- ble speed or torque operation, producing a sub- stantially smooth control voltage, dependent on the variable output voltage, the control voltage, upon passing through an intermediate value corre- sponding to a minimum useful reduction, continu- ing monotonically toward a final value, and generating a signal for changing the direction of motor rotation at a value of the control voltage be- tween said intermediate and final values.

In accordance with a further aspect of the inven- tive method the rate of downward adjustment of energy per unit change in output voltage supplied to the motor is enhanced and the range of voltage reduction required for the desired minimum setting (e.g, motor stalling) reduced by means of a pulse width modulator The pulse modulator, produces output pulses whose "on" time also controls the rate at which energy is supplied to the motor.

As a further variation of the inventive method, the generation of a signal for motor reversal en- tails first generating a signal for suspending the energization for motor rotation in one sense, and after a short interruption for protection of the mo- tor switches, generating a signal for motor rotation in an opposite sense.

Brief description of the drawings

The novel and distinctive features of the inven- tion are set forth in the claims appended to the present application The invention itself, together with further objects and advantages thereof, may best be understood by reference to the following description and accompanying drawings described below.

Figure 1 is an illustration of the installation of a ceiling fixture combining a fan and a light, and in- cluding manual controls, the ceiling fan being de- signed to be driven by an electronically commutated dc motor.

Figure 2 is a wiring diagram of the electronic cir- cuitry providing electronic commutation of the fan motor and giving effect to the manual controls.

More specifically, Figure 2 is a wiring diagram of a printed circuit board, including the interconnec- tions with the fan motor, the ceiling light, the man- ual controls and a custom integrated circuit for motor control.

Figure 3 illustrates the control and commutation waveforms of the motor control integrated circuit.

Figure 4 is a block diagram of the principal func- tional subdivisions or blocks of the motor control integrated circuit and the functional interconnec- tions between said functional blocks Figures 5 A, 6, 7, 9, 1 OA and 11 A are logic diagrams and/or circuit diagrams of the functional blocks for the motor control integrated circuit.

Figure 5 A is a logic diagram of the Input Gating and a circuit diagram including device parameters of the Integrating Transconductance Amplifier blocks of Figure 4 Figures 5 B, 5 C and 5 D are sim- plified electrical circuit descriptions of the Integrat- ing Transconductance Amplifier Figure 5 B illustrates a slightly extended and slightly simpli- fied circuit of the Integrating Transconductance Amplifier including the input connections to an ex- emplary winding stage and the nulling resistances also treatable as a part of the Autonull circuit; Fig- 8 GB 2177559 A ure 5 C illustrates an equivalent circuit representa- tion of the Integrating Transconductance Amplifier (without feedback); and Figure 5 D illustrates the equivalent circuit representation of the Amplifier employing series current feedback for stabilizing the amplifier transconductance, a mode of feed- back comparable to that herein employed.

Figure 6 is a logic diagram of the Comparator Network and of the Modulo 6 Counter blocks of Figure 4.

Figure 7 is a circuit diagram including device pa- rameters in part and a logic diagram in part of the Autonull Circuit block of Figure 7.

Figure 8 is the output waveform of the Integrat- ing Transconductance Amplifier for a single com- mutation period The waveform illustrates the time allocated between integration and reset of a capac- itor used to time the commutation instant and the nulling of the Amplifier.

Figure 9 is a logic diagram of the Control Logic and Output Drivers blocks of Figure 4.

Figure 10 A is a combined circuit and logic dia- gram of the oscillator, Pulse Width Modulator and the Forward/Reverse Logic blocks of Figure 4 Fig- ure 10 B are waveforms explanatory of operation of the Pulse Width Modulator block; Figure 10 C is a plot of the effect of manual operation of the wall control upon motor speed and direction of rota- tion; and Figure 10 D is a simplified showing of a switchable wall control for motor speed and direc- tion.

Figure 10 E is a block diagram illustrating an open loop pulse width modulationmotor control arrangement according to the invention.

Figure 1 OF is a detailed representation of one of the motor control waveforms in Figure 3.

Figure 11 A is a circuit diagram including device parameters in part and a logic diagram in part for the Power On Reset block of Figure 4; Figure 11 B is a graph illustrating the setting of the release voltage of the Power On Reset block.

Figures 12 A and 12 B contain the principal inter- nal waveforms incident to operation of the motor control integrating circuit Figure 12 A deals with commutation and balancing of the Integrating Am- plifier for an exemplary commuttion period; and Figure 12 B deals with overall operation during the power on sequence.

Description of the preferred embodiment

Combined lamp and ceiling fan fixture using elec- tronically commutated dc motor Referring now to Figure 1, an installation of a combined lamp 100 and ceiling fan 101 fixture is shown, together with the appropriate manual con- trols The fan motor, which is housed in housing 102, is, in this embodiment, an electronically com- mutated dc motor (ECM) driving the 4-bladed fan.

A stationary assembly of the motor comprises a ferromagnetic stator having a multi-stage winding arrangement associated therewith which includes a plurality of stages, each in turn formed of a plural- ity of coils inserted into a plurality of slots spaced about a core of the stator A rotatable assembly of the motor is arranged in selective magnetic coupling relation with the winding stages of the stator and comprises a rotor having a plurality of perma- nent magnet elements disposed thereon.

Although a specific ECM is illustrated herein for purposes of disclosure, it is contemplated that other types of EC Ms having various other constructions and electrical characteristics may be uti- lized within the scope of the invention For example, some of the EC Ms which may be utilized are disclosed in U S Patent Nos 4,005,347 and 4,169,990 to David M Erdman, and U S Patent No 4,162,435 to Floyd H Wright.

The connections to the motor traverse a hollow shaft in the motor permitting a stationary tube to carry wires between a conduit pipe 103, mounted on the upper surface of the motor housing 102 and a control box 104 supported upon the under sur- face of the housing The conduit pipe 103 may be used to carry wires to a connection box (not shown) mounted on the ceiling The conduit pipe 103 may also support the fixture The control box 104 contains the control circuitry for the operation of the motor, including three manually operated controls The lamp assembly 100 is supported on the under surface of the control box 104 The con- trol circuitry is supported upon a circular printed circuit wiring board, fitted within the control box.

The controls for the fixture include a three-way switch 52, operated by a pull chain, for mode se- lection, a forward-reverse slide switch 51, and a speed adjusting potentiometer R 40 The mode se- lection switch permits four modes: fan on; lamp on; fan and lamp on; and fan and lamp off The ceiling fixture is energized from a 115 V ac main, connected in series with a wall mounted control which also contains manual controls.

In the example, the wall control includes manual controls for both fan and motor These also include an on and off switch for the fixture, a motor speed, forward/reverse control, and a lamp dimmer.

The control circuitry for operation of the ceiling fixture is illustrated in Figure 2, which is a wiring diagram of the Figure 1 installation Figure 2 con- tains as its principal features, the lamp 100, the three winding stage motor 120, the wall control 105, the wiring mounted on the printed circuit board, which includes as five major features, a mo- tor control integrated circuit 121, three principal solid state switches 122, 123, 124 and a four sec- tion, precision resistance voltage divider 125 In addition to these five principal features, the printed circuit board includes the circuit element for sup- plying power to the lamp, the motor, the motor control IC, and the timing and the manual controls coupled to the integrated circuit.

Operation of the fixture takes place in the follow- ing manner The lamp receives power during "po- sitive" half cycles of the ac main Lamp (only) operation takes place when the three-way mode selection switch 52 is rotated to the lamp only po- sition Let it be further assumed that the wall con- trol is "on" providing a low resistance bi- directional current path between its two external terminals Assuming that the 115 V ac main is ener- gized, ac current follows a path from the first ac GB 2177559 A 9 terminal 126, via the wall control 105, the de- mountable connector E 4, the lamp 100, the de- mountable connector E 2, the anode first and the cathode second of diode CR 4, the demountable connector El, the switch 52, and finally the second ac terminal 127.

The motor and the IC receive power during "negative" half cycles of the ac main Assuming that switch 52 is rotated to the motor only, or mo- tor and fan on position, current from terminal 127 progresses via the switch 52, the connector E 5, to a 150 V dc power supply, consisting of a fuse Fl, a current limiting resistance R 22, a diode CR 5, and a filter capacitor Cl connected between the cathode of the diode CR 5, and the common ground connec- tion of the supply The transistor switches 122, 123, 124 each have a power input terminal connected via a protective network (Li, CR 12, CR 13) to the + volt bus of the dc supply originating at the cathode of diode CR 5, and a load terminal con- nected respectively via the connectors E 6, E 7 and E 8 to one end of the motor winding stages A, B and C respectively The other ends of the motor winding stages are connected to a neutral node 128, which is not an external connection point for motor energization The switches A, B and C, which are identical, operate with one switch (for instance A) conductive high, another (for instance B) conductive low, and the third switch (C) in a high impedance (non-conductive) state In this in- stance, current flows from the 150 V B+ bus via switch 122, connector E 6 into the winding A, via the winding node 128 into winding B, into the con- nector E 7, via switch 123 to the common ground.

The common ground, also the negative terminal of filter capacitor Cl is returned via connector E 4, and the wall control 105 to the other terminal 126 of the ac main As has been indicated, power is sup- plied to the motor 120 and the motor control IC 121 only during the negative half cycle of the ac main because of unidirectional conduction by the diode CR 5 Power is supplied to the lamp only dur- ing the positive half cycles of the ac main because of the unidirectional conduction of the diode CR 4.

The motor control IC 121 receives its power (Vdd) at the output of the protective network (Li, CR 12, CR 13) via a voltage dropping resistor R 23, a filter capacitor C 2, and a voltage limiting zener diode CR 1, which is coupled to the pad P 13 The IC ground (Vss) is returned via the pad P 6 to the sys- tem ground, to which the capacitor C 2, and the ze- ner CR 1 are also returned The arrangement provides an approximately + 9 0 volts Vdd potential for operating the IC The IC is manufactured of sili- con using a complementary (C) metal oxide semi- conductor (MOS) process The CMOS process readily produces P-channel field effect transistors (FE Ts), N-channel field effect transistors, single diodes, and resistances.

The control IC provides the appropriate output - signals to commutate the three winding stage mo- tor 120, and effectuates control over the motor giv- ing effect to the manual controls in the motor mounted control box 104 and in the wall control 105 The IC derives the timing information used for commutation from the individual winding stages of the motor, the non-energized winding being sensed for back emf, to define the instant for com- mutation The ends of the winding stages A, B and C, including the winding node 128, are connected respectively via the connectors E 6, E 7, E 8 and E 3, to one end terminal of each of four separate, preci- sion, two resistor voltage dividers The other end terminal of each divider is interconnected at node 129 and returned via two series connected, forward sensed diodes CR 2 and CR 3 to ground The diodes are shunted by a filter capacitor C 3 A resistance R 28 connects the node 129 to the B+ output at CR 5, C 1 The taps on the four voltage dividers, which are set at a division ratio of 1 to 41, are cou- pled respectively to the input pads of the motor control IC labeled P 5 (VA); P 4 (VB); P 3 (VC); and P 2 (VN) The voltage division ratio is designed so that the voltage swing about neutral (VN) at the IC inputs does not exceed the input capabilities of the motor control IC The foregoing configuration, which is used for sensing the back emf in the mo- mentarily non-energized winding stage, allows the voltage on the neutral winding node 128, which ideally equals half the apparent B+ supply, and which is also divided down to 1 part of 41 to form a reference voltage (VN) The voltages VA, VB or VC referenced to the voltage (VN) form a suitable signal for application to the differential input of the IC.

For assured starting in the face of error in the Single In-line Plastic (SIP) resistance matrix 125, a discharge mechanism (Q 92, R 41) at Pl for capaci- tor C 5 is provided, which still maintains an essen- tial minimum time constant of 0 20 sec The collector of Q 92 is connected to P 1, the emitter via R 41 ( 240 K) to system ground, and the base to node 129 so as to provide a 2 1/2 pa current drain at P 1 The selection provides a starting period of 0 25 seconds and a margin for a 2 p La system error.

The offset error in timing becomes negligible at medium and high rpms.

The switches 122, 123 and 124 are designed to respond to control signals supplied by the IC at the pads P 7 (AT); P 8 (AB); P 9 (BB); P 10 (BT); P 11 (CT); and P 12 (CB) The initial letters, A, B and C desig- nrte the winding stage of the motor 120 The sec- ond letter "T" denotes that "on" signals from the pads so designated on the IC will produce switch conduction of the + 150 volt bus (T for Top) in rela- tion to system ground potential or to a point + 75 volts in relation to the voltage on the neutral wind- ing node 128 The second letter "B" denotes that "on" signals from the pads so designated on the IC will produce switch conduction to system ground (B for Bottom) or to a point -75 volts in relation to the voltage on the neutral node.

The circuit of the switch 122, which controls the A winding of the motor, is shown in Figure 2 It comprises three bipolar transistors Q 82, Q 88, Q 85, which function to couple the non-neutral terminal of winding A terminal to B+ when AT at P 7 is high and a single FET Q 91, which functions to couple that winding terminal to system ground when AB at P 8 is high The switches represent a low cost GB 2177559 A design, with the base of the input NPN transistor Q 82 being coupled to the pad P 7, and the emitter connected via R 37 to ground The signal appearing at the collector of Q 82 is developed in the load re- sistor R 31, serially coupled via the protective diode CR 6 cathode first, anode second to the 150 V B+ bus A PNP transistor Q 88, connected in the emit- ter common configuration, has its base connected to the collector of Q 82, its emitter coupled to the cathode of diode CR 6 The collector of Q 88 is connected to the base of the NPN output transistor Q 85, and via a collector load resistance R 34 to the emitter of Q 85 The collector of Q 85 isconnected via diode CR 6 to the + 150 volt bus The emitter of Q 85 is coupled via connector E 6 to the A winding stage Transistor Q 88 serves to shift the level and provide the correct sense for driving the output transistor Q 85 The diode CR 9, which has its anode coupled to the emitter of Q 85, and its cathode cou- pled to the B+ output at CR 5, C 1, is a flyback diode, reducing the inverse switching transients.

The Q 82, Q 88, 085 combination provide a low re- sistance, high current capacity connection of wind- ing stage A to the + 150 V bus when the voltage AT at pad P 7 goes to an active high.

The field effect transistor Q 91 is an N-channel device, which couples winding stage A to system ground The gate of Q 91 is coupled to pad P 8, the source is connected to system ground, and the drain is connected to the emitter of Q 85, and via connector E 6 to the non-neutral terminal of wind, ing stage A Transistor Q 91 provides a low resist- ance, high current capacity connection of winding stage A to the system ground when the voltage A 8 at pad P 8 goes to an "active" high The high cur- rents under discussion are those appropriate for a watt fan motor.

The inductor L 1, as a part of the protective net- work (L 1, CR 12, CR 13), prevents the extremely high switching current peaks which would stress the solid state power switches In this application, the problem is more acute in the bottom rank FE Ts (Q 91 in switch A, or the counterparts of Q 91 in switches B and C) These peak currents would ordi- narily occur when selected upper rank bipolar tran- sistor switches (Q 85 in switch A, or the counterparts of Q 85 in switches B and C) are turned on, while the current from the motor is flowing in the diode portion of the FET (drainsource connection) The recovery of this "diode" (structurally the base-collector junction of a bipolar transistor inherent in the FET) determines this cur- rent and the "safe" recovery of the device.

The two serially connected diodes CR 12 and CR 13 shunt L 1, so that the voltage transients ap- pearing on the 150 V bus will be clamped to the main filter capacitor C 1 Therefore, the B+ connec- tion to these switches will not fly back significantly above the B+ voltage established by the filter ca- pacitor For the circuit to be effective, one of the diodes (e g CR 12) should be a fast recovery diode.

The protective circuit protects against the "shoot thru" current mentioned above, during PWM switching, which could otherwise result in danger- ously high peak currents in both ranks of the tran- sistor switches.

An alternative protective scheme for the lower rank FE Ts is to use two diodes, one connected be- tween the drain and the system ground in shunt with the lower rank FET (e g Q 91), the diode being poled to conduct when the FET is back-biased, and a second diode inserted in the drain poled to con- duct when the FET is forward biased.

As the drawing of the switch implies, if both pads P 8 and P 7 are low, the switch A is in a high impedance state, or non-conductive state, with the non-neutral lead at the winding stage A, now une- nergized, free to reach whatever value is produced by the back emf as the winding stage A is sub- jected to the field produced by the rotating perma- nent magnet rotor.

The sequence in which switching occurs is shown in the commutation waveforms of Figure 3.

The waveforms available at the pads P 7-P 12 on the IC for control of the switches 122, 123, 124 are the six lowermost waveforms (AT, AB, BT, etc), with those to the left representing FORWARD motor ro- tation and those to the right representing REVERSE motor rotation The two waveforms denoted the "FOR" for forward or "REV" for reverse waveforms are internally generated on the IC, and are affected by the setting of SPDT 51, connected to the FOR/ REV pad P 16, and the wall control With the IC in a Forward state, (FOR active high), the switching waveforms allow a first sequence from the left margin to the center of the drawing Should the forward signal go low and the reverse signal go high, the switching signals will resume a second sequence.

The Commutation Output Waveforms or ener- gized winding selection signals, occur in a se- quence of 6 waveforms (AT, AB, BT, BB, CT, CB) for energization of the winding stages A, B or C.

The "highs" of each waveform (for purposes of ini- tial discussion, the vertical markings under highs on the waveform, which denote duty cycled opera- tion, are ignored) have a duration of two counts of the least significant bit (BO) of a three-bit (BO, B 1, B 2) Modulo 6 Counter The motor, taken as a whole, has 6 distinctive energization states, in each of which one winding (A, B or C, e g A) is con- nected to B+, one remaining winding (B or C, e g.

B) is connected to ground, and the remaining winding (e g C) is not energized Each motor ener- gization state lasts for one count of the least signif- icant bit (BO) of the Modulo 6 Counter, and each motor energization state ends by definition at the commutation instant.

The commutation output waveforms, as will be described, are logically derived from the counts (BO, B 1, B 2) of three flip-flops in the Modulo 6 Counter which lead to six counter output states CSO, C 51, C 52, C 53, C 54, C 55, (the overlining de- noting that the low is active) The counter output waveforms (CSO, etc) are used to derive the com- mutation output waveforms and are unenergized winding selection signals used for selecting the unenergized winding at the input of the control IC for commutation sensing.

The order of active lows of the CSO-C 55 wave- GB 2 177559 A 11 forms to the left of the margin ascend to the right (from CSO to C 55 before reversal, and descend to the right (from C 55 to CSO) after reversal The BB and CT waveforms are undefined until the POR (power on reset) goes to an inactive high, releasing the counter from the CSO state (BO= O; Bl = O; B 2 = 0) At the next count, CSO goes high and C 51 goes low, AB goes on, BB and BT are off, and CT continues on At the next count, C 52 goes low, AB stays on, BT goes on and CT and CB are off The described sequence of winding energizations con- tinue to the center of the figure until FOR goes low, at which the sequence reverses as illustrated.

The production of the correct sequence of switching waveforms to produce forward rotation, reverse rotation, or faster or slower motor rotation, and to commutate the stator assembly at the cor- rect angular position of the rotor is the function of the motor control IC 121, whose internal design will now be described.

Motor control IC 121 for electronically commutated dc motor The principal functional subdivisions of the mo- tor control IC 121 are shown in Figure 4 The de- tailed logical and/or circuit designs of the functional blocks are shown in Figures 5 A, 6, 7, 9, A and 11 A.

The control IC consists of 11 interconnected blocks 140 and 150 interconnected to the circuitry on the printed circuit board by the 16 pads Pl to P 16 as already noted The rotational position of the rotor is "identified" by the Modulo 6 or Commuta- tion Counter 144, which has six states (C 50-C 55).

The permanent magnet rotor, due to magnetic coupling rotates in synchronism with the rotation of the magnetic field produced by the stator as- sembly Depending on the number of "poles" of the motor, the count may repeat once, twice, three times, four times, etc per revolution The actual embodiment herein described employs a 6 pole permanent magnet rotor with an 18 coil, 3 winding stage, 36 "tooth" stator assembly The 6 count is repeated three times per revolution.

The Modulo 6 Counter 144 controls the sequen- tial switching of the Output Drivers 146 for sequen- tial energization of the winding stages, and for the sequential enabling of the Input Gate 140 for se- lecting the appropriate unenergized winding for commutation timing The Counter is subject to control for a forward or a reverse count by means of the Forward waveform (FOR) derived from the Forward/Reverse Logic 149 When power is first applied, the Counter is held in a preset state by means of the Power On Reset waveform (POR) de- rived from the Power On Reset Waveform 150 The commutation instant for the electronically commu- tated motor is defined by means of the positive going edge Reset 1 waveform supplied by the Comparator Network 142 to the Counter 144 The Reset 1 waveform "clocks" the Counter 144, thus defining the instant that the energization stage of the rotor changes and the instant that the winding stage being sensed for commutation timing is changed.

The Modulo 6 Counter 144 controls the energiza- tion sequence of the winding stages A, B and C by means of the Control Logic 145, the Output Drivers 146, and the switches 122, 123, and 124 The out- put from the Counter 144 in the form of six NAN Ded combinations of adjacent counter states (CSO, C 51, C 51, C 52; etc) and the least significant bit (BO) of the counter memory is coupled to the Control Logic 145 The Control Logic 145, decoding the outputs from Counter 144, derives high or low control signals for application to the six individual drivers, which make up the Output Drivers 146.

The Control Logic 145 is subject to control for a forward or a reverse count by means of the FOR- WARD Waveform (FOR) and the REVERSE Wave- form (REV) derived from the FORWARD/REVERSE Logic 149 It is also subject to a control which in- verts the sense of the driver output on alternate counts This inversion is achieved by means of the BO waveform derived from the least significant bit of the Counter memory, and NO Red with the RE- SET 1 waveform derived from the Comparator Net- work 142 The Control Logic, by means of the PWM Output Waveform derived from the Pulse Width Modulator 148, effects a pulse width modu- lation of a 20 K Hz oscillation from Oscillator 147, which affects the conduction duty cycle of the out- put drivers in the manner indicated in the vertically lined areas of the driver waveforms (AT, AB, etc) of Figure 3.

The Output Drivers 146 to which the waveforms (AT, AB, etc) are applied provide signal gain at the pads P 7-P 12 of the Motor Control IC adequate to drive the separate switching transistors in the solid state switches 122, 123, 124 on the printed circuit board The output drivers 146 by means of the I start waveform derived from POR 150, defer the actual application of power to the motor windings until 5 commutation intervals have taken place after power is initially turned on This allows the commutation timing circuitry to stabilize before the actual application of power to the windings.

The Modulo 6 Counter 144 sequentially enables the Input Gating 140 for selecting the appropriate unenergized winding stage for connection to the Integrating Transconductance Amplifier 141 and Comparator Network 142 for commutation timing.

In timing the commutation, the back emf devel- oped in the unenergized winding stage (as a result of rotation of the permanent magnets on the rotor past the stationary, un-energized winding stage) once selected by the Input Gating 140, is amplified in the Amplifier 141, and integrated and measured in the Comparator Network 142 to determine the correct commutation angle The selection of the appropriate unenergized winding stage by the In- put Gating 140 is synchronized with the selection of the other two of the three winding stages by the Control Logic 145 for energization.

The Input Gating 140 is coupled via pads P 2-P 5 to the voltage divider matrix in the printed circuit board connected to the non-neutral terminals of each of the three motor stator winding stages (A, B, C) and to the neutral terminal for selection of the appropriate timing information The Modulo 6 12 GB 2 177559 A Counter controls the Input Gating 140 in identifying and selecting the stator winding stages which are unenergized, by providing the six counter output waveforms (C 50, C 51, etc) to the enabling inputs of the Gating, which have an active low when the Gating should be enabled The output of the Input Gating is connected to the input of the Integrating Transconductance Amplifier 141, which has two differentially connected inputs The Input Gating selects a single identified unenergized winding stage taking one input (e g VA) from the non-neu- tral terminal of the winding stage, and one input (e.g VN) from the neutral winding node 126 The counter stages (C 50, C 51, etc) are assigned to cause alternation of the sense of the connections between the non-neutral terminals of the winding stages and the Amplifier inputs on successive counts The alternation of the connection sense be- tween the common neutral terminal and the Am- plifier inputs is achieved by means of the least significant bit (BO) derived from the Counter mem- ory.

This alternation by the Input Gating 140 of the sense of the connection between the winding stages and the Integrating Amplifier 141 is necessary to insure that the polarity of the Amplifier out- put is always the same The waveform of the back EMF appearing on one winding stage has a first slope (e g positive) while the waveform of the next winding stage for the next period of integration has an opposite slope The inversions produced by the Input Gating thus keep the sense of the Ampli- fier output the same for successive integration pe- riods.

The Input Gating 140 is thus the input switching means of the IC which couples the back EMF wav- eform via the matrix 125 from the winding stage.

This waveform, which indicates the instantaneous angular velocity of the rotor is next coupled to the blocks 141, 142, 143 for integration to obtain the angular translation of the rotor These blocks, and more particularly the Comparator Network 142 (in- cluding C 5), produce an output pulse, i e the Reset 1 pulse, at the instant the correct rotor angle for commutation has been reached The Reset 1 pulse is used to clock the Modulo 6 Counter 144 The Re- set 1 waveform is also coupled to disable the Input Gating during the nulling of the Amplifier 141 and during resetting of the integrating capacitor (C 5), connected to the Comparator Network 142.

The Integrating Transconductance Amplifier 141 is a difference amplifier to the two inputs of which the signal from the selected winding stage in the form of a voltage are differentially applied The in- tegrating Transconductance Amplifier 141 converts the differentially applied input voltage to an output current which is integrated in the Comparator Network 142 in determining the correct commutation angle The output current from the Amplifier is coupled to an integrating capacitor C 5 coupled to pad P 1 Capacitor C 5, in storing the Amplifier out- put current, develops a voltage derived from the selected unenergized winding stage, which is an appropriate means of determining the instanta- neous rotor angle The voltage integral is a meas- ure of the angular position of the rotor which is substantially independent of the rate of rotation of the rotor over a 10/1 range of rotational rates The voltage appearing on the capacitor C 5 as a result of integrating the Amplifier output current provides an accurate duplication of the voltage integral to the extent that the Amplifier output current is pro- portional to the differential input voltage and to the extent that a time integral of the Amplifier output current is equal to the time integral of the input voltage The voltage integrated by the capacitor C 5 is then compared with a standard voltage (Vref 3) corresponding to a known optimum rotor commu- tation angle to determine the instant that commu- tation should take place.

The accuracy of this method of rotor angle deter- mination depends on the stability of the transcon- ductance of the Integrating Transconductance Amplifier, and, since the Amplifier is a direct cou- pled difference amplifier susceptible to imbalance, it also depends on the accuracy with which any imbalance may be compensated.

The output of the Amplifier 141 is coupled to a Comparator Network 142, which detects when the voltage stored in the capacitor C 5 as a result of current integration has equaled the standard volt- age corresponding to the correct angular position of the rotor for commutation When equality is sensed, the Comparator Network signals (RESET 1), the commutation instant to the Modulo 6 Counter 144 Upon this signal, the Counter ad- vances to the next count, and the Input Gating 140 and Output Drivers 146 are advanced to implement the commutation and commence the energization, de-energization and voltage sensing for the three winding stages appropriate to the next count.

The third block active in commutation timing is the Autonull Circuit 143, which provides an offset to correct any imbalance in output current of the Integrating Amplifier "Nulling" of the Integrating Amplifier occurs on each commutation As illus- trated in Figure 8, nulling takes place after the ca- pacitor integration period has ended, signaled by the RESET 1 pulse, but before the timing capacitor (C 5) is reset (during RESET 2) preparatory to the next capacitor integration period The Amplifier 141 is placed in a condition to be nulled, and then causes reset of the integrating capacitor by the ap- plication of the RESET 1 and RESET 2 waveforms, respectively The RESET 1 waveform shorts the dif- ferential input of the Amplifier, and thus provides a zero differential input signal essential to nulling.

The Reset 2 waveform is active after nulling, and sets the amplifier output into a state in which the integrating capacitor (C 5) is rapidly recharged to- ward Vdd In addition, during nulling, certain con- trols are applied to the resistance R 3 A-D and R 4 A- D, which for certain purposes, form a portion of the Amplifier These will be discussed in connec- tion with the Autonull Circuit.

The nulling of the Amplifier 141 produces a pe- riodically verified current offset which is applied to one amplifier channel to null the amplifier output current for a zero input signal The Autonull Circuit 143 produces this offset current in small ( 3/4 p A) in- G 1 B 2 177559 A 13 crements which are applied to a current offset one channel of the amplifier The increments are de- signed to raise or lower the current transfer ratio of a mirror in one channel of the Amplifier to bring the output current of that channel into balance with the output current of the other channel The nulling takes a small time, typically less than a millisecond, but not exceeding a maximum of 1 4 mil- liseconds After nulling, the timing capacitor C 5 is reset (during RESET 2), which takes 3-5 millise- conds, to prepare for the next capacitor integration period to time the next commutation It is also nec- essary to provide this time delay after commuta- tion has taken place to assure that all of the stored energy in the now unenergized winding (which was energized prior to commutation) has time to dissipate This is necessary to assure that stored energy is not incorrectly interpreted as back-emf causing a large error in the commutation instant.

The Autonull Circuit 143 and its relationship to the, other functional blocks will be described in detail below.

The remaining blocks in the control IC deal pri- marily with implementing the manual control func- tions When the ceiling fixture is turned on, and power is to be applied to the fan motor, the "Power On Reset" (POR) is active.

The POR 150 is a protection circuit for other por- tions of the ECM control circuit which becomes ac- tive when power is turned on or turned off It insures that the protected circuitry is held in a de- sired safe inactive state when the supply voltage on the protected circuit is below a first value when power is turned on, or below a second value (usu- ally slightly lower) when power is turned off When power is turned on, it releases the protected circuit in a desired initial state The interaction of the POR with other functional divisions of the Motor Control IC is in part illustrated in the waveforms of Figure 3 and Figure 12 B. In consequence of the appearance of the active output of the POR when power is turned on, the Amplifier 141 is disconnected from capacitor C 5, and the Comparator Network 142 and the Autonull Circuit 143 are preset This produces an initial state, akin to the occurrence of a commutation instant in preparation for nulling the amplifier The POR presets the 3 bit memory of the Commutation Counter 144 in an initial ( 000) state It presets the Forward/Reverse Logic to the state set in by the switch 51 on the printed circuit board The preset- ting occurs immediately after power has been ap- plied to the POR and lasts until Vdd is high enough (e.g 7 0 volts) to insure that the analog and logic circuitry is valid.

When the active POR output terminates, the au- tonull circuit is released for nulling, insuring that the Amplifier is nulled before it is used for integra- tion timing After this, the POR 150, now acting by means of the IST waveform coupled to the Auton- ull Circuit, influences starting for five artificial counts of the Commutation Counter 144 by intro- ducing an offset current in the resistance network of the Amplifier 141, which facilitates the discharge of the integrating capacitor C 5 to the voltage set to mark the commutation instant and nulling For the same 5 count period, the POR, acting by means of the I start waveform, turns off the "bottom" switches of the output drivers, precluding the cou- pling of energy to the winding stages of the motor until the Amplifier 141, Comparator Network 142 and the Autonull Circuit 143 have stabilized.

The Forward/Reverse Logic 149 is responsive to the setting of the switch 51 coupled to the pad P 16 on the IC It is also responsive to a controlled dimi- nution in the B+ supply effected by the operation of the wall control to reduce the B+ voltage below the desired threshold In addition, when power is reapplied, after having been turned off, the POR 150 circuit presets the Forward/Reverse Logic to the state that corresponds to the setting of switch 51 A change in the output from 149 which causes the Forward waveform to go to an active High from a prior Low, and the Reverse waveform to go to an inactive Low from a prior High, or vice versa, produces a reversal in the direction of rotation of the motor These waveforms, which are illustrated in Figure 3, are the means by which a reversal in motor rotation is achieved The Forward waveform is coupled to the Commutation Counter 144 to ef- fect both a forward and a reverse count The For- ward and Reverse waveforms are coupled to the control logic for enabling the Forward gates (U 42- U 47) or the Reverse gates (U 36-U 41) The Forward or Reverse waveform is also coupled to the POR for decoding the five count interval for simulated commutation When the Forward/Reverse Logic is in a Forward state, the POR is enabled to count forward to the C 55 state, and when the Forward/ Reverse Logic is in a Reverse statethe POR is ena- bled to count "backwards" to the CSO state, both of which provide the required delay.

Control of the Forward or Reverse state of the Logic 149 is achieved through operation of the wall control 105 If reversal is desired, the motor speed control is moved in the direction of reducing speed past the point at which the motor will stall The ef- fect of so moving this control is to reduce the B+ below a threshold This in turn is sensed on the regulate pad (p 14) via the action of transistor Q 81, thus raising the regulate voltage above the peak sawtooth voltage This is sensed in the Logic and used to cause a reversal in the state of the For- ward/Reverse setting The sensing is achieved by comparing the B+ using circuitry on the printed circuit board including Q 81, R 25, R 26, R 27, R 29 and R 30, with a Zener stabilized voltage reference, also on the printed circuit board, but divided down on the Motor Control IC 121 The Logic includes a comparator which compares a voltage proportional to the B+ voltage with a voltage proportional to the Zener voltage, and includes a circuit on the IC for introducing hysteresis in the threshold to make the switching action positive.

Finally, the Forward/Reverse Logic is provided with a delay based on the use of a 20 K Hz pulse for the Oscillator 147 in the actual changeover from forward to reverse operation The Clock waveform CLK is coupled to the Forward/Reverse Logic to ef- fect this delay.

14 GB 2 177559 A The Oscillator 147 and the Pulse Width Modula- tor 148 enter into the regulation of the speed The motor is designed to run at a speed established by the amount of electrical power supplied to the motor and the amount of mechanical power required to rotate the fan and drive the air impinging on its blades When greater power is supplied, the rate Qf rotation increases, and when lesser power is sup- plied, the rate of rotation decreases The speed is thus controlled by the amount of power supplied, and that power is subject to a continuous control.

The commutation is designed to be at the correct angle irrespective of the speed of rotation and is not intentionally varied with adjustment of the speed.

The Oscillator 147 and Pulse Width Modulator 148 provide the means for adjusting the power supplied to the motor over a range of substantially all off to all on In practice, the arrangement per- mits the motor to operate over a 20 to 1 range of speeds As earlier explained, the motor is ener- gized by simultaneous energization of two serially connected winding stages Should only one wind- ing stage be energized as when the I start wave- form is applied, the motor receives no electrical energy.

The control of the motor speed is exerted by pulse width modulating one of the two switches which are enabled at each count of the counter.

This is best seen from an examination of Figure 3.

The waveforms derived by the output drivers (AT, AB, etc) and coupled to the output of pads P 7-P 12 illustrate these properties Each waveform (AT, AB, etc) has an active high of two counts duration with the same two highs being on simultaneously for only a single count In addition to the two highs that are on, one is always shown with the vertical lines indicative of pulse width modulation Thus, by pulse width modulating one of the two active switches, pulse width modulation occurs at all times In addition, due to the classic nature of the pulse width modulation, the on time of the pulse width modulated waveform may vary from 0 to % which thus provides a full range of power control.

The Oscillator 147 is a relaxation oscillator whose principal circuitry is on the IC but which has an external capacitor C 6 and a resistance R 24 mounted on the printed circuit board and con- nected to the IC at pad 15 The internal oscillator waveform is a unidirectional pulse having an approximately 20 K Hz repetition rate with an on time of 300 nanoseconds for the narrower portion of the pulse The CLK output of the oscillator derived from a flip-flop (U 94-U 91 is coupled to the For- ward/Reverse Logic 149, as earlier noted, for effect- ing a delay when the direction of motor rotation is changed equal to at least one pulse width interval, The inverse of the oscillator waveform CLK is cou- pled to the Autonull Circuit 143 where it controls the incrementing rate in the nulling process.

The output of the Oscillator 147 is modulated by the Pulse Width Modulator 148 The components of the Pulse Width Modulator are in part on the integrated circuit and in part on the printed circuit board being interconnected by means of the pad P 14 (REG) The external components are largely shared with the Forward/Reverse Logic They in- clude the potentiometer R 40, the resistances R 25, R 26, R 27, R 29, R 30, and capacitor C 4.

The Pulse Width Modulator is a classical modu- lator which provides an output which in the limit- ing cases is on all of the time or off all of the time, and in intermediate cases is on part of the time and off part of the time, as illustrated in Figure B The output of the Pulse Width Modulator (PWM out) is coupled to the Control Logic 145 by means of which it introduces a pulse width modu- lation into the switching waveforms in either of the forward bank (U 42-U 47) or the reverse bank (U 36- U 41) of gates. The Autonull Circuit 143 nulls the Integrating Transconductance Amplifier

to remove any error in timing of the commutation instant attributable to Amplifier input offset and to improve motor start- ing performance The Autonull Circuit is located entirely on the Integrated Circuit and requires no pads for external connection.

The Autonull Circuit includes two digitally subdi- vided resistive elements R 3 A-D and R 4 A-D, which are the resistive elements in a current mirror in one of the two channels of the Amplifier 141 fol- lowing the differential input stage The current mir- ror is modified by the inclusion of means for introducing an offset current which may be digitally stepped in 3/4 p A increments on either the in- put or output side of the current mirror, and which in effect brings one channel of the Amplifier into balance with the other The incrementing occurs under the control of a 5 bit counter, which counts at the 20 K Hz rate of the Oscillator 147 (CLK) In the nulling process, the 5 bit counter is preset to a maximum offset current condition and is then dec- remented at the clock rate until a balance is de- tected When the balance is detected, the counter stops and the offset current in maintained until nulling is again instituted.

The Autonulling Circuit functions once for each commutation The waveforms that are involved in nulling for normal operation are illustrated in Figure 12 A The nulling period starts after the Com- parator Network 142 (COM 2, U 80, D 16 Q) has signalled the commutation instant (see Figure 9), causing the RESET 1 waveform to go high (D 16 Q).

When the RESET 1 waveform goes high, the input to the Integrating Amplifier 140 is referenced to a voltage reference (Vref 1) suitable for nulling and the differential amplifier inputs are shorted to- gether At the same time the Null Clock waveform is generated by the Comparator Network 142 (D 17 Q) This waveform is coupled to a 5 bit counter in the Autonull Circuit (D 8, D 12) which forces the Au- tonull Circuit into a PRESET condition in which the maximum offset current, earlier mentioned, is in- jected into the Amplifier 141 At substantially the same time, the Autonull Circuit generates the Null Output waveform (D 7, Q) which is coupled to a transmission gate U 85) at the input to the Compar- ator Network 142 This disconnects the Amplifier from the external integrating capacitor (C 5), leav- GB 2 177559 A 15 ing the Amplifier output connected only to third comparator (COM 3) in the Comparator Network.

The input conditions cause the Amplifier output voltage to climb past the threshold Vref 2 of the third comparator (COM 3) causing the Null Set waveform originating at COM 3 U 81 to go low.

This waveform, when coupled back to the Autonull Circuit, releases the PRESETS on the counter, and allows the counter to decrement at the clock rate.

Decrementing is accompanied by a stepped reduc- tion in the offset current applied to the Integrating Amplifier When the comparator COM 3 senses that the voltage at the output of the Amplifier, which had been near Vdd changes in direction, sig- nalling the null, the Null Set waveform goes high.

On the following clock pulse the Null Output (D 7 Q) waveform goes low The Null Output waveform (D 7 G) is coupled to the Comparator Network which generates the RESET 2 waveform, which converts the Amplifier 141 into a maximum current supply stage At the same time the Null Output waveform operates the transmission gage U 85 to reconnect the Integrating Amplifier to the integrat- ing capacitor C 5 When the upper voltage reference (Vref 4) is crossed, both RESET 1 and RESIET 2 ter- minate and the next capacitor integration period commences.

During start conditions the Autonull sequence is affected by the Power On Reset 150 The Power On sequence is illustrated in the waveforms of Figure 128 When power is first applied, the POR wave- form is in an active low which causes the Null Clock waveform (D 17 Q) to go high This causes the Autonull counter to be preset in a high offset current condition When the POR waveform goes to an inactive high subsequently, the Null Clock waveform falls, allowing the counter in the Auton- ull Circuit to decrement The autonulling is further affected by the application of an offset current IST which is interrupted during nulling, but active during capacitor resetting and integration The offset current lST adds to the discharge current of the In- tegrating Amplifier and causes the integrating ca- pacitor to discharge more rapidly and more positively toward the threshold of comparator COM 2 Under the influence of the logic contained in the POR block, the IST current continues until 5 autonull sequences are completed During the same 5 count sequence, the lower drivers BOBA-C are also disabled so that no power is applied to the motor windings On the sixth count, the IST and I Start highs are terminated, the motor windings are energized and autonulling continues in the normal manner.

The input gating 140 The Input Gating 140 is the input switching means of the Control IC 121 which selects the cor- rect unenergized motor winding stage for determi- nation of the next commutation instant The Input Gating 140 is coupled to the pads P 5, P 4, P 3 and P 2, respectively designed for connection via the four section voltage divider 125 to the VA, VB, VC and VN motor winding terminals earlier identified.

The voltage divider 125 is the means immediately connected to the winding stages for deriving volt- ages proportional ( 1/41) to the voltages induced in the winding stages reduced to values suitable for application of the IC.

The Input Gating 140 couples the output voltage from the selected winding stage to the input termi- nals 150, 151 of the Integrating Transconductance Amplifier 141 in the correct sense to keep the cor- rect Amplifier output polarity over successive com- mutation periods The Input Gating consists of eight bidirectional transmission gates U 58, U 60, U 62, U 64, U 66, U 68, U 70 and U 72, each associated with an inverter U 57, U 59, U 61, U 63, U 65, U 67, U 69 and U 71, respectively, three gates U 54, U 55 and U 56 used to control the sense of the selection of the nautral (N), and six gates U 73-U 78 used to control the sense of selection of the three non-neu- tral winding stage terminals (A, B, C) The output voltage from the selected winding is coupled be- tween the input terminals 150, 151 of the Integrat- ing Transconductance Amplifier 141 The control signals for operating the input gates are derived from the Comparator Network (RESET 1) and the Modulo 6 Counter 144 (B 0, CSO-5).

The Input Gating 140 is connected as follows.

The transmission gates are bidirectional conductive devices, each consisting of two complementary field effect transistors connected in parallel be- tween the signal input terminal and the signal out- put terminal Each transmission gate has two control terminals requiring oppositely sensed con- trol voltages In the illustrated configurations, a signal is coupled directly to one control terminal, and through an inverter to the other control termi- nal, so that there is in fact only a single control connection assigned to each gate The transmis- sion gates are enabled with a high control signal, and not enabled with a low control signal The sig- nal input terminals to the gates U 58 and U 60 are coupled to the pad P 2 for application of the VN voltage The output terminal of the gate U 60 is connected to the input terminal 150 of the Inte- grated Transconductance Amplifier, while the sig- nal output terminal of the gate U 58 is connected to the input terminal 151 of the Integrating Transconductance Amplifier Similarly, the signal input ter- minals of the gates U 62 and U 64 are connected to pad P 5 for application of the VA voltage The sig- nal output terminal of the gate U 64 is connected to the amplifier input terminal 150, while the signal output of the gate U 62 is connected to the ampli- fier input terminal 151 The signal input terminals of the gates U 66 and U 68 are connected to the pad P 4 for application of the VB voltage The signal output terminal of the gate U 68 is connected to the amplifier input terminal 150 The signal output ter- minal of the gate U 66 is connected to the amplifier input terminal 151 The signal input terminals of the gates U 70 and U 72 are connected to the pad P 3 for application of the VC voltage The signal output terminal of the gate U 72 is connected to the amplifier input terminal 150 The signal output terminal of the gate U 70 is connected to the amplifier input terminal 151.

As already indicated, each transmission gate has 16 GB 2 177559 A an associated inverter, which inverts the applicable control signal The uninverted control signal for each transmission gate is directly coupled via the associated inverter to the other control input of the transmission gate The inverter U 54 and two input NOR gates U 55 and U 56 are connected to the con- trol inputs of transmission gates U 60 and U 58 The control signals for these gates are the RESET 1 waveform derived from D 16 Q of the Comparator Network 142, and the least significant bit (B 0), from the flip-flop D 1 Q of the Modulo 6 Counter 144.

The RESET 1 pulse is coupled to one input of NOR gate U 55 and to one input of NOR gate U 56 The least significant bit (B 0) from the Modulo 6 Counter is directly coupled to one input of the NOR gate U 56, and indirectly coupled via the inverter U 54 (whose input is connected to D 1 Q) to the other in- put of NOR gate U 55 The two input NOR gates U 73 to U 78 each have one input coupled to D 16 Q for application of the RESET 1 pulse, and one input coupled respectively to the Counter 144 for application of the C 55-C 50 waveforms The outputs of the NOR gates U 55, U 56 and U 78 to U 73 are con- nected to the control inputs of the transmission gates U 58, U 60, U 62, U 64, U 66, U 68, U 70 and U 72, respectively.

The Input gating 140 is designed to sense the voltage of the selected winding during the capaci- tor integration period, when the RESET 1 waveform is low (see Figure 8) Thus, each NOR gate (U 55, U 56, U 73-U 78), which has one input coupled to D 16 Q for application of the RESET 1 waveform, inhibits all eight transmission gates (U 58, U 60, U 62, U 64, U 66, U 68, U 70, U 72) when the RESET 1 waveform is high When the RESET 1 waveform is low, however, corresponding to the capacitor inte- gration period, the NOR gates may be selectively energized in accordance with the state of the Mod- ulo 6 Counter.

The transmission gates of the Input Gating are arranged to successively invert the polarity of the signal coupled from the motor winding stage to the input terminals 150, 151 of the Integrating Am- plifier 141 Assuming that the counter is in the CSO state (and that the RESET 1 waveform is low), CSO is low, the output of gate U 78 is high, enabling transmission gate U 62, which couples VA at pad P 5 to terminal 151 At the CSO state, the least sig- nificant bit is also low NOR gate U 56, with two lows at the input, has a high at the output, ena- bling transmission gate U 60 to coupled VN at pad P 2 to terminal 150 At the next count, the C 51 state, the output of U 75 is high, enabling U 68, and coupling VB at pad P 4 to terminal 150 The least significant bit is now high, and NOR gate U 55, with two lows at the input, has a high at the output, en- abling transmission gate U 58 to couple VN at pad P 2 to terminal 151 Similarly, at the next count, the C 52 state, the output of U 74 is high, enabling U 70, and coupling VC at pad P 3 to terminal 151 The least significant bit is now low, and the output of U 56 is high, enabling U 60, and coupling VN at pad P 2 to terminal 150 Each succeeding count for the states (C 53, C 54, C 55, CSO, etc) which follows, connects an unenergized winding to the input of the Integrated Amplifier, and does so in a polarity which is opposite to that of the preceding connec- tion (i e, with neutral connection to terminal 150 on even counts, and to terminal 151 on odd counts).

Figure 3 illustrates the winding stage selection which is made by the input gating as a function of the counter states During CSO, both winding stages B and C are energized; therefore winding stage A, which is unenergized is sensed via gate U 62 During C 51, both winding stages A and C are energized; therefore winding stage B is sensed via gate U 68 During C 52, both winding stages A and B are energized; therefore winding stage C is sensed via gate U 70 During C 53, winding states B and C are energized; therefore winding stage A is sensed via transmission gate U 64 During C 55, ' winding stages A and B are energized; therefore winding stage C is sensed via gate U 72.

Integrating transconductance amplifier 141 The Integrating Transconductance Amplifier is il- lustrated in Figures 5 A, 5 B, 5 C and 5 D Figure 5 A illustrates all the active circuit elements of the amplifier less the resistance in the amplifier current sink into which offset currents are introduced to null the amplifier Figures 5 B, 5 C and 5 D are pro- vided to explain the operation of the Transconduct- ance Amplifier, emphasizing those measures for stabilizing the amplifier transponductance The cur- rent sink resistances (R 3, R 4) are made a part of the Figure 5 B illustration without the offsetting means used for nulling the amplifier In addition, to complete the Transconductance Amplifier, the connections VA and VN to a representative motor field winding stage (A), are shown coupled via two appropriate pairs of voltage dividing resistors, and via two transmission gates to the inputs 150, 151 of the Transconductance Amplifier The grounding circuit to the divider network including diodes CR 2, CR 3 and capacitor C 3 are also shown in Figure 5 B. As shown primarily in Figure 5 A, the Integrating Transconductance Amplifier consists of the transis- tors Q 1 to Q 11; Q 16, Q 17; Q 18 and Q 23 to 029 and the resistances R 1 to R 8 The Amplifier consists es- sentially of a differential input stage (Q 1, Q 2, Q 3, Q 4, Q 5, Q 6) a first current mirror (Q 10, Q 11) cou- pled to one output (Q 5) of the differential input stage; a second current mirror (Q 16, Q 17) coupled to the other output (Q 6) of the differential input stage; a common gate buffer Q 24 coupling the output of the first current mirror to a high output impedance inverting current mirror Q 26-Q 29; and a common gate buffer Q 25 coupled to the output of the second current mirror The input signal is cou- pled to the positive ( 150) and negative ( 151) input terminals of the differential input stage (Q 5, Q 6), where the positive input is defined to be the one which drives the upper output device (Q 27) and the negative input drives the lower output device (Q 25) The output of the inverting current mirror (Q 26-Q 29) appears at the drain of the transistor Q 27 and the output of the buffer Q 25 appears at the drain of Q 25 The drains of push-pull con- nected transistors Q 27, Q 25 form the output termi- GB 2 177559 A 17 nal 152 of the Integrating Transconductance Ampli- fier.

The five transistors Q 7, Q 8, Q 9, Q 18 and Q 23 control the Integrating Amplifier during nulling and capacitor reset The transistors Q 7 and Q 8 provide a means for shorting out the differential input to the Integrating Amplifier during nulling and reset of the capacitor C 5 They become operative during the Reset 1 pulse The transistors Q 9, Q 18 and Q 23 are the means for causing rapid reset of the capac- itor C 5 after nulling is complete During the Reset 2 pulse, transistor Q 9 disables the current sink Q 10, Q 11; Q 18 disables the current sink Q 16, Q 17; while Q 23 enables the upper current mirror Q 26-Q 29 to supply the desired charging current via Q 27.

The input differential amplifier stage of the Tran- sconductance Amplifier consists of the differen- tially connected P-channel transistors Q 5 and Q 6.

The input signal at the positive terminal 150 is cou- pled to the gate of Q 5, and at the negative input terminal 151 is coupled to the gate of Q 6 The source of Q 5 is connected via a degenerating 2000 Q resistance R 1 to the drain of P-channel tran- sistor Q 4 for the supply of current to Q 5 The source of Q 6 is connected via a degenerating 2000 Q resistance R 2 to the drain of Q 4 for the sup- ply of current to Q 6 The resistances R 1 and R 2 provide current series feedback as symbolized in Figure 5 D for stabilizing the Amplifier Transcon- ductance.

The transistors Q 1, Q 2, Q 3, Q 4 supply a fixed current (typically 250 p LA) to the sources of transis- tors Q 5 and Q 6 Serially connected N-channel tran- sistor Q 1 and P-channel transistor Q 2 are current references establishing the output current of the current source The transistor Q 2 has its source connected to Vdd, and its drain connected to the drain of transistor Q 1 The drain and gate of Q 2 are connected together The source of Q 1 is connected to the IC ground and the gate of Q 1 is connected to Vdd to establish conduction in the series con- nected Q 1, Q 2 transistor pair The geometry selec- tion 200/4 gate (gate width to gate length) for Q 2 and 4/4 for Q 1 establishes a current of typically 250 p A in Q 1 and Q 2 The output P-channel transis- tor Q 3 of the current mirror, which has its source connected to Vdd, has its gate connected to the gate of Q 2 Transistor Q 3, which has similar geom- etry ( 200/4) to Q 2, is held at a gate to source volt- age equal to that of Q 2, and tends to "mirror" an output current equal to the current in the reference at its drain The drain of Q 3 is coupled to the source of current source buffer P-channel transistor Q 4 Transistor Q 4 is of large design ( 500/4) to ob- tain a low drain to source saturation voltage, and has its gate coupled to a 5 8 V reference (formed of a plurality of series connected transistors) set to establish conduction in Q 4 The current output of the current source (Q 1-Q 4) appears at the drain of buffer transistor Q 4, which is coupled, as already noted, to supply current ( 2501 LA) to the transistors Q 5 and Q 6 of the differential input stage.

The signal voltage coupled between the gates of Q 5 and Q 6 produces two output signal currents at the drains of Q 5 and Q 6 respectively As earlier de- fined, the gate of Q 5 may be regarded as the input to the positive "channel" of the Transconductance Amplifier since it controls the conduction of output transistors Q 27 Conduction of Q 27, which is the upper member of the push-pull output pair, "sup- plies" current from the positive (Vdd) supply to the load For similar reasons the gate of Q 6 may be re- garded as the input to the negative channel of the amplifier, since it controls the conduction of Q 25, which "withdraws" current from the load toward (Vss) at IC ground.

The signal current appearing at the drain of Q 5 is coupled to the drain of N-channel transistor Q 10, the input current reference of the first current mir- ror (Q 10, Q 11) in the positive channel The source of Q 10 is connected through a tapped 2000 ohm resistance R 3 (best shown in Figure 7) to the IC ground The gate of Q 10 is coupled to the drain of transistor Q 10 The configuration tends to establish a seriesacurrent bias of approximately 125 FA in Q 10 (half of the Q output current) and in Q 5 The gate of Q 10 is coupled to the gate of the mirror output N-channel transistor Q 11, whose source is connected through a tapped 2000 ohm resistance R 4 (best shown in Figure 7) to the IC ground The appearance of a signal current in Q 10 produces a nearly equal mirrored signal output current in the mirror output transistor Q 11 The current transfer accuracy of the mirror is in part due to the magni- tude of the degenerating resistances R 3 and R 4.

The signal current appearing at the drain of Q 6 is coupled to the drain of the N-channel transistor Q 16, the input current reference of the second cur- rent mirror in the negative channel The source of Q 16 is connected through a 2000 Q resistance R 5 to the IC ground The gate of Q 16 is connected to the drain of Q 16 The configuration tends to establish a series current bias of approximately 125 RA in Q 16 (half of the Q 4 current) and in Q 6 The gate of Q 16 is coupled to the gate of the mirror output N-chan- nel transistor Q 17, whose source is connected through a 2000 ohm resistance R 5 to the IC ground The appearance of a signal current in Q 16 produces a nearly equal mirrored signal output current in the mirror output transistor Q 17 The current transfer accuracy of the mirror is in part due to the magnitude of the degenerating resist- ances R 5 and R 6.

The output current appearing at the drain of transistor Q 11 in the first current mirror in the po- sitive channel is connected to the source of the large geometry ( 500/4) N-channel buffer transistor Q 24 The gate of Q 24 is returned to a 3 2 volt refer- ence voltage supply The output current of buffer transistor Q 24 is coupled from the drain of Q 24 to the input of the polarity inverting current mirror Q 26-029 from which a part of the amplifier output is derived The common gate configuration of Q 24 accurately preserves a unity current transfer ratio between the source of Q 24, which is held to equal- ity with the output current of the first current mir- ror Q 11 and the current at the drain of Q 24 into which the current from the polarity inverting cur- rent mirror is drawn.

The output current appearing at the drain of the 18 GB 2177559 A transistor Q 17 in the second current mirror in the negative channel is connected to the source of the large geometry ( 500/4) N-channel buffer and output transistor Q 25 The gate of Q 25 is returned to the 3 2 volt reference voltage supply shared with the gate of Q 24 The output current of buffer transistor Q 25 enters the drain of Q 25 from the Integrating Amplifier output terminal 152 The common gate configuration of Q 25 accurately preserves a unity current transfer ratio between the source of Q 25, which is held to equality with the output current of the second current mirror 017, and the current at the drain of Q 25, connected to the output terminal 152 of the Integrating Amplifier.

* The output current appearing at the drain of the buffer transistor Q 24 in the positive channel is cou- pled to the input of the modified Wilson current mirror employing transistors Q 26 and Q 29 These transistors are all P-channel devices of 200/4 ge- ometry The mirror, which has a current transfer ratio very closely approximating unity, inverts the signal current direction and exhibits a high output impedance The drain of Q 24 is connected to the gate of the P-channel transistor Q 27 whose drain is connected to the amplifier output terminal 152 The drain of Q 24 is also connected to the gate of the P- channel transistor Q 26, whose gate and drain are joined The transistor Q 27 is serially connected with the P-channel transistor Q 29 The source of Q 27 is connected to the drain of Q 29, with the source of Q 29 being connected via the 3000 fl re- sistance R 8 to the Vdd supply, and the gate and drain of Q 29 being joined By these connections the current in Q 29 is forced into equality with the current in Q 27 Continuing, P-channel transistor Q 28 has its gate connected to the gate of Q 29, and its source connected via the 3000 f Q resistance R 7 tq the Vdd supply By these connections Q 28 tends to mirror the current in Q 29 The mirror is completed by the connection of the drain of Q 28 to the source of Q 26 The serial connection of Q 24, Q 26, and Q 28 forces the current in all three transistors into equality with the positive channel signal current in Q 24 The result of the foregoing four transistor configuration is to transfer the positive channel signal current from the drain of Q 24 in inverse po- larity to transistor Q 27, where it is of a polarity to supply current from Vdd to the output terminal 152.

The Transconductance Amplifier output stage may also be regarded as two current sources (Q 26- Q 29; and Q 16, Q 17, Q 25) in push-pull with output transistor Q 27 tending to supply current to the out- put terminal from a source at Vdd potential, and the output transistor Q 25 tending to withdraw cur- rent from the output terminal of the IC ground The consequence of the serial connection of two cur- rent sources is that the output voltage is not de- fined until a current exchanging load has been connected to the Amplifier output terminal In the event that the circuit load is the gate of an FET, which draws negligible current, any slight asym- metry in current gain or dc imbalance between po- sitive and negative channels will force the output potential toward either the Vdd or Vss determined limits If the load is of relatively low impedance in relation to the output impedance of the Amplifier, such as a relatively "large" capacitor operating with a relatively "short" time constant, and further assuming that the input impedance of the Ampli- fier is large relative to the source impedance (which is true for FE Ts), then the Transconductance Amplifier is operated in the natural mode, and the output current closely equals the input voltage times the design transconductance of the Ampli- fier Further, we may assume that the differential input stage, and the three current mirrors have a high dependency on processed resistances rather than on Gm dependent parameters alone for defin- ing the Gm of the initial stage and for maintaining equality in the current ratios of the subsequent current mirrors The uncertainty in amplifier Gm may be reduced by a factor greater than two using the indicated parameters These measures on the IC have provided an accurate amplifier Gm, avoiding the need for compensation external to the inte- grated circuit.

Matched pairs of resistors used in the Amplifier mirrors are implemented using interdigitated poly- silicon tunnels which are readily available on the conventional gate array These tunnels are located in a column between the input/output cells and the body of the array In a custom IC design, these re- sistances would be produced using polysilicon in an interdigitated configuration This process im- proves the ratio matching of the individual resist- ances and improves the accuracy of the current mirror.

Means are also provided on the IC for offsetting any imbalance between the positive and negative channels of the Transconductance Amplifier (i e.

the Autonull Circuit 143).

The five transistors Q 7, Q 8, Q 9, Q 18 and Q 23 earlier mentioned control the Integrating Amplifier during nulling and reset of the capacitor C 5 The transistors Q 7 and Q 8 are two N-channel devices of 100/4 geometry having their drains connected, respectively, to the amplifier input terminals 151 and 150, and their sources connected together to a 3 volt voltage reference (Vref 1) The gates of Q 7 and Q 8 are connected together for application of the Reset 1 waveform available from the Compara- tor Network (D 16 Q) They short out the differential input, and maintain both channels at a normal level of condition when the Reset 1 pulse is high for nulling the Amplifier, and for facilitating reset of the capacitor C 5.

The transistors Q 9, Q 18 and Q 23 are designed to create a high output current during reset of the ca- pacitor C 5, under the control of the Reset 2 wave- form The transistors Q 9 and Q 18 are two N- channel devices of 200/4 geometry Transistor Q 9 has its drain connected to the gates of the transis- tors Q 10, Q 11 in the first current mirror and its source connected to the IC ground Transistor Q 18 has its drain connected to the gates of the transis- tors Q 16 and Q 17 in the second current mirror and its source connected to the IC ground The transis- tor Q 23 is an N-channel device of 4/10 geometry having its drain connected to the gates of the tran- 193 GB 2177559 A 19 sistors Q 26 and Q 27 of the inverting current mirror, and its source connected to the IC ground The gates of transistors Q 9, Q 18 and Q 23 are con- nected together for application of the Reset 2 wav- eform available from the Comparator Network.

When transistors Q 9 and Q 18 are conductive as by application of the Reset 2 waveform, the gates of the current mirrors Q 10, Q 11 and Q 16, Q17 are held at near IC ground potential, and the output sinking currents are turned off When transistor Q 23 is conductive, as by application of the Reset 2 waveform, the upper current mirror is turned on, and a large current becomes available via transis- tor Q 27 for resetting capacitor C 5.

Comparator network 142 The Comparator Network 142 accepts the output current from the Integrating Transconductance Amplifier 141, "integrates" that current in the inte- grating capacitor C 5, and by measuring the change in voltage on the capacitor by comparisons to in- ternal voltage references determines the commuta- tion instant As earlier noted, the amplifier output current is proportional to the reverse electromotive force (or voltage) induced in the unenergized wind- ing If that voltage is integrated from the reference rotor position, where the voltage reverses in direc- tion, or zero, an accurate measure of the actual ro- tor position may be obtained with respect to reference position Since the amplifier produces an output current proportional to input voltage, an integration of the amplifier output current equals an integration of the voltage (assuming appropriate limits of integration) The Comparator Network 142 produces an output pulse (Reset 1) when the measured voltage change has reached the correct value, and causes commutation In addition, the Comparator Network, in cooperation with the Au- tonull Circuit 143, is used to sense the correction of imbalance in the Integrating Amplifier In nulling the Integrating Amplifier, which occurs once for each commutation in the present arrangement, an offset current is incremented until the output cur- rent of the Transconductance Amplifier reverses in direction (passes through zero) When that occurs, the Comparator Network produces an output pulse (Reset 2) terminating the nulling process, causing "reset" of the integrating capacitor C 5 and re-insti- tuting timing for the next commutation event.

The Comparator Network 142, which performs the foregoing functions in timing the commutation and amplifier nulling, consists of a transmission gate U 85 and accompanying inverter U 84 'three comparators (COM 1-3), each followed by a hyster- esis gate U 79-U 81, respectively, two flip-flops D 16, D 17; and a NOR gate U 83.

The Comparator Network 142 is connected as follows The output terminal 152 of the Integrating Amplifier is coupled to the signal input terminal of the transmission gate U 85, and to the negative in- put of the comparator COM 3 The transmission gate is a bi-directional device consisting of two complementary field effect transistors connected in parallel, and requiring oppositely sensed control voltages at the control terminals The control volt- age for U 85 is derived from the Autonull Circuit (D 7 Q) and is coupled to one control terminal unin- verted and to the other control terminal inverted by means of the inverter U 84 The signal output of the transmission gate U 85 is connected to the pad Pl for connection to the integrating capacitor C 5, to the positive input terminal of the comparator COM 1, and to the negative input terminal of com- parator COM 2.

The individual comparators, which monitor the voltage on the capacitor C 5 and/or Amplifier out- put, are respectively COM 1, the reset comparator, which terminates capacitor reset; COM 2, the com- parison means for timing the commutation instant; and COM 3, the nulling comparator.

The inputs of the three comparators COM 1-3 are connected as follows The positive input of COM 1 is connected to the signal output of the transmission gate U 85 and via the pad Pl to the integrating capacitor C 5 The negative input of COM 2 is also connected to the signal output of the transmission gate U 85 and the integrating capacitor C 5 The negative input of COM 1 is connected to the high (e.g 6 5 volts) voltage reference Vref 4 The posi- tive input of COM 2 is connected to the low (e g.

3.0 volts) voltage reference Vref 3 These voltage references (Vref 4 and Vref 3) set the difference in voltage through which the capacitor C 5 is dis- charged to time the commutation degrees from zero winding voltage The amplifier output 152 is connected to the negative input to comparator COM 3 The positive input of COM 3 is coupled to an intermediate (e g 5 5 volts) voltage reference Vref 2 Comparator COM 3 senses the output voltage of the Integrating Amplifier during nulling (when the Integrating Amplifier is disconnected from the integrating capacitor), and detects when the output voltage of the Integrating Amplifier is falling from Vdd saturation toward Vss to termi- nate nulling.

The outputs of the comparators COM 1-3 are coupled to the hysteresis gates U 79-U 81, flip-flops D 16 and D 17, and the NOR gate U 83 of the Comparator Network as follows The output of the com- parator COM 1 is coupled via the inverting hysteresis gate U 79 to the reset (R) terminal of the flip-flop D 16 The output of the comparator COM 2 is coupled via the inverting hysteresis gate U 80 to the clocking terminals (C) of D 16 and D 17 Both D 16 and D 17 are designed to trigger on the nega- tive going edge of a clocking waveform The out- put of the comparator COM 3 is coupled through the non-inverting hysteresis gate U 81 to the reset (R) terminal of D 17, and to the Autonull Circuit 143 (D 7; D input) The output of U 81 is denominated the "Null Set" waveform It is used to signal that the Amplifier output, initially set to maximum off- set by the Autonull Circuit, has increased from Vref 2 at the input to COM 3, and is now ready to dec- rement the initial offset, toward whatever lesser value is required to achieve a null The data (D) in- puts of D 16 and D 17 are both coupled to Vdd The set (S) terminals of D 16 and D 17 are coupled to the POR 150 (POR output of U 120) The Q output of flip-flop D 16, denominated "Reset 1 ", is a wave- GB 2 177559 A form coupled to the Modulo 6 Counter 144 (D 1-D 3 C inputs); to the Input Gating 140 (U 55, U 56, U 73- U 78); to the Integrating Transconductance Ampli- fier 141 (Q 7,Q 7); and to the Control Logic 145 (U 13) The Q output of D 16 is connected to one in- put of NOR gate U 83 The NOR gate U 83 "NO Rs" the "Null Output" signal of the Autonull Circuit 143 (D 7; Q) with (D 16; Q) to produce the "Reset 2 " waveform which is coupled to the Integrating Am- plifier 141 (Q 9, Q 18, Q 23) The D 17; Q output, de- nominated the "Null Clock" waveform is coupled to the Autonull Circuit 143 at the input to inverter U 92 The output of U 92 (Null Clock Inverted), is coupled to the C input of D 6 and to the R inputs of D 7-D 12 The Null Clock waveform resets and holds the flip-flops D 7-D 12 until termination of the Null Clock interval which ends when the amplifier out- put exceeds Vref 2, and is ready to decrement to- ward a null.

The operation of the Comparator Network is il- lustrated in Figure 8 The commutation period var- ies from 17 to 170 milliseconds depending on motor speed The capacitor integration period be- gins when the voltage at the output of the Integrat- ing Amplifier exceeds Vref 4 (the threshold of COM 1), and reset of the capacitor C 5 is complete The transmission gate U 85 became conductive 3 to 5 milliseconds earlier, allowing reset to commence.

When U 85 is conducting, the output of the Inte- grating Amplifier 141 is connected to the integrat- ing capacitor C 5, to the positive and negative inputs respectively of the comparators COM 1 and COM 2.

The transmission gate U 85 is turned on when re- set of the capacitor C 5 is occurring at the conclu- sion of nulling The transmission gate U 85 remains conductive during the period that capacitor inte- gration is occurring, and is non-conductive during amplifier nulling (Null Output waveform: D 7, Q high) The gate U 85 becomes non-conducting when the Comparator COM 2 signals that the volt- age on the capacitor C 5 has fallen below Vref 3, causing the Reset 1 pulse to be generated and the nulling of the Amplifier to commence _ During amplifier nulling (Null Output D 7 Q high), the output of the Integrating Amplifier 141 is disconnected by transmission gate U 85 from the inte- grating capacitor C 5, and from the positive and negative inputs respectively to the comparators COM 1 and COM 2, but the amplifier output re- mains connected to the comparator COM 3 During nulling (as will be explained) the Integrating Ampli- fier is initially driven to force the output to go high.

The balancing process decrements the offset to the point where a current reversal occurs at the output of the Integrating Amplifier, causing the amplifier output voltage to fall precipitously toward Vss The fall is intercepted at Vref 2 by COM 3 which gener- ates a pulse as the null is achieved, which termi- nates the nulling sequence upon the next 20 K Hz clock pulse The transmission gate U 85 also re- connects the integrating capacitor at the same K Hz clock pulse and the charging "reset" of capacitor C 5 toward Vdd commences The duration of the nulling period is a variable depending upon the amplifier imbalance The maximum count available in the present design allows for 32 counts at the 20 K Hz clocking rate or approximately 1 5 milliseconds for a maximum duration for nulling.

Assuming a reset time of about 5 milliseconds, the nulling is designed to accommodate a motor of the indicated design rotating at 20-200 rpms, allowing an interval of from 17 to 170 ms between commu- tations.

The Figure 8 waveform illustrates both the ap- proximate time scale (for a fast rotation) and the approximate values of the critical voltages in the commutation timing and nulling process The volt- age of Vref 4 is set slightly less than the Vdd sup- ply voltage less one threshold drop plus "one Vds on" (i e Vds which occurs for Ids= 0) The voltage of Vref 4 is set close to but below the upper satu- ration voltage of the Transconductance Amplifier.

The voltage of Vref 4 should be small enough to assure that the amplifier saturation voltage is greater than that value The amplifier outp 4 it will be forced all the way to positive saturation by the positive back-emf signal which is occurring during this time An error in commutation degrees may occur if the back emf does not saturate the Tran- sconductance Amplifier prior to the zero crossing of the back emf, and the capacitor does not start to discharge from a full charge The typical value for a Vdd of 9 volts is 6 5 volts for Vref 4.

The voltage of reference Vref 3 is somewhat ar- bitrary, and is selected to be significantly below Vdd/2 The voltage of Vref 3 should stay above the negative saturation voltage of the amplifier A typi- cal value for Vref 3 is 3 volts.

The value of Vref 2 is chosen below Vref 4, but the exact value is not critical Vref 2 is selected to signal the end of the nulling process Since the Amplifier 141 is disconnected from the capacitor C 5 during nulling, the load on the Amplifier is very light, and the amplifier output voltage falls very rapidly after the null has been crossed The nulling interval is timed by 20 K Hz clock counts Setting Vref 2 too low may allow additional counts to oc- cur after the null, which lessens the accuracy of nulling A reasonable value for Vref 2 is about 5 5 volts.

A more complete understanding of the Compara- tor Network 142 requires resort to the timing dia- grams of Figure 12 A, in particular, which illustrates the output of the comparators COM 1-3 already de- scribed, on a time scale large enough to show the individual 20 K Hz clock pulses, and assumes a null- ing procedure requiring only a few increments The Null Set waveform is alternately the COM 3 output.

The drawing also shows the 20 K Hz clocking pulses, the Null Clocking Signal (D 17 Q), the Null Output Signal (D 7 Q) which is high during nulling; the Re- set 2 waveform (U 83 Output) which is high during capacitor C 5 reset; and the Reset 1 waveform (D 16 Q) which is high during nulling and the reset of ca- pacitor C 5.

Starting consideration of Figure 12 A from the commutation instant when comparator COM 2 goes high (as the voltage on C 5 falls below the 3 volts on Vref 3), the output of comparator COM 2 I GB 2 177559 A 21 goes high; and the U 80 output goes low With both D inputs of D 16 and D 17 high by the Vdd con- nection, the negative going edge from U 80 output clocks the Q outputs of D 16, D 17 high The Q out- put of D 16 supplies the Reset 1 waveform to the Modulo 6 Counter 144, and the Input Gating 140.

The Q output of D 17 (Null Clock) is connected via the inverter U 92 to the C input of D 6 and to the R inputs of D 7 and of the counter D 8-D 12 When the Null Clock waveform goes high, Q 1 to Q 5 go low; and Q 1 to Q 5 go high The flip-flops set 55 to 58 high and set 51 to 54 low, acting via gates U 99- U 106 As will be explained, this forces the output ( 152) of the Integrating Amplifier to swing from low starting from Vref 3 (e g 3 volts) toward high ( 6.5 volts) as shown in Figure 8.

The Null Clock waveform going high also resets flip-flop D 7 (Q low), which in turn disables the gate U 85, disconnecting the Integrating Amplifier 141 from the integrating capacitor C 5, allowing the autonulling sequence to begin.

As the voltage at the output ( 152) of the Integrat- ing Amplifier increases through Vref 2 ( 5 5 volts), see Figure 8, the output COM 3 (U 81) goes low, re- setting D 17 (Q low), removing forced reset from the Autonull Circuit, and the autonulling process begins (which will be treated subsequently) When the output of U 92 goes high, flip-flop D 6 is set by its positive going edge This enables U 93, which allows the clock signal toeach the counter D 8- D 12.

When the decrementing causes a downward swing in the Amplifier output (see Figure 8) below Vref 2 at the input to COM 3, a balance has been detected, and nulling is terminated The output of COM 3 (U 81) and the Null Set waveform goes high This causes the D input to D 7 to go high The clock input to D 7 is coupled to the output of U 93, which NANDS the 20 K Hz clock (CLK) with the out- put of D 6 (now high) When the next 20 K Hz pulse occurs after D 7:D has gone high, U 93 clocks D 7, and the null output (D 7 Q) goes low The immedi- ate effect of this (D 7 Q) low output is to enable the transmission gate U 85 This connects the Integrat- ing Amplifier to C 5 Simultaneously, with both D 16, Q low, and D 7, Q low, NOR gate U 83 goes low, ini- tiating the Reset 2 pulse When D 7, Q goes low, D 6 is reset (Q low) This disables U 93 removing the clock signal from the counter "freezing" the count at its present value.

As Reset 2 goes high, the Integrating Amplifier via Q 9, Q 18 and Q 23 begins to supply charging current to reset C 5 The capacitor continues to charge until Vref 4 is exceeded at the input to C 1 (see Figure 8) When COM 1 goes high (in about 4 milliseconds), D 16, Q goes high, and Reset 2 is also terminated, discontinuing the resetting of C 5, and allowing the capacitor integration period to begin.

In the event of significant imbalance "off" the IC, e.g due to errors in the resistance ratios of the re- sistor divider network 125, a discharge means should be provided for C 5 to prevent this imbal- ance from halting the application of successive starting commutations to the motor and preventing starting The NPN transistor Q 92, having its collec- tor connected to the pad P 1, its emitter returned to ground through 240 K resistor R 41, and its base coupled to node 129 to provide forward bias, is the preferred discharge means A resistor could be used (approximately 2 meg) but it has the disad- vantage of having a relatively small current near the lower threshold of Vref 3 ( 2-1/2 to 3 volts) The current error produced in the single in line package "SIP" resistor network 125 could be as high as 2 piamps, which is enough to prevent the circuit from reliably starting.

The transistor current source herein provided has the same average current as the current that is generated when the trip voltage is reached and should always be capable of ( 1) overcoming the er- ror in the single in line package (SIP) resistor net- work and ( 2) providing a commutation period in excess of 0 2 seconds for good starting perform- ance The current is set for at least 2-1/2 pamps which provides a commutation period of 0 3 + sec.

with the indicated 15 pif capacitor C 5 and provides a margin over the 2 p amp SIP error.

The upper limit for current drain is approxi- mately 3 5 l amp because this will provide a start- ing period of 0 2 sec, the smallest permissible to guarantee smooth starting performance The lower limit for current drain is approximately 2 Lamps, which is set by the current error due to the SIP re- sistor tolerance.

The offset error in commutation timing caused by the current source Q 92 becomes negligible at medium and high RPM.

The autonull circuit 143 The Autonull Circuit "Nulls" the Integrating Tran- sconductance Amplifier 141 to remove any error in timing the commutation instant attributable to am- plifier input offset and to improve motor starting performance As shown in Figure 8, the autonulling circuit is operative after the commutation instant.

The commutation instant occurs when the volt- age on the Capacitor C 5 falls below Vref 3 applied to COM 2, which causes D 16 Q, at which the Reset 1 waveform is derived, to go high, and the Null Clock waveform derived at D 17 Q to go high.

When the Reset 1 waveform goes high, the switches Q 7 and Q 8 at the input to the Integrating Amplifier are turned on, shorting out any differential input voltage at the gate of the input transis- tors Q 5 and Q 6 At the same time, the gates of both Q 5 and Q 6 are returned to a 3 volt reference (Vrefl), selected to be equal to an average value of the amplifier common mode voltage over the nor- mal operating range.

The Null Clock waveform from D 17 Q is coupled to the Autonull Circuit It causes D 7 Q to produce the Null Output waveform which is coupled back to the input to the transmission gate U 85, disabling the gate and disconnecting the output of the Inte- grating Amplifier from the Capacitor C 5 and the Comparators COM 1 and COM 2.

The Null Clock waveform from D 17 Q also resets and holds the Autonull Circuit in a preassigned ini- tial state in which a maximum offset (+ 12 lLa) is ap- 22 GB 2 177559 A plied to the Integrating Amplifier sensed to pro- duce an assured current supply at the amplifier output.

By these three events, the output voltage of the amplifier previously at 3 volts, begins to climb, and when it exceeds 5 5 volts at Vref 2, COM 3 pro- duces a low in the Null Set waveform The low in the Null Set waveform is accompanied by a low in the Null Clock waveform at D 17 Q This releases the Autonull Circuit from its initial state, and allows decrementing of the offset at the amplifier input.

Decrementing occurs at the rate of the 20 K Hz clock coupled to the input of gate U 93 When the output voltage of the amplifier falls below Vref 2, balance is achieved.

At the next clock pulse, the Null Output wave- form (D 7 Q) goes low, enabling the transmission gate U 85, and causing the generating of the Reset 2 pulse, which as earlier noted, turns the Integrat- ing Amplifier into a maximum current supply mode ( 150 la) for charging Capacitor C 5 When the upper voltage reference Vref of 6 5 volts is crossed, both Reset 1 and Reset 2 terminate, and the next capacitor integration period commences.

The Autonull Circuit 143 is depicted in Figure 7.

It includes the resistive elements (R 3, R 4) of a modified current mirror (Q 10,Q 11), which is in one channel of the two channel differential input Inte- grating Transconductance Amplifier 141 The cur- rent mirror is modified by the inclusion of means for introducing a digitally controlled offset current ( 51-58, Q 65-Q 68), a counter (D 8-D 12) for achieving a large initial current offset followed by an ordered decrementing of the offset current to the desired fi- nal value, the counter also storing the final decre- mented state, a decoder (U 99-U 106) for translating the counter state to appropriate offset current set- tings, and control logic interfacing with the remain- der of the control IC for initiating the nulling process and for terminating the process when a null in the amplifier output has been produced.

The digitally controlled current mirror consists of a first set of 4 digitally scaled resistances R 3 A, R 3 B, R 3 C and R 3 D, and a second set of 4 digitally scaled resistances R 4 A, R 4 B, R 4 C and R 4 D; a first set of four N-channel transistor switches 58-55 as- sociated with the first set of resistances R 3 A-D; a second set of four N-channel switches 54-51 asso- ciated with the second set of resistances; a set of four P-channel current source transistors 068-Q 65, each associated with the supply of current to a switch in each set of switches; and a current refer- ence made up of transistors Q 59-Q 64 for the cur- rent sources Q 65-Q 68.

The elements of the decrementing current sink are interconnected as follows The resistances R 3 A, R 3 B, R 3 C and R 3 D are serially connected in the or- der recited between the source of the reference transistor Q 10 in the current mirror Q 10, Q 11 and the IC ground, while the resistances R 4 A, R 4 B, R 4 C and R 4 D are serially connected in the order recited between the source of the output transistor 011 in the current mirror and IC ground The "A" resis- tors are of 4 units magnitude, e g, 1000 Qf; the "B" resistors are of 2 units magnitude, e g 500 Qf; and the "C" and "D" resistances are of 1 unit magni- tude, e g 250 f Q.

A current source is provided for supplying cur- rent via a first transistor switch to each tap on R 3, or via a second transistor switch to a correspond- ing tap on R 4 Starting from the taps above R 3 D and R 4 D, the current source Q 65 has its source connected to Vdd, and its drain jointly connected to the drain of transistor switch 55, whose source is connected to the series resistance R 3 above R 3 D, and to the drain of transistor switch 51 whose source is connected to its series resistance R 4, above R 4 D The current source Q 66 has its source connected to Vdd, and its drain jointly connected to the drain of transistor switch 56, whose source is connected to the series resistance R 3 above R 3 C, and to the drain of transistor switch 52 whose source is connected to the series resistance R 4, above R 4 C The current source 067 has its source connected to Vdd, and its drain jointly connected to the drain of transistor switch 57, whose source is connected to the series resistance R 3 above R 3 B, and to the drain of transistor switch 53 whose source is connected to the series resistance R 4 above R 4 B The current source Q 68 has its source connected to Vdd, and its drain jointly connected to the drain of transistor switch 58, whose source is connected to the series resistance R 3 above R 3 A, and to the drain of transistor switch 54 whose source is connected to the series resistance R 4, above R 4 A.

The current sources Q 65-Q 68 are of 45/12 geom- etry and have four gates tied to a common current reference comprising the transistors Q 69-Q 64 The current reference transistors are connected in two series paths The P-channel transistor Q 59 has its source connected to Vdd and its drain connected to the drain and gate of N-channel transistor Q 61.

The source of Q 61 is connected to the drain and gate of N-channel transistor Q 62 The source of Q 62 is connected to the drain and gate of N-chan- nel transistor Q 63, whose source is connected to IC ground Transistor Q 59 is of 4/40 geometry, while transistors Q 61-Q 63 are of 25/4 geometry The sec- ond series path in the reference comprises a Pchannel transistor Q 64 having its source connected to Vdd and its gate and drain tied together and to the drain of N-channel transistor Q 60 The source of Q 60 is connected to IC ground and the gate is connected to the interconnection between Q 59 and Q 61 The arrangement establishes a current of about 18 microamperes in the reference and be- cause of the geometry ratio, currents of about 6 pa in each of the current sources Q 68-Q 65.

A current offset between input and output cur- rent in the Q 10, Q 11 current mirror of the Integrat- ing Amplifier is achieved by the settings of the respective switches 51 to 58 The gate to ground voltage of the transistor Q 11 is held into equality with the gate to ground voltage of Q 10 If all switches 51-58 are off, and assuming that the re- sistances R 3 and R 4 are equal, then the current in Q 11 will accurately mirror the current in Q 10 If, however, a 6 pa current is injected into a part of R 3 (e g, R 3 D by conduction of switch 55,) a small in- G 2 B 2 177559 A 23 crease in gate to ground voltage will occur in Q 10; and the increase in current should cause an equal IR drop in R 4 Since R 3 D is 1/8th of the total resist- ance of R 3, which equals R 4, the 6 p La current in- jected by Q 65 in R 3 D produces a positive offset of approximately 6 8 lLa in the output current of the mirror If all switches 55 to 58 are conductive, a positive offset of approximately 12 lLa in output current in Q 11 may be expected with respect to the input current in Q 10.

If switches 54 to 51 are operated, it being as- sumed that switches 58 to 55 are open, then the output current is decreased in relation to the input current by comparable decrements: 6/8 lLa when 51 is conductive, and negative offset of approximately 12 lLa when 51-54 are all conductive The result is to give a control range of approximately 24 Ra for nulling the amplifier.

The immediate control of the states of the switches 51-58, which control the offset current in the current mirror is provided by the 5 stage counter D 8-D 12, and the decoder consisting of 8 NOR gates U 99-UL 106 interconnecting the output stages of the counter to the gates of the individual switches The counter is in turn controlled by the control logic which comprises the gates U 92-U 94 and the flip-flops D 6 and D 7 The decrementing of the counter occurs at the 20 K Hz clock rate of the Oscillator 147.

The switches, counter, decoder and control logic of the Autonull Circuit are interconnected and ex- change control waveforms as follows The two control waveforms applied to the Autonull Circuit are the Null Clock waveform derived from D 17 Q and the Null Set waveform derived from the com- parator COM 3 (i e, U 81) both in the Comparator Network 142 The Null Clock waveform is con- nected to the input of inverter U 92, whose output is coupled to the C input of the flip-flop D 6 and to the R input of the flip-flop D 7 and to the R inputs of the counter D 8-D 12 The D input of the flip-flop D 6 is connected to Vdd The Q output of D 6 and the 20 K Hz clocking waveform CLK from Oscillator 147 are each coupled to one of the two inputs of NAND gate U 93 The output of the NAND gate U 93 is directly coupled to the C input of D 7, and after inversion by interter U 94, is coupled to the C input of D 8, the first flip-flop in the 5 stage counter.

The Null Set waveform is coupled to the D input of the flip-flop D 7 The Q output of D 7 is coupled to the R input of D 6 The Nulil Output waveform of the Autonull Circuit, responsive to detection of a Null by the COM 3 in the Comparator Network, is derived from D 7 Q.

In the 5 stage counter, the count is propagated by connecting the Q 1 output of D 8 to the C input of D 9 Similarly, the Q 2 output of D 9 is connected to the C input of D 10; and Q 3 output of D 10 is cou- pled to the C input of D 11, and the Q 4 output of D 11 is connected to the C input of D 12 Also on the Counter, the D and Q 1 terminals of D 8 are joined, as are D and Q 2 terminals of D 9 Similarly, the D and Q 3 terminals of D 10 are joined, the D and Q 4 terminals of D 11 are joined, and the D and Q 5 ter- minals of D 12 are joined.

The 8 NOR gate (U 99-U 106) form the decoder which translates the states of the counter D 8-D 112 to appropriate settings for the switches 51-58 in achieving the desired offset current The 4 NOR gates U 103 to U 106 couple the Q 1 to Q 5 inputs to the switches 55-58 More particularly, the NOR gate U 103 has one input connected to Q 1 and one input connected to Q 5and its output connected to the gate of 55 NOR gate U 104 has one input con- nected to Q 2 and one input connected to Q 5 and the output of U 104 is connected to the gate of 56.

Similarly, one input of NOR gate U 105 is con- nected to Q 3 and one input is connected to Q 5, and the output of U 105 is connected to the gate of 57 Similarly, one input of NOR gate U 106 is con- nected to Q 4 and one input is connected to Q 5 and the output of U 106 is connected to the gate of 58.

If Q 5 is low, the NOR gates U 103-U 106 are enabled so that a low on any of the Q 1-Q 4 counter termi- nals will produce a high at the output of the appro- priate NOR gate and turn on the appropriate switch 55-58.

_The 4 NOR gates U 99 to U 102 coupled the Q 1 to Q 5 outputs of the counter to the switches 51-54.

More particularly, the NOR gate U 99 has one input connected to Q 1 and one input connected to Q 5 and its output connected to the gate of 51 NOR gate 100 has one input connected to Q 2 and one input connected to Q 5 and the output of U 100 is connected to the gate of 52 Similarly, one input of NOR gate U 101 is connected to Q 3 and one input is connected to Q 5 and the output of U 101 is con- nected to the gate of 53 Similarly, one input of NOR gate U 102 is connected to Q 4 and one input is connected to Q 5 and the output of U 102 is con- nected to the gate of 54 If Q 5 is low, the NOR gates U 99-U 102 are enabled so that a low on any of the Q 1-Q 4 counter terminals will produce a high at the output of the appropriate NOR gate and turn on the appropriate switch 51-54.

Resetting the counter produces a maximum po- sitive offset current ( 12 iia) in the current mirrors by initially turning switches 55 to 58 on and 51 to 54 off The effect of "clocking" the current from a Re- set condition of the counter is to decrement the maximum positive offset current in 3/41 La decre- ments through zero offset current until all switches to 58 are off and then to progressively more negative offset currents until a maximum negative offset current ( 12 p La) is produced when switches 55 to 58 are off and 51 to 54 are on.

The state of switches and offset currents result- ing from resetting the counter and then decre- menting may be explained as follows The first counter stage D 8 is associated with the lowest (first) rank switches 51 and 55 The second counter stage D 9 is associated with the second rank switches 52 and 54 The third counter stage D 9 is associated with the third rank switches 53 and 57.

The fourth counter stage is associated with the fourth rank switches 54 and 58.

If the counter D 8-D 12 _is reset, the Q 1-Q 5 outputs are set to zero and the Q 1-Q 5 outputs are high.

Under these conditions, the switches 51-54 are open and the switches 55-58 are closed Accord- 24 GB 2 177559 A ingly, a maximum positive offset current ( 12 a) is caused in the output current of the current mirror Q 10, Q 11 (and the output of the Integrating Tran- sconductance Amplifier goes high) If the counter is now clocked periodically from the C input of D 8, with the stages Q 1-Q 4 initially at zero, the first clock pulse (after transfer to Q 1) will cause the first stage of the counter to go high, which turns off 55 and which produces a 6/8 lLa decrement in the off- set current The counter state is 00001 The next clock pulse will produce a low at Q 1 and a high at Q 2 This will turn switch 55 back on and turn off 56, causing a decrement in current of 1-1/2 lta The counter state is 00010 This process will continue for 16 counts until all switches 51-55 are turned off and the counter state is 01111.

The transfer to a negative offset current occurs at this point in the count On the next count, 05 goes high, disabling the gates U 103 to U 106 and the counter state, as seen at the Q 1 to Q 5 outputs is 10000 On the same 10000 count, Q 5 (comple- mentary to 05) goes low, enabling the gates U 99 to U 102 so that additional counts will progressively turn on switches 51 through 54 On the same 01111 count, as seen at the Q 1 to Q 5 outputs, the switches 55 to 58 are turned off On the next count, thecounter state will be 01110, as seen at the Q 1 to Q 5 outputs and switch 51 will be turned on The count will now proceed as before, until all switches 51-54 have been turned on, producing a maximum negative offset current 12 pa, and the counter state is 00000 as seen from the Q 1 to Q 5 outputs In normal operation, the count will be sus- pended at some point in the counting sequence by detection of a null that will halt the count between the maximum positive offset current and the maxi- mum negative offset current.

Assuming that the comparator COM 2 has gone high to signal the commutation instant, D 16 Q, at which the Reset 1 waveform appears, goes high.

The Reset 1 waveform shorts out the differential input to the Integrating Transconductance Ampli- fier input, readying it to begin the nulling process.

Clocked also by the output of COM 2, D 16 Q, at which the Null Clock waveform appears, goes high.

The Null Clock waveform is coupled via the in- verter U 92 to the clock input of D 6 to the resets of D 7 and the counter stages D 8 through D 12.

The D input to D 7, which is coupled to the out- put of COM 3 (i e, U 81) has been high since the amplifier output fell below 5 5 volts Thus, the Null Clock waveform at the reset input of D 7 produces a high at the D 7 Q output at which the Null Output waveform appears The Null Output waveform is coupled back to one input of the NOR gate U 83 and to the control input of the transmission gate U 85 While no change occurs at the NOR gate U 83, the transmission gate is disabled, and the output of the Integrating Amplifier is now disconnected from the integrating Capacitor C 5 and from the in- puts of the Comparators COM 1 and COM 2 The amplifier output is now ready for nulling.

With the Null Clock waveform high, the counter is reset and held in a reset state in which a maxi- mum positive offset current is produced At this point, the differential amplifier input is shorted, a maximum positive offset current is introduced at the input, and the amplifier output, disconnected from the Capacitor C 5, is coupled to the comparator COM 3, and the counter (D 8-D 12) is reset, hold- ing the offset current at the maximum value The output voltage of the amplifier which was near 3 volts upon commutation, begins to increase When the amplifier output voltage exceeds 5 5 V, COM 3 goes low, resetting D 17 Q (i e, Q goes low), and the Null Clock waveform appearing at D 17 Q goes low The Null Clock waveform coupled via U 92 and inverted to a high, releases D 7, and releases the counter D 8 to D 12, allowing the counter to incre- ment in a direction to reduce the offset current, whenever 20 K Hz clocking pulses are supplied.

Meanwhile, the 20 K Hz clock pulses from Oscilla- tor 147 have been coupled to one input of the NAND gate U 93, whose other input is coupled to the Q output of D 6 The Q output of D 6 went high when D 7 was reset, enabling NAND gate U 93, and coupling clock pulses directly to the C input of D 7, and after inversion in U 94 coupling inverted clock pulses to the C input of the counters D 8-D 12 The incrementing can now proceed.

The counter continues to decrement the current offset at the 20 K Hz clocking rate, and the compara- tor COM 3, to which the amplifier output is con- nected, senses a drop in the amplifier output voltage When the voltage falls below 5 5 volts (Vref 2), the Null Set waveform (COM 3 output) goes high, coupling a high to the D input of D 7.

Upon the next positive going edge of the 20 K Hz clock pulse (CLK) from U 93, coupled to the C input of D 7, D 7 Q, which provides the Null Output wave- form, goes low When D 7 Q goes low, it resets D 6.

(D 6 Q goes low) This effectively disables U 93 from coupling clock pulses to D 7 and D 8 The output of U 93, which is now high, is forced to remain high by the application of a low to one input This also forces the clock input of D 8 to remain low, inhibit- ing another positive going edge from occurring and assuring that the counter state is "frozen" at the value which resulted in the null just detected.

The inversion in U 94 delays the response of D 8 by approximately 300 nanoseconds relative to the response of D 7 This inversion assures that the po- sitive going clock edge of the CLK waveform sup- plied to D 7 occurs about 300 nanoseconds before the positive going clock edge of the CLK waveform supplied to D 8 (The difference is due to the width of the narrow portion of the CLK waveforms The clock pulse has a duty cycle of lessthan 1 %) The Null Output waveform (D 7, Q) having gone low, is coupled to the transmission gate U 85, and to the NOR gate U 83 U 85 is now enabled and re- connects the output of the Integrating Amplifier to C 5, and to the comparators COM 1 and COM 2 Si- multaneously, U 83 with two lows upon its input (D 17 Q low and D 7 Q low) goes high, generating the Reset 2 pulse The Reset 2 pulse turns on the upper output portion (Q 27) of the Amplifier 141, and with the connection made via U 85 to the capacitor, the resetting of the capacitor is undertaken as shown in Figure 8 When comparator COM 1 G 2 B 2 177559 A 25 detects that Vref 4 is exceeded, the next capacitor commutation period begins again.

Modulo 6 counter 144 The Modulo 6 Counter is a reversible counter which maintains a count of the rotor commutation events and position so that the winding sensing sequence and the winding energization sequence keep in step The Modulo 6 Counter, consistently with a 6 state succession of energization states, re- petitively counts to 6, and each counter state corre- sponds to one of the 6 energization states illustrated in Figure 3 As earlier noted, the forward sequence and reverse sequences are both illus- trated The event which steps the counter is the production of the Reset 1 pulse from D 16, Q at the commutation instant One output of the counter (the unenergized winding selection signals), in the form of one unique state at one of 6 sequential po- sitions, is coupled via a 6 conductor connection to the enabling gates U 73-U 78 of the input gating Another output of the counter deals with two state combinations, suitable when applied to the control logic 145 for forming the energized winding selection signals, for jointly energizing two wind- ings in the stepping sequence illustrated in Figure 3 A third output of the counter is the "Least Sig- nificant Bit" (BO; D 1 Q) used to invert the sense of the neutral winding connection to the input gating (U 55, U 56) in synchronism with the gating wave- forms applied to U 73-U 78 The controls applied to the modulo 6 counter include a Forward waveform from Forward/Reverse Logic 149 (U 112), and a Power on Reset waveform (POR; U 120).

The Modulo 6 Counter 144 consists of the fol- lowing logical elements: three flip-flops D 1, D 2, D 3 forming the memory of the counter; three two in- put NAND gates U 8, U 9, U 10, associated with D 2 for decoding from the counter output stages the correct next state for D 2 in either a forward or re- verse counting sequence, three two input NAND gates U 20, U 21, U 22 associated with D 3 for decod- ing from the counter output stages the correct next state for D 3 in either a forward or a reverse count- ing sequence; a first rank of three input NAND gates U 24-U 29, for decoding the memory states of D 1-D 3 to obtain a unique state (low) which follows the counting sequence; and a second decoder rank of two input NAND gates for detecting 2 state combinations for application to the control logic Finally, a pair of inverts U 12, U 7 is provided for introduction of the Forward waveform to the

Counter.

The elements of the Modulo 6 Counter 144 are connnected as follows The R inputs of the D 1-D 3 flip-flops are connected for power on reset to POR (U 120 POR) In starting, POR is low, holding D 1, D 2, D 3 in a Q low Q high state When POR goes high, the count may proceed The D 16, Q out- put (Reset 1) is connected to the clock (C) inputs of D 1, D 2 and D 3 The Q output of D 1 is connected to the D input of D 1 The Q output of D 1 is coupled to one input of NAND gates U 25, U 27 and U 29 The Q output of D 1 is coupled to one input of U 24, U 26 and U 28 The Q output of D 2 is coupled to one in- put of U 26 and U 27 The Q output of D 2 is con- nected to one input of U 24, U 25, U 28 and U 29 The Q output of D 3 is connected to one input of U 28 and U 29 The Q output of D 3 is connected to one input of U 24, U 25, U 26 and U 27.

The three input NAND gates U 24-U 29 in the first rank of memory decoders are arranged by the foregoing connections to provide a consecutive repeating succession of unique low states of U 24, U 25, U 26, U 27, U 28, U 29, U 24, U 25, U 26, etc as the memory of D 1, D 2, D 3 is incremented At the initial state of the memory, U 24 is low The zero bi- nary state ( 000) may be verified by noting that U 24 has its three inputs connected to D 1, Q; D 2, Q and D 3, Q When the inputs are high, the U 24 output is low (and all other NAND gates are high) This is the "CSO" state Assuming that one count has oc- curred, and D 1, Q is now high, U 25 which has its three inputs connected to D 1, Q; D 2 Q; and D 3 Q (all high), the U 25 output is low and the other NAND gates are high This may be called the bi- nary state 001 or the "CS 1 " state That this decod- ing continues may be verified as to each successive counter state At the next binary state ( 010 or the "CS 2 " state): U 26 connected to D 1, Q (high); D 2, Q (high); and 03, Q (high) goes (low).

At the next binary state ( 011, U 27 goes low, etc).

The low state remains unique in the NAND gate U 24-U 29 outputs, which are connected respectively via NOR gates U 73-U 78 to the inputs of transmission gates U 62, U 64, U 66, U 68, U 70, U 72, respec- tively, so that only one of the above transmission gates is enabled at one time, and it is enabled in the desired consecutive repeating succession.

The two input NAND gates U 30-U 35 in the sec- ond rank of memory decoders aid in transferring the state of D 1 to D 2 to D 3 in forward and reverse counting and in commutating the sequence in either a forward or a reverse count This first re- quires "O Ring" two succesive states in the first rank of NAND gates for coupling to the second rank The second rank is also used to further the decoding required for the Control Logic and Output Drivers In particular, U 30 NAN Ding the outputs of the U 24 and U 25, is high on the first two states and goes low on the third state when U 24 and U 25 are both high, and it remains low until the end of the count U 31 NAN Ding the outputs of U 25, U 26 (C 51, C 52) (equivalent to O Ring the active high states C 51, C 52), is low on the first state, high on the next two and low on the last three states.

NAND gate U 32 NAN Ds the outputs of U 26, U 27; NAND gate U 33 NAN Ds the outputs of U 27, U 28; NAND gate U 34 NAN Ds the outputs of U 28, U 29; and NAND gate U 35 NAN Ds the outputs of U 29, U 24.

Only the Forward waveform is applied to the Modulo 6 Counter, and both low and highs of that waveform are used to control the Counter for a forward or reverse count The Forward waveform from U 112 is applied to U 12, U 7 It is inverted in U 12, and re-inverted in U 7 The U 8, U 9, U 10 gate assembly associated with counter D 2 sets the next state for D 2 depending on whether the counter is in a forward or reverse mode Similarly, the U 20, 26 GB 2 177559 A U 2 o 1 and U 22 gate assembly associated with counter D 3 sets the next state for D 3 depending on whether the counter is in a forward or a reverse mode The gates U 8 and U 9 have their outputs coupled to NAND gate U 10, whose function is to "OR" the inputs into the D input of D 2 Similarly, the gates U 20 and U 21 have their outputs coupled to NAND gate 22, whose function is to "OR" the inputs into the D input of D 3 When the counter is in a forward mode, the gate U 9 is driven by U 31, which decodes states C 51, C 52 if a "low" is pres- ent on either state it produces a high at the input of U 10, which is coupled via U 10 to the D input of D 2 At the same time the output from U 12, which is in the inverse of the output of U 7, is coupled to U 8 and to U 20 This signal which puts a low on the input of U 8 and U 20, inhibits the decoded output stage (if low) from being fed back to the D inputs of D 2 and D 3, respectively.

The transfer of states between flip-flops D 1-D 3 and formation of the desired consecutive repeating succession is performed in the following manner.

In the Forward state, the Forward waveform is high (see Figure 3), and U 12 out is low, U 7 is high, mak- ing U 9 and U 21 active in transferring the count D 2 and D 3 U 9 NAN Ds the output of U 7 and the out- put of U 31 U 31 is high on the 001 (C 51 low) and (C 52 low) states On the state 001, U 9 goes low, and U 10, irrespective of the input, goes high, which is coupled to the D input to D 2 Upon the next commutation, Reset 1 clocks a high into the Q output of D 2 and D 1 increments again to 010 (C 52 low) On the state 010 (C 52 low), U 31 remains high and U 9 goes low again, and U 10, irrespective of its other input, goes high at the D input to D 2 Upon the next commutation, Reset 1 clocks the second high into D 2, and D 2 Q stays high ( 011; C 53 low).

Upon the next count, U 33 goes high, U 21 goes low, and U 22 goes high The next Reset 1 pulse clocks a high into D 3, Q out, and a low into the D 1 Out for a ( 100: C 54 low) The next Reset 1 pulse, U 33 remains high and a high is reclocked into D 3; Q low into D 2, Q; and a high into D 1, Q ( 101: C 55 low) In the next Reset 1 pulse lows are clocked into D 3 and D 2 and D 1 changes state to ( 000: CSO).

In the reverse state, the Forward waveform is low (see Figure 3) and U 12 is high, U 7 is low mak- ing U 8 and U 20 active in transferring the count to D 2 and D 3 The sequence is now inverted with U 29 becoming low first (C 55 low); U 28 low next (C 54 low), etc until U 24 is low last Assuming the D 1, D 2 and D 3 are low at the start of the count, U 29 which is tied to the O outputs of D 1, D 2, D 3, goes low on the first count corresponding to C 55 low state (The backward count will continue in the same manner already explained) The NAND gates U 30-U 35 also aid in decoding the states CSO to C 55 for application to the Control Logic 145 As noted above, U 30, which NAN Ds the U 24, U 25 outputs, is in an active high state during CSO and C 51; U 31 is in an active high state during C 51 and C 52; U 32 is in an active high state during C 52 and C 53; U 33 is in an active high state during C 53 and C 54; U 34 is in an active high state during C 54 and C 55; and U 35 is in an active high state during C 55 and C 50 In short, by a 6 count 6 over lapping timing waveforms have been created, or- dered in correspondence to the high durations of CT; AB; BT; CB; At and BB (shown in Figure 3), re- spectively These timing waveforms can be cou- pled to the Control Logic 145 for timing the output signals coupled to the Output Drivers 146.

The Modulo-6 commutation counter ( 144) is vir- tually two counters in one, an up counter and a down counter sharing both the flip-flops D 1, D 2, D 3 and parts of the decoding logic (U 10, U 22, and U 29-U 35).

The up or down counter is enabled/disabled by the Forward control signal When the forward gates U 9, U 21 are enabled, they decode the-out- puts of the counter flip-flops D 1, D 2, D 3 and set the inputs of these flip-flops to the values required for the next state At the rising edge of the RESET 1 signal, these inputs are transferred to the output side of the positive edge triggered flip-flops (D 1, D 2, D 3) Since this transition occurs simultaneously with the edge of the incoming RESET 1 signal, each flip-flop is clocked at exactly the same time.

This prevents the outputs from changing at differ- ent times (i e, not in synchronization) and causing voltage spikes (glitches) to appear at the counter outputs.

When the outputs of the flip-flops change state at the rising edge of the RESET 1 pulse, they are decoded into a variety of state signals (CSO, C 51 C 55) by gates U 24 to U 29 Combinations of these states are also decoded by U 30 to U 35 This de- coding occurs, substantially simultaneously with the rising edge of the RESET 1 signal Any slight delay due to propagation delays (e g, < 100 nano- seconds) through the gates, is several orders of magnitude less than the time it takes for the next rising edge of RESET 1 to occur (milliseconds) Be- cause of this, these signals (which are fed back to the inputs of D 1, D 2 and D 3 to set the next state) will attain a steady value by the time the next ris- ing edge of RESET 1 occurs Having this stable in- put available at the inputs of the flip-flops ensures proper "Glitch-free" operation of the counter.

The decoding of each state and synchronous clocking of the flip-flops causes the length of each state to be fixed, and dependent on the length of the RESET 1 pulse and not on the specific state that the counter is in This is especially important when, in the forward direction, the count reaches 5 and must then go to 0 This counter treats the 5 to 0 transition as just another state transition rather than causing the counter to be RESET when the counter reaches the end of its count Simply reset- ting the counter at the end of the count would re- sult in the unwanted shortening of the last state or "Glitches" when performing the RESET The state transitions for the forward case are 0 to 1, 1 to 2, 2 to 3, 3 to 4, 4 to 5, 5 to O, etc The necessary outputs for the "next" state are available from the gates U 24 to U 29 which decode the individual states and combinations of these states which are available from gates U 30-U 35 and returned via gates U 8,U 9,U 10,U 20,U 21, U 22 The gates U 24- U 35, serve the dual function of providing the next GB 2 177559 A 27 state to the commutation counter as well as pro- viding an indication of the present state, or combi- nation of states, to other circuits on the chip.

The reverse gates U 8 to U 20 operate in a similar fashion when enabled by the forward signal In the reverse mode though, the state transitions are 0 to 5,5 to 4,4 to 3,3 to 2,2 to 1,1 to O,etc As mentioned before, the counter can only change state on the rising edge of the RESET 1 signal This ensures that even if the count direction is changed from forward to reverse by switching the "For- ward" signal line, no pertubations (glitches) will occur in the output of the counter Thq counter will stay in the present state for its correct amount of time and will then continue counting in the oppo- site direction upon the next rising edge of the RESET 1 pulse.

All of the flip-flops of the counter are equipped with an asynchronous RESET This RESET is con- trolled by the Power On RESET circuit ( 150) When the POR line is low, the counter is held in its 000 (zero) start state When the RESET line POR is released (allowed to go high), the counter will start counting on the next rising edge of RESET 1 and transition to the next correct state after 0 ( 5 for re- verse direction, 1 for forward direction).

Since there are three memory elements in the counter D 1, D 2, D 3, there are 8 possible states that could occur ( 0-7) In the event that the counter would find itself in one of the unused states ( 6 or 7) the counter is designed so that it will transition to a correct state (into the regular counter loop) should one of these states occur Also the decoder logic U 24-U 29 has been designed not to decode these two states should they occur This is so their occurance does not cause problems to any other logic connected to this circuit.

The control logic 145 The Control Logic 145 accepts the timing information from the Modulo 6 Counter at the outputs of gates U 30 to U 35, and converts that information into a collection of waveforms suitable for applica- tion to the Output Drivers 146 on the IC for appli- cation to the three power switches 122, 123 and 124 on the printed ciruit board The Control Logic is timed by a first connection to the Comparator Network 142 for response to the (Reset) waveform (D 16 Q), to cause commutation of the switches 122, 123 and 124 at the commutation instants The Control Logic is controlled for a forward or reverse sequence by two connections to the Forward/Re- verse Logic 149 (U 112 Forward, U 111 Reverse).

The output (PWM) from the Pulse Width Modulator 148 is coupled to the Control Logic to modify the output driving waveforms coupled to the output drivers to permit control of the power applied to the motor windings The least significant bit (BO) is sensed by a connection to the Modulo 6 Counter 144 (D 1 Q) for further use in connection with power control.

The output waveforms of the Control Logic 145 are the six waveforms, AT, AB, BT, BB, CT and CB illustrated at the bottom of Figure 3 These waveforms, whose sequences are reversed through op- eration of the Wall Control 105 or the Forward/Re- verse Switch 51 on the printed circuit board (Fig- ure 2), provide for forward and reverse rotation of the motor Similarly, the lined portions of the out- put waveforms illustrate those periods during which the respective output switches may be sub- jected to a duty cycle control through operation of the wall control or potentiometer R 40 also on the printed circuit board (Figure 2) for adjustment of the motor speed.

The Control Logic 145 consists of a first rank of 3 input NAND gates U 36-U 41 associated with reverse operation of the motor, a second rank of 3 input NAND gates U 42 U 47 associated with forward operation of the motor, a third rank of two input NAND gates U 48 to U 53 acting to multiplex the forward and reverse sequences to the Output Driv- ers 146 The Control Logic is completed by the gates U 13 to U 16, which respond to the least sig- nificant bit and to the pulse width modulation sig- nals in achieving a continuous control of output power.

The logic elements of the Control Logic are con- nected as follows The inputs of the Exclusive NOR gate U 13 are coupled to D 16 Q and D 1 Q as previ- ously noted The output on gate U 13 is coupled through inverter U 14 to one input of the two input NAND gate U 15 and to one input of the two input NAND gate U 16 The other inputs of NAND gates U 15 and U 16 are connected to the pulse width modulator 148 (U 89) The output of NAND gate U 15 is connected to one input of each of the three input NAND gates U 37, U 39 and U 41 in the first rank of NAND gates associated respectively with the AB, BB and CB switching output pads of the IC and to U 42, U 44 and U 46 of the second rank of NAND gates associated respectively with the AT, BT and CT switching output pads of the IC The output of NAND gate U 16 is coupled to one input of the NAND gates U 36, U 38 and U 40 in the first rank of NAND gates associated respectively with the AT, BT, CT switching output pads of the IC, and to one input of the NAND gates U 43, U 45 and U 47 in the second rank of NAND gates associated with the AB, BB, CB switching output pads of the IC.

One input of gate U 36 and one input of gate U 43 are connected to the U 31 output of the Modulo 6 Counter 144 One input of gate U 37 and one input of gate U 42 are connected to U 34 in the Modulo 6 Counter; one input of gate U 38 and one input of gete U 45 are coupled to the output of gate U 35 in the Modulo 6 Counter One input of gate U 39 and one input of gate U 44 are connected to gate U 32 in the Modulo 6 Counter One input of the gate U 40 and one input of gate U 47 are connected to the output of U 33 in the Modulo 6 Counter One input of gate U 41 and one input of gate U 46 are coupled to the output of NAND gate U 30 in the Modulo 6 Counter Finally, one input of the gates of the first rank U 36-U 41 are coupled to the Forward/Reverse Logic (U 1) for reverse operation; and one input of the gates in the second rank U 42-U 47 are cou- pled to the Forward/Reverse Logic (U 112) for for- ward operation The outputs of NAND gates U 36 and U 42 are connected to the inputs of the two in- 28 GB 2 177559 A put NAND gate U 48 The outputs of NAND gate U 37 and U 43 areconnected to the inputs of NAND gate U 49; U 38 and U 44 outputs to the input of U 50; U 39, U 45 outputs to the inputs of U 51; U 40, U 46 outputs to the input of U 52; and the outputs of U 41, U 47 to the input of U 53 The outputs of the NAND gates U 48-U 53, as will be explained, are coupled to the Output Drivers for eventual connec- tion to the separate output pads P 7 (AT), P 8 (AB), P 10 (BT), P 9 (BB), P 11 (CT), P 12 (CB) respectively.

As earlier noted, these are the six waveforms illus- trated at the bottom of Figure 3.

The production of the output waveforms listed above may be explained as follows The Q outputs of the flip-flops D 1, D 2, D 3 forming the memory of the Modulo 6 Counter and illustrated in Figure 3 establish the timing and duration of the Wave- forms C 50, C 51, C 52, etc of the Modulo 6 Counter.

Logical combinations of these waveforms taken two at a time by the gates U 30-U 35 in the Modulo 6 Counter produce waveforms having high por- tions of double count duration corresponding to the high portions of the output waveforms At the separate stages of the three stage motor, this means that in the middle of the energization period for one stage (e g, A), a second stage (e g, B) is being de-energized while a third stage (e g, C) is being energized so that two stages are being ener- gized at all times.

The logical combination of the C 51, C 52 states, which appears at the output of gate U 31 is coupled for forward operation of Switch A to one input of gate U 43, the output of which is coupled via gate U 49, in forming the AB drive waveform, and via output driver BOBA to the Pad P 8 For reverse op- eration of the Switch A, the output of gate U 31 is coupled to one input of gate U 36, whose output is coufled via gate U 48, in forming the AT drive wav- eform, and via output driver TOBA to the Pad P 7.

The logical combination of the C 52, C 53 states, which appears at the output of gate U 32 is coupled for forward operation of Switch B to one input of gate U 44, the output of which is coupled via gate U 50, in forming the BT drive waveform, and via output driver TOBB to the Pad P 10 For reverse op- eration of the Switch B, the output of gate U 32 is coupled to one input of gate U 39, whose output is coupled via gate U 51, in forming the BB drive wav- eform, and via output driver BOBB to the Pad P 9.

The logical combination of the C 53, C 54 states, which appears at the output of gate U 33 is coupled for forward operation of Switch C to one input of gate U 47, the output of which is coupled via gate U 53, in forming the CB drive waveform, and via output driver BOBC to the Pad P 12 For reverse op- eration of the Switch C, the output of gate U 33 is coupled to one input of gate U 40, whose output is coupled via gate U 52, in forming the CT drive wav- eform, and via output driver TOBC to the Pad P 11.

The logical combination of the C 54, C 55 states, which appears at the output of gate U 34 is coupled for forward operation of Switch A to one input of gate U 42, the output of which is coupled via gate U 48, in forming the AT drive waveform, and via output driver TOBA to the Pad P 7 For reverse op- eration of the Switch A, the output of gate U 34 is coupled to one input of gate U 37, whose output is coupled via gate U 49, in forming the AB drive wav- eform, and via output driver BOBA to the Pad P 8.

The logical combination of the C 55, CSO states, which appears at the output of gate U 35 is coupled for forward operation of Switch B to one input of gate U 45, the output of which is coupled via gate U 51, in forming the BB drive waveform, and via output driver BOBB to the Pad P 9 For reverse op- eration of the Switch C, the output of gate U 35 is coupled to one input of gate U 38, whose output is coupled via gate U 50, in forming the BT drive wav- eform, and via output driver TOBB to the Pad P 10.

The logical combination of the CSO, C 51, states, which appears at the output of gate U 30 is coupled for forward operation of Switch C to one input of gate U 46, the output of which is coupled via gate U 52, in forming the CT drive waveform, and via output driver TOBC to the Pad P 11 For reverse op- eration of the Switch C, the output of gate U 30 is coupled to one input of gate U 41, whose output is coupled via gate U 53, in forming the CB drive wav- eform, and via output driver BOBC to the Pad P 12.

As already noted, forward rotation of the motor is provided when the Forward waveform is high and the Reverse waveform is low Since the Forward waveform is high in the lefthand portion of Figure 3, the waveforms of the counter states (CSO, C 51, C 52, etc) and the output switching wave- forms (AT, AB, BT, etc) to the left of the center of the figure illustrate forward operation To the right of the center of the figure, the Forward waveform goes low and the Reverse waveform goes high.

Accordingly, the waveforms of the counter states and output switching waveforms are reversed in sequence Forward operation is provided by means of the gates U 42-U 47 Forward operation is ena- bled with a high due to the Forward waveform coupled to one input of each of the gates U 42-U 47.

When all three inputs of U 42-U 47 are high, at se- lected times in forward operation, the outputs of selected pairs of these gates go low, and assist in forming the forward sequence of the output wave- forms During forward operation, all of the gates U 36-U 41 are quiescent due to a low of the reverse waveform on each of these gates.

Similarly, reverse operation is provided by means of the gates U 36-U 41 Reverse operation is enabled with a high due to the Reverse waveform coupled to one input of each of the gates U 36-U 41.

When all three inputs of the gates U 36-U 41 are high at selected times in reverse operation, the output of selected pairs of these gates go low, and assist in forming the reverse sequence of the out- put waveforms During reverse operation, all of the gates U 42-U 47 are quiescent due to a low from the forward waveform on each of these gates The two input NAND gates U 48-U 53 are enabled for either forward or reverse operation and couple an input to the output drivers from either the active forward or the active reverse gates.

The output switching waveforms AT, AB, BT, etc.

will be virtually as shown in Figure 3 by the solid line high portions in a setting of the manual speed 2 GB 2177559 A 29 controls R 40 and 105 (see Figure 2) in which a maximum of power is applied to the motor wind- ings The amount of power that is applied is varia- ble from a lower limit of no power to an upper limit of full power Full power operation occurs when the two serially connected winding stages are energized 100 % of the time Duty cycling oper- ation in the individual switchin waveforms occurs in those regions defined by a solid line high in the output waveform and a dotted line low For in- stance, the forward AT output switching waveform, has a high coincidental with the C 54 low and the C 55 low The AT waveform has a dotted low for one Reset 1 pulse (equal to the width of the Reset ( 1) pulse) at the beginning of the C 54 low or a dot- ted low delayed one Reset ( 1) pulse at the begin- ning of the C 55 low, continuing to the end of the C 55 low These two periods, as will be shown, are periods during which a 20 K Hz waveform is sub- jected to pulse width modulation, which in one limit is not applied at all for a zero duty cycle and in the other limit loses the periodic component and becomes continuous for the 100 % duty cycle In the customary intermediate values of duty cycle, a square wave is produced having a 20 K Hz repetition rate, and some ON and some OFF time.

The production of the dotted line "lows" in the output switching waveforms, during which duty cycled operation occurs, involves the gates U 13, U 14, U 15 and U 16 The waveform B O (the least sig- nificant bit) from the memory D 1 of the Modulo 6 Counter, is "exclusive NO Red" with the Reset 1 pulse from the Flip-Flop (D 16 Q) of the Comparator.

The Reset 1 waveform (referring to Figure 8), com- mences at the commutation instant, and has a du- ration of about 1/3 of one commutation period in the fastest motor speed setting In the slowest mo- tor speed setting, the Reset 1 pulse has a duration of about 1/30th of one commutation period The "exclusive" NO Ring of the two waveforms pro- duces a high when both waveforms are low and a low when both waveforms are high, and produces a waveform at the output of gate U 13 which is a delayed inversion of the B O waveform -having the same high and low durations, but delayed by the duration of the Reset 1 pulse as shown in Figure 3.

The output of gate U 13 is then coupled to the input of the gate U 16 and through the inverter U 14 to the input of the gate U 15 The duty cycled wave- form (PWM) is also supplied to the inputs of the gates U 15 and U 16 The U 13 waveform is NAN Ded with a PWM output in U 16 and the output of U 16 is applied to the reverse gates (U 36-U 41) Similarly, the U 13 waveform after inversion in U 14 is NAN Ded with a PWM waveform in gate U 15 and the output of gate U 15 is coupled to the input of forward gates U 42-U 47.

Duty cycled operation occurs in the following manner when forward motor rotation is taking place In forward rotation, the Forward waveform is high so that the forward gates U 42-U 47, whicl? produce an active low output when all inputs are high, are enabled Thus, an active low is produced in gates U 42-U 47 during the ON times (highs) of the duty cycled waveform, occuring during the highs of the respective output waveforms from gates U 31-U 35 of the Modulo 6 Counter For exam- ple, during forward motor rotation, the gate U 42 is active in formation of the AT output switching waveform The output waveform from the gate U 34, which corresponds to the AT waveform is high when C 54 and C 55 are low.

If the duty cycle setting is zero, and the output from U 15 stays low, then the AT waveform is low for an initial portion of C 54 equal to the duration of Reset 1 It then becomes high for a commuta- tion period The AT waveform (with U 15 held low) goes low after C 55 has gone low with a time delay equal to the duration of the Reset 1 pulse If the duty cycle setting is for 100 %, and the output from U 15 stays high, then the AT waveform remains high for the duration of C 54 and C 55 If an inter- mediate setting of duty cycle is involved, then the AT waveform as illustrated in Figure 3, is partially ON and partially OFF During the C 54 low switching occurs at the 20 K Hz rate for a period corre- sponding to the length of the Reset 1 pulse The AT waveform then remains high (without duty cycling) for a commutation period, and then returns to duty cycled 20 K Hz switching for the balance of the C 55 low interval It should be noted that the start of the second portion of the duty cycled switching begins after a delay equal to Reset 1 from the beginning of the C 55 low.

The waveforms to the left of Figure 3 illustrate forward rotation of the motor and the output switching waveforms illustrating duty cycled operation The left portion of the drawing is affected by start-up conditions during the low portion of the POR waveform The I start waveform, for this para- graph's discussion, is assumed to be high at all times After POR (low) is completed, the wave- forms assume with their conventional regularity - until the middle of the page is reached At the mid- d Ie of the page, a reversal in rotation is indicated, and waveforms corresponding to a reversal are provided for the righthand portion of the figure.

For forward rotation, assuming that the BB wave- form is first, CT follows, then AB, then BT, CB, AT, BB, CT, etc Two waveforms are always on to- gether, and the duty cycling occurs first (after POR) on the ("B" for bottom) ground connected switch (BB) Duty cycling occurs second on the ("T" for top) VDD connnected switch (CT) Duty cycling oc- curs next on the ground connected switch (AB), next on the VDD connected switch (BT), etc Each successive time, the switch connection alternates between a Vdd and a Vss (ground) connection In addition, at any instant, two highs exist but one is duty cycled and one is not duty cycled While this method of alternation causes a shift in the voltage of the winding neutral, the differential amplifier has very good common mode rejection, and by connecting both ends of the winding stage being measured to the differential inputs of the amplifier, the error produced is negligible The duty cycled sequence, in addition, is adjusted so that as a winding is de-energized the next winding to be en- ergized has a sense to absorb the turn-off tran- sient The Reset 1 pulse is therefore selected to GB 2 177559 A have a duration approximately equal to the dura- tion of this transient or slightly longer The effect is to produce smoother motor operation.

Output drivers 146 The control IC has at its output 6 separate output buffer amplifiers TOBA, BOBA, TOBB, BOBB, TOBC, AND BOBC coupled to the output pads P 7, P 8, P 10, P 9, P 11 and P 12 respectively The letter assignments having a coded meaning The first two letters designate whether switched connection is to be made between the winding stages and B+ or ground potential; "TO" for top means connec- tion to B+ potential, while "BO" for bottom means connection to ground potential The third "B" means buffer amplifier The fourth letter, A, B, or C denotes whether connection is made to the A, B, or C winding stage The output switching wave- forms produced by the buffers (in the order al- ready cited) are respectively at the AT, AB, BT, BB, CT and CB Here, the initial letter designates the winding stage, and the terminal letter determines whether it is designed for load connection to B+ or to ground potential The output switching wave- forms are those shown as the bottom 6 waveforms illustrated in Figure 3 The waveforms with a final "T" indicate that they are to be connected to the base of Q 82 in switch A or its counterpart in switches B or C for connection to B+ potential The waveforms with a final "B" indicate that they are to be connected to the gate of Q 91 in switch A or its counterpart in switch B or C for connection to ground potential The conduction periods that are produced in the top and bottom switches correspond to the highs in the waveforms, with the ver- tical lines indicating duty cycled operation, as earlier explained.

The logical design of the Output Drivers 146 is il- lustrated in Figure 9 The "Top" buffers are each two stage amplifiers consisting of two successive inverters designed to drive the Top portion (Q 82, etc) of the switches A, B and C The "Bottom" buffers, each consist of a two input NAND gate in the first stage followed by an inverter in the sec- ond stage designed to drive the Bottom portion (Q 91) of the switches A, B and C The second input of each NAND gate is connected to the POR 150 for application of the I start waveform The effect of an inhibition of the bottom buffers is to prevent the application of power to the motor, since both a top and bottom switch must be conductive for power to flow to the winding stagel As will be ex- plained in connection with the POR 150, upon starting the motor, power is not applied to the windings until the fifth count (C 55) in operation of the Modulo 6 Counter 144.

Oscillator 147 and pulse width modulator 148 The Oscillator 147 is used for two purposes on the Control IC In the operation of the Autonull Circuit, the Oscillator output controls the counting rate used to decrement the offset current in nulling the Amplifier 141 The Oscillator 147 and the Pulse Width Modulator 148 together enter into the ad- justment of the speed of the fan motor The elec- tronically commutated motor is designed to oper- ate at a speed established by the amount of electri- cal power supplied to the motor When more electrical power is supplied, the motor rotates at a higher rate and when less electrical power is sup- plied, the motor rotates at a lower rate In the pres- ent embodiment, the amount of power supplied to the fan motor is subject to control from approxi- mately 100 % to less than 1 % of maximum power.

This range of power adjustment produces at least a 200:10 rpm speed range The AT, AB, BT, BB, CT, CB waveforms illustrated in Figure 3 depict the mode of application of duty cycled energization to the motor windings The creation of these wave- forms based on the supply of a pulse width modulated waveform from the Pulse Width Modulator 148 has been described in connection with the Control Logic 145 and the Output Drivers 146 The present discussion deals with the Oscillator 147 and the Pulse Width Modulator 148 in the creation of that waveform, a combination which facilitates the wide range of motor speed adjustment sought herein.

The Oscillator 147 is a relaxation oscillator The circuit elements of the Oscillator external to the IC are shown in Figure 2 Those circuit elements on the IC are shown in Figure 10 A It comprises a ca- pacitor C 6, a transistor Q 42 for recurrently dis- charging the capacitor and a resistor R 24 for recurrently charging the capacitor The Oscillator circuit also includes two comparators (COM 4 and COM 5) for setting the limits of the voltage swing of the relaxation oscillator, each comparator being followed by an inverting hysteresis gate, U 87, U 88, a flip-flop comprised of NAND gates U 90, U 91, a reference voltage comprising transistors Q 47, Q 48, Q 49, resistors R 9 and R 10, and a protective net- work including resistor R 11 and diodes D 2 and D 3.

The elements of the Oscillator are interconnected as follows The capacitor C 6, which is external to the integrated circuit, has one terminal connected to pad P 15 and the other terminal connected to the system ground The resistor R 24, which is also ex- ternal to the integrated circuit, is connected be- tween pad P 13 to which the source of Vdd voltage is applied and the pad P 15 The N-channel transis- tor Q 42 has its drain connected to pad P 15 and its source connected to IC ground The drain of tran- sistor Q 42 is also connected via 250 Q resistor R 11 to the positive input of the comparator COM 4 and to the negative input terminal of comparator COM The negative input terminal of the comparator COM 4 is connected to the voltage reference circuit at a point having a normal potential of 1 8 volts.

The positive input terminal of comparator COM 5 is connected to a voltage reference (Vref 5) having a potential of 0 75 volts The output terminal of the comparator COM 4 is connected via the inverting hysteresis gate U 87 to one input terminal (S) of the NAND gate U 90 The output terminal of the com- parator COM 5 is connected via the inverting hys- teresis gate U 88 to one input terminal (R) of the NAND gate U 91 The other input of the NAND gate U 90 is connected to the output of the NAND gate U 91, at which the O output of the Flip-Flop ap- G 1 B 2 177559 A 31 pears The other input of the NAND gate U 91 is connected to the output of the NAND gate U 90 at which the Q output of the Flip-Flop appears The Q output of the Flip-Flop (U 90, U 91) is connected to the gate of Q 42 The output of the oscillator CLK in the form of a rectangular pulse having a short interval duration of approximately 300 nanoseconds and a pulse repetition rate of 20 K Hz is coupled from the output of U 91 to U 93 in the Autonull Cir- cuit for timing the counting rate.

The voltage reference and the remainder of the Oscillator circuit components are interconnected as follows The P-channel transistor Q 47, of 4/8 geom- etry, has its source connected to Vdd, its gate con- nected to IC ground, and its drain connected via 1.6 K resistor R 9, and 1 6 K resistor R 10 to the drain of the N-channel transistor Q 49, bf 50/4 geometry.

The gate and drain of Q 49 are connected together, and the source of Q 49 is connected to IC ground.

The 1 8 volt reference coupled to the negative in- put terminal of COM 4 appears at the drain of Q 49.

Protective diodes D 2 and D 3 are serially connected between Vdd and IC ground, their interconnection being connected to the positive input terminal of COM 4 and the negative input terminal of COM 5.

The Oscillator operates as a relaxation oscillator whose amplitude is defined by the limits set by the voltage references at the comparator inputs Wave- forms useful to understanding oscillator operation are provided in Figure 10 B When first energized, capacitor C 6 begins to charge toward Vdd, the voltage on the capacitor C 6 appearing at the inputs of both comparators When the voltage exceeds PWM "Ref" (+ 1 8 volts), COM 4 sets the Flip-Flop, and the Q output goes high, turning on Q 42, which discharges the capacitor C 6 When the voltage on C 6 falls below Vref 5 (+ 0 75 volts), COM 5 goes high, resetting the Flip-Flop, with Q low and turn- ing off Q 42 Since the discharfe of C 6 is extremely fast (for the values of R 24, C 6 shown), and COM 5 has a finite response time, the voltage on C 6 tends to fall all the way to ground The capacitor C 5 then begins to recharge, and the cycle repeats The out- put waveform (CLK) appearing at the output of U 91 is coupled to U 93 of the Autonull circuit The wav- eform appearing at the capacitor C 6 is the saw- tooth waveform in the upper part of Figure 10 B. The CLK waveform is the rectangular pulse super- imposed on the sawtooth waveform The duty cycle, as earlier noted, for the clock waveform is < 1 %, using the indicated parameters The selection of the parameters is designed to create a relatively linear sawtooth waveform on the capacitor C 5.

The Pulse Width Modulator 148 utilizes the saw- tooth capacitor waveform and provides an output waveform (i e, PWM output), which is selectively either always off; on some off some; or always on.

The ratio of on-to-off time (i e Pulse Width) is con- trolled by the setting of the external potentiometer R 40 or the wall speed control 105 These three possibilities are described in Figure 10 B. The Pulse Width Modulator comprises the exter- nal potentiometer R 40, external transistor Q 81, ex- ternal resistances R 25, R 26, R 27, R 29, R 30 and external capacitor C 4 associated with "Regulate" pad P 14 and the comparator COM 6, and hyster- esis gate U 89 on the IC The 100 K ohm potentiom- eter R 40 has its end terminals connected between Vdd (pad P 13) and the system and IC ground (pad P 6) Te tap on the potentiometer R 40 is connected via the 150 K resistor to the pad P 14 The 2 21 Lf ca- pacitor C 4 and the 39 K resistor are connected be- tween the pad P 14 and system ground PNP transistor Q 81 has its collector coupled to pad P 14, its base connected to the tap on a voltage division network comprising 430 K resistor R 26 connected to the 150 volt supply and 36 K resistor R 27 connected to system ground, and its emitter connected via 36 K resistor R 25 to Vdd The principal collector load is the 39 K resistor R 30 connected between the collector of Q 81 and system ground.

On the IC, the comparator COM 6 has its nega- tive input terminal coupled to the pad P 14, and its positive input terminal coupled via the resistance R 1 1 to the capacitor C 6 The output of the compar- ator COM 6 is coupled to the inverting hysteresis gate U 89 at the output of which the PWM output appears.

The limits and an intermediateiform of the PWM output wave are illustrated in Figure 10 B The duty cycle is affected by both potentiometer R 40 and the wall control 105 When the potentiometer R 40 is set very low, the negative input of the compara- tor is always below the voltage on the capacitor C 6, and the COM 6 output is high The PWM out- put derived from U 99 is always low When R 40 is set very hjgh, the comparator output is always low, and the PWM output is always high When R 40 is set at an intermediate position between the limits of the oscillation voltage appearing across the ca- pacitor, the PWM output waveform is high part of the time and low part of the time Since the capaci- tor voltage is controlled to rise and fall substan- tially linearly, the practical linear adjustment range of the duty cycle is very close to the 0 to 100 % absolute limits.

Figure 10 C, which also applies the Forward/Re- verse Logic, illustrates how the duty cycle is af- fected by the wall control 105 When the wall control is used, the maximum B+ voltage is lim- ited to about 135 V Downward adjustment of the motor potentiometer in the wall control reduces the B+ (+ 135 V) applied to the motor Initial down- ward adjustment of the control brings about a re- duction in speed by a reduction in the voltage applied to the motor After the voltage has been reduced from a nominal value of 150 volts to ap- proximately 100 volts, further downward adjustment of the wall potentiometer brings about simultaneous downward adjustment of the B+ and the imposition of a pulse format upon the output waveform, whose duty cycle is gradually de- creased This is illustrated in Figure 10 C The duty cycle is controllable by this control from 100 % to nearly 0 % as indicated in relation to the adjust- ment of R 40.

The operation of the wall control 105 involves the components earlier named connected to the Regulate pad P 14 These include the transistor Q 81 and resistors R 25, R 26, R 27, R 29, R 30 and R 40 Op- 32 GB 2177559 A eration of the wall control adjusts the average volt- age applied to the motor The maximum voltage (e.g 135 volts) produces the maximum speed Decreasing the average voltage by means of the wall control produces a substantially linear reduction in voltage applied to the motor as indicated by the upper solid line (When this reduction begins, let us assume that R 40 is set at the maximum value) At the maximum value, Q 81 is biased off by an ap- proximately 1 4 volts different between its emitter voltage, which is defined by the Zener diode CR 1 at 9 volts above ground, and the base voltage, which is defined at about 10 4 volts by the voltage divider formed by R 26 and R 27 connected between the 135 V B+ terminal and ground As the B+ po- tential is adjusted down, the voltage on the emitter connected to the Zener diode remains constant, while the voltage on the base connected to the voltage divider falls in proportion to the reduction in B+ potential At about 110 V B+, the reverse bias on Q 81 is removed, and adequate forward bias provided to overcome the junction drop, and initi- ate conduction To this point, in the downward adjustment of the potential, the voltage on the Regulate pad P 14 has been unaffected, and has re- mained at zero potential Beyond this point, conduction by transistor Q 81 between Vdd and the Regulate pad causes the voltage on the pad to in- crease Any slight increase in voltage raises the threshold of U 89, and causes a decrease in the Pulse Width The joint reduction in absolute B+ voltage and in the duty cycle produces an increased rate of decrease in average voltage At about 60 volts, a minimum rotation rate (just above the stalling speed of the motor) is achieved and the PWM duty cycle is near zero For a REG voltage equal to about 2 2 volts, the PWM duty cycle and speed are both zero At this point any further decrease in voltage provides no further de- crease in speed of the motor, but rather a further elevation of the voltage of the Regulate pad This last range of adjustment permits the voltage in- crease on the Regulate pad to signal a reversal in rotation by tripping a comparator set at 2 4 volts, as will be described in connection with the Forward/Reverse Logic 149.

Control of the rate of rotation of the fan motor is achieved by a combination of an initial reduction in the B+ voltage supplied to the fan motor followed by the utilization of a pulse width modulated form of energization in which further reduction of the B+ supply is accompanied by a progressive nar- rowing of the energizing pulses of fixed repetition rate As the voltage is further reduced, a minimum point is reached at which there is essentially no "on" time for the pulses and the energization is es- sentially cut off The practical range of speed adjustment exceeds 200:20 rpms.

To get a 10:1 speed control range using a varia- tion of B+ supply voltage only would require a 10:1 range of voltage This is difficult to do andstill use a single zener diode power supply to power the IC from the B+ supply By proportion- ately reducing pulse width with B+ voltage reduction, a 10:1 speed range can be obtained with only a 2 to 3:1 variation in B+ The B+ supply voltage variation is used in order to control motor speed with the wall control If a wall control is not used, the full speed range can be obtained using PWM only.

Achieving this range of control requires a system capable of stable operation at both the upper and lower limits of operation This has been achieved by the avoidance of a pulse by pulse feedback loop for current control, and the use of a higher PWM rate The present arrangement, which uses an open loop pulse width modulation configuration is particularly advantageous when it is desired to achieve the present wide range of control Open loop operation is characterized in a block diagram in Figure 10 E The applicable waveform is the AT waveform of Figure 10 F, also illustrated with less detail in Figure 3.

In the Figure 10 E illustration, the motor speed is set by an energy balance between a mechanical load imposed on the ECM motor 206 primarily by the fan 207 and the electrical energy supplied to the motor and determined by the operator The block diagram illustrates a manually adjusted po- tentiometer 203 whose end terminals are con- nected between Vdd and ground and whose tap is connected to the negative input terminal of com- parator 202 The positive input terminal of the comparator 202 is coupled to the output of a source of sawtooth waveforms 201 The comparator 202 output is coupled to Electronic Gating 205.

Power is supplied to the Electronic Gating 205 from the dc power source 204 Power is derived from Electronic Gating by three separate connections (A, B, C) to the three winding stages of the ECM 206 The output of the comparator, depending upon the setting of 203 produces an output waveform which is a sustained logical "one", a pulsed logical " 1 " having a fixed 20 K Hz repetition rate whose duration is determined by the setting of 203 or finally, a sustained logical "zero".

The intermediate case is illustrated in Figure 10 E.

The Electronic Gating 205 is primarily the Control Logic 145 whose function is to provide gating in response to the pulse width modulation which ap- pears at U 89 and in response to the output of the Modulo 6 Counter which defines the double com- mutation periods for energizing the separate wind- ing stages The setting of the input of the comparator is determined by the operator when he sets the voltage at 203 This arrangement provides a full range of control and does so with the required stability at both the upper and lower limits.

While lacking the drift stability of a closed loop feedback system, the open loop system has the ad- vantage of simplicity, and any slight drift which might occur is not ordinarily objectionable.

The objective of open loop PWM (pulse width modulation) operation is to avoid anomalies due to time delay which occur in closed loop PWM sys- tems Specifically, in feedback PWM systems the system is turned on and then turned off at a later time by some motor related parameter such as current or voltage There is a minimum pulse width that can be thus generated which corre- 3 GB 2177559 A 33 sponds to the total time delay of the system including the turn-off delay of the power transistors.

If an attempt is made to generate a PWM pulse which is shorter than the system time delay, the system will either jump to zero from some finite value or it will duty cycle back and forth between zero and this minimum finite value, in a bang-bang way, trying to achieve the "forbidden" setting by averaging over many pulses some of which are too large and the others of which are zero.

The avoidance of these anomalies sets require- ments upon the manner of adjusting the variable level and the mode of generation of the periodic waveform, the two being illustrated as the inputs to the comparator 202 of Figure 10 E Requirements are also placed upon the relationship of one to the other.

In the disclosed embodiment, the user of the fan may look at the fan, determine whether it is going at the desired speed and make an upward or downward adjustment The adjustment, once made is essentially independent of what hpppens to the motor and the power circuit, and when the user has moved away from the control and is no longer regulating by hand and by eye, this operation is also open loop.

The control 203 need not be manually adjusted in the manner just described, however The ad- justed level may be part of a power sensing, cur- rent sensing, cooling sensing, etc feedback system in which average levels of slowly varying parame- ters such as average currents, average tempera- tures, etc may be used It is thus possible to have an open loop modulator used in a closed loop mo- tor system.

The adjustable level in the PWM input must meet two criteria It should not be instantaneously responsive to motor circuit parameters nor have any frequency components comparable to that of the repetitive wave such as would disturb the dis- tance between intercepts used to define the active state of the comparator output and thus the duty cycle of the PWM waveform Re-phrased, the ad- justable wave should not have any components whose rate of change is comparable to the rate of change of the repetitive waveform.

Another requirement is that the repetitive wave- form should be independent of the motor in a strict sense in that in both the short term and in e 50 the long term there is no relationship between them In the actual embodiment, the oscillator is powered from the same DC supply as the motor but the supply is controlled by a Zener voltage reg- ulator and DC levels as well as short time current instabilities are precluded from affecting the oscil- lator frequency, amplitude, or waveform If these conditions are maintained, then the motor speed is adjusted throughout essentially all of its range without any unevenness in the motor speed func- tion.

The present arrangement achieves a large range of speed adjustment with quiet operation The con- tinuous control range is from approximately 0 % to % duty cycle adjustment corresponding to a rate of rotation of approximately 10 rpms to ap- proximately 200 rpms maximum At near zero duty cycle, the power switches do not fully turn on and operate in an analog fashion down to 0 duty cycle.

The pulse to pulse feedback systems on the other hand are usually restricted to 5 % to 95 % duty cycle adjustment because of limitations in the delay times of available low cost semiconductor switches and the delay times in the signal logic itself.

Economics normally dictates that the repetition rate of the pulses be in excess of the audible limits ( 20 K Hz) but not so significantly above audible lim- its as to require high cost, high frequency transis- tor switches An economically practical limit is approximately 30 K Hz.

In practical circuits using NPN devices, the saw- tooth waveform has a very accurate positive peak and a not too accurate lower peak This is because the positive peak is associated with the turn on of a device while the negative peak is associated with the turn off of the device For this reason the 0 % modulation is associated with the positive peak which occurs at approximately 2 volts and the % modulation is associated with the negative peak which occurs at ground, since smooth modu- lation of 0 % is more critical The turn-on time al- ways embraces the positive peak, the turn-off time the negative.

The forward/reverse logic 149 The Forward/Reverse or direction control Logic is responsive to the setting of the forward/reverse switch 51 coupled to the pad P 16 on the IC, and to a controlled diminution in the B+ supply, effected by the wall motor speed control An inversion in the logic state of the output of 149 causes an in- version in the counting sequence and a reversal in the sense of rotation of the motor.

The direction control Logic 149 comprises the transistor Q 48, the comparator COM 7, hysteresis gate U 113, the flip-flops D 13, D 14, D 15, exclusive OR gates U 107, U 110, and NOR gates U 111 and U 112 External to the IC, the transistor Q 81; resis- tors R 25, R 26, R 27, R 29 and R 30 (mentioned in connection to PWM 148); and the switch 51 enter into forward/reverse operation.

The comparator COM 7, which is the heart of the control, has its positive input terminal coupled to the "REG" pad P 14 and its negative input terminal coupled to an internal reference (Vref 9) at 2 4 volts The potential at pad P 14, while affected by the setting on potentiometer R 40, will not change the state of COM 7 The state of COM 7 may be changed only by adjustment of control 105, which affects the state of conduction of Q 81, as earlier described.

The negative input terminal of COM 7 is con- nected to a voltage reference to which hysteresis is added at the moment that switching takes place.

The input connection is made to the drain of the P- channel transistor Q 47, which is never less than 1 8 volts irrespective of reductions in B+ The drain of Q 47 is connected via serially connected resistances R 9, R 10 and transistor Q 49 (with interconnected gates and drain) to ground The PWM reference voltage of 1 8 V appearing across Q 49 is used as 34 GB 2 177559 A the reference to set the maximum amplitude of the sawtooth waveform By adding the voltage drops across R 9 and R 10 to this level ( 1 8 V) and coupling the resulting voltage to the negative input terminal of COM 7, the trip point for COM 7 is set in a man- ner which assures that reverse always occurs be- low zero speed One of the two outputs taken from COM 7 is connected via an inverting hysteresis gate U 113 to the C input of the flip-flop D 15 The other output of COM 7 is connected to the gate of N-channel transistor Q 48 of 500/4 geometry, whose drain and source are connected to shunt resistance R 9 When Q 48 becomes conductive as the COM 7 output goes high upon sensing an increase in volt- age at P 14 in excess of the Vref 9, it reduces the voltage on Vref 9 by approximately one quarter volt This introduces hysteresis which makes the reversal more positive acting, assuring that only a single reversal occurs every time VREG exceeds Vref 9.

The reduction in B+ is coupled to the forward/ reverse circuit in the following manner When the B+ voltage is reduced by wall control 105 to a point where Q 81 becomes conductive, the voltage on the Regulate pad P 14 monotonically increases as shown in Figure 10 C (It is assumed that R 40 is set at a maximum clockwise position when the wall control 105 is used) Adjustment of wall con- trol 105 over the normal range of PWM control leads to a final value of 1 8 volts Adjustment past 1.8 volts produces a voltage peak in excess of 2 4 volts The comparator COM 7 is set to trip the For- ward/Reverse Logic at about 2 4 volts.

The setting of R 40 does not interfere with the re- versal achieved by control 105 and will not itself produce a reversal in motor rotation So long as Q 81 is nonconductive, the voltage on the Regulate pad P 14 is determined by the setting of the poten- tiometer R 40 and resistors R 29 and R 30 With Q 81 nonconductive, the configuration sets a maximum voltage on the Regulate pad P 14 of approximately 2.2 volts, when the tap on R 40 is at Vdd (and no reversal will occur) The 2 2 volts is used to assure that minimum speed is reached even under worst case conditions The minimum value of zero volts occurs when the tap on R 40 is at ground When transistor Q 81 becomes conductive by a suitable fall in B+ voltage with adjustment of 105, the volt- age on the Regulate pad P 14 will increase toward Vdd as shown in Figure 10 C The setting of R 40, which is isolated by the 150 K ohms of R 29, has only a slight affect on the Figure 10 C characteristic.

In normal operation, the operator, when it is de- cided to reverse the fan motor rotation, reduces the manual control to its lowest speed setting, which first reduces the speed to a minimum value (stalling), and then continues past that setting to a value which trips the reversing comparator COM 7.

Since the setting is too low for use, the operator returns the setting forward to the desired speed of rotation In this manner, the speed characteristic il- lustrated in Figure 10 C is reproduced in the course of either a speed increase or a speed decrease.

The output of U 113 is connected to the C input of flip-flop D 15 The R input of D 15 is connected to the POR 150 (U 120) The Q output of D 15 is con- nected to the D input of D 15, and the D 15 Q output is connected to one input of the exclusive OR gate U 107 The other input of the gate 107 is connected to pad P 16 for application via single pole, double throw switch 51 to either Vdd or system ground potential Switch 51 provides the permanent mem- ory for motor direction, and determines the direc- tion of rotation when power is first applied.

The output of the exclusive OR gate U 107 is con- nected to the D input of flip-flop D 13, which to- gether with flip-flop D 14, provides at least one clock pulse of delay before a reversal can occur.

The Q output of D 13 is connected to the D input of flip-flop D 14 The CLK signal is connected to the C inputs of D 13, D 14 The exclusive OR gate U 110 has one input connected to the output of U 107 and one input connected to the Q output of D 14, from which is coupled an input of U 116 (in POR 150).

The Q output of D 14 is coupled to an input of U 115 (in POR 150) NOR gate U 111 has one input con- nected to the output of exclusive OR gate U 110, and one input connected to D 14 O NOR gate U 112 has one input connected to the output of exclusive OR gate U 110 and one input coupled to D 14 Q The output of U 112, at which the Forward waveform appears, is coupled to gate U 12 in the Modulo 6 Counter and after two successive inversions in U 12, U 7 is coupled uninverted to the gates of U 42- U 47 of the Control Logic The output of NOR gate U 1 i 1, at which the Reverse waveform appears is coupled to the gates U 36-U 41 in the Control Logic.

The output state of the Forward/Reverse Logic is defined by the state of D 15, which is in turn de- pendent on the state of COM 7 and on the setting of switch 51 connected to pad P 16 When the in- stallation is first turned on, D 15 is reset (Q low) by the POR If P 16 is connected to ground by 51 (a logical low), then with two lows at the input of U 107, a low is produced at the U 107 output This produces one low immediately at the input to ex- clusive OR gate U 110 Meanwhile, after a 1 to 2 clock pulse delay, D 13 Q and D 14 Q have gone low With two lows at the input to U 110, the U 110 output goes low This causes U 112 (forward) to go low, and U 111 (reverse) with inputs which are con- nected to D 13 Q and U 110 (both low), to go high, and reverse operation to occur.

If switch 51 is set high, D 15 Q being low, then the exclusive OR gate U 107 output goes high, and a high is propagated directly and indirectly via D 13 Q, D 14 Q to exclusive OR gate U 110 The output of gate U 110 goes low after a delay of at least one clock pulse, and NOR gate U 112, with lows at both inputs, goes high for forward operation.

The delayed operation of at least one pulse is achieved by the insertion of D 13 and D 14 in the signal path in parallel with the U 107 output; and the application of the delayed and undelayed sig- nal to the exclusive OR U 110 The exclusive OR produces no high unless both inputs are different.

Thus, it acts to defer the transmission of a high to the output gate U 110 until the delayed and unde- layed waveforms have reached the gate U 110 out- put The logical use of the Q and G outputs of the - GB 2 177559 A 35 flip-flops allows the delay to occur with both a change to reverse or a fhange to forward rotation.

The direction control logic 149 produces output signals at U 11 and U 112 for control of the direc- tion (clockwise/counter clockwise; or Forward/Re- verse) of motor rotation The absence of an active output signal from U 1 or U 112 inhibits any input to the winding stages The active outputs (highs) for U 111 (Reverse) and U 112 (Forward) never coexist, and an interruption occurs for long enough to protect the solid state switches 122-4 after one ac- tive state is terminated, before the other active state starts.

The Forward and Reverse waveforms have been illustrated in the waveforms of Figure 3 and as- sume a logical high or low The connections of the output of the Forward/Reverse Logic 149 are made to the Commutation Counter for inverting the count sequence within the counter (U 8, U 9, U 20, U 21), as earlier described, and to the Control Logic for selecting the forward (U 42-U 47) or reverse (U 36-U 41) "decoders" for achieving the correct switching sequence in the output drivers 146.

Power on reset 150 The Power on Reset or Protection Circuit 150 senses Vdd as it increases after power is first turned on (i e "Power On") and holds certain por- tions of the logic in an initial state (i e "Reset") until the appearance of sufficient Vdd voltage gives assurance that the logic is valid It performs a simi- lar function after power is turned off When power is turned on, it also dictates the initial operation, which is nulling of the Amplifier 141 before it is used for integration timing.

In addition, the POR 150 precludes the applica- tion of power to the motor windings until other portions of the control IC have been properly initialized and are ready to perform the normal con- trol functions The present POR circuit performs its function with the addition of an external pad, and does not require the provision of an additional ca- pacitor.

The analog and digital portions of the POR Cir- cuit 150 are illustrated in Figure 11 A The input voltages to the comparator (COM 8 of the POR), il- lustrating the operation of the POR in response to increasing Vdd upon turn on, are illustrated in Fig- ure 11 B The waveforms derived from the POR 150 are shown in Figures 3, 12 A and 12 B. The Power On Reset 150 maintains an initial re- set condition by means of the POR waveform responsive to the instantaneous value of the Vdd voltage The POR waveform becomes inactive when the Vdd voltage exceeds the desired thresh- old (i e 7 volts) The POR waveform is coupled to the Set inputs of the flip-flops D 16, D 17 of the Comparator Network 142; to the Reset inputs of the flip-flops D 1, D 2 and D 3 (assuring a 000 initial state) in the Commutation Counter; and to the Re- set input of D 15 of the Forward/Reverse Logic 149, assuring a return to the state (Forward or Reverse) established by the position of 51 The D 17 Q output is coupled via U 92 to D 7, and D 7 Q opens gate U 85, disconnecting the Amplifier 141 from capacitor C 5.

When the Amplifier is reconnected after nulling, a significant ( 6 lLA) current (IST) is injected into (R 4 A- D) of the Integrating Amplifier in a sense to cause a discharge of capacitor C 5, via gate U 85, below the comparator COM 2 threshold ( 3 volts) This current, which is interrupted during each of four subsequent nullings, prevents the Amplifier from "hanging'up" in a Vdd saturated state upon turn on, but is not so great as to interfere with the reset of the capacitor C 5.

The Vdd sensing portion of the POR Circuit 150 comprises the transistors Q 52-Q 59, the comparator COM 8 and the non-inverting hysteresis gate U 120.

The positive terminal of the comparator is con- nected to a first series circuit comprising diode D 1 and N-channel transistors Q 58 and Q 59 The nega- tive terminal of the comparator COM 8 is con- nected to a second series circuit comprising the P- channel transistors Q 52-Q 57.

In the first series circuit, the anode of D 1 is con- nected to the source of Vdd potentials and the cathode is connected to the gate and drain of Nchannel transistor Q 58 of 500/4 geometry The source and body of Q 58 are connected together and to the drain of N-channel transistor Q 59 of 4/ geometry These three connections are inter- connected to the positive input terminal of the comparator COM 8 The source of Q 59 is con- nected to the IC ground The gate of Q 59 is con- nected to the Vdd source The foregoing connections apply a potential to the positive input terminal of comparator COM 8 which is equal to the instantaneous Vdd voltage less a constant, which is equal to the voltage drop in diode D 1 and drop in Q 58 This is approximately 1 4 volts.

The negative input terminal of comparator COM 8 is connected to a second series circuit in which the slope is a fixed fraction (K< 1) of the Vdd volt- age and which is provided with hysteresis to in- sure positive operation of the POR In particular, P- channel transistor Q 52 of 10/6 geometry has its drain connected to the source of transistor Q 54 Pchannel transistor 054 of 100/4 geometry has its drain connected to the source of Q 55 P-channel transistor Q 55 of 25/4 geometry has its gate and drain joined, and the two electrodes are connected to the source of Q 56 P-channel transistor Q 56 of 25/4 geometry has its gate and drain joined, and the two electrodes are connected to the source of Q 57 P-channel transistor Q 57 of 25/4 geometry has its gate and drain connected to IC ground The P- channel transistor Q 53 of 20/6 geometry has its source connected to Vdd The gate and drain of Q 53 are joined and connected to the gate of Q 52, to the drain of Q 54 and to the negative input terminal of COM 8 The output terminal of COM 8 is connected to the gate of Q 54 for effecting hyster- esis.

The output terminal of comparator COM 8 is connected to the input terminal of the non-invert- ing hysteresis gate U 120 The POR output wave- form is derived from the output of U 120.

Upon energization, the output of comparator COM 8 arrives at a logical "low" value once Vdd is in excess of several volts and so remains until the 36 GB 2 177559 A trip point occurs (at a Vdd of about 7 volts).

As shown in Figure 11 B, the trip point of the comparator COM 8 occurs when the voltages at its positive and negative inputs intersect At this point, the POR waveform goes to an inactive high The voltage of this intersection is designed to be at a level which allows the logic in the digital circuitry of the IC to become valid and the analog circuitry, particularly that involved in nulling, to become functional This voltage is set at approximately 7 volts for an upward change in Vdd and 6 5 volts for a downward change in Vdd as a result of the provision for hysteresis.

The foregoing trip point is determined by two in- dependent variables characterizing the series cir- cuits associated with the positive and negative input terminals, respectively, of the comparator COM 8 The first is the voltage offset provided by the diode D 1 and Q 58 in the first series circuit at the positive input terminal of the comparator, it being assumed that the slope of the resulting input voltage is unitary as a function of Vdd The second independent variable is the voltage division ratio of the second series circuit, which is coupled to the negative input terminal of the comparator COM 8 and which is assumed to act as a simple resistive voltage divider The fraction K has a value of 0 8 for an intercept at about 7 volts These values are approximate and appreciable latitude is to be ex- pected.

Hysteresis is provided by the output connection of the COM 8 to the gate of Q 54 If the output of COM 8 is low, Q 54 is conductive and, similarly, Q 52 in series with it is conductive Thus, current is provided to the transistors Q 55, Q 56 and Q 57 via both transistors Q 52 and Q 54 in one path and Q 53 in the other path When the output of COM 8 goes high, then Q 54 and Q 52 are disabled to conduct current in parallel with Q 53, and the voltage at the negative input to COM 8 falls from 5 53 to 5 41, or millivolts, implying a lower conductance The change in the Vdd threshold is approximately 1/2 volt and insures a positive switchover.

The output circuitry of the POR circuit 150 re- sponds to both the state of the Vdd as sensed at the comparator COM 8 and to the state of the other circuits on the IC which are caused to go through a preliminary series of simulated commu- tations by the POR The output circuitry of the POR consists of the SR flip-flop U 118, U 119, the NOR gate U 86, the three NOR gates U 15, U 116, U 117 and the transistors 069 and 59 The five commuta- tion count duration of the IST and I start POR wav- eforms is derived from a connection of U 115, U 116 to U 25, U 29 of the Commutation Counter 144 The connection of U 118, U 119 to U 86, and U 86 to D 7 Q of the Autonull Circuit 193 causes the Ist waveform to be delayed until after the first nulling, and inter- rupted for the next four nullings The circuit is as follows.

The SR flip-flop consists of two, two terminal NAND gates U 118 and U 119 with the R input being responsive to the Modulo 6 Counter and to the Forward/Reverse Logic, and the S input being re- sponsive to the state of the Vdd (COM 8, U 120).

The outputs of the two NOR gates U 15 and U 116 are connected to the input of the two input NOR gate U 117 One input of the two input NOR gate U 15 is connected to the C 55 output of the Modulo 6 Counter and the other input of U 115 to con- nected to the D 14 Q of the Forward/Reverse Logic.

One input of the two input terminal NOR gate U 116 is connected to the Modulo 6 Counter for ap- plication of the C 51 waveform The other input of U 116 is connected to the D 14 Q output of the For- ward/Reverse Logic The two outputs of NOR gates U 1 15 and U 116 are connected to the two respective inputs of NOR gate U 117 The output of U 117 is connected to the R input of the flip-flop The set (S)input of the flip-flop at the input of U 119 is con- nected to the output of hysteresis gate U 120.

The NAND gates U 118 and U 119 have cross-cou- pled outputs, one (Q) of which is connected to one input of U 86, and to the Output Drivers 146 The Q output of the flip-flop appearing at the output of_ U 119 is coupled to the other input of U 118 The Q output of the flip-flop appearing at the output of U 118 is connected to the other input of U 119 The Q of the flip-flop is then connected to one input of the two input NOR gate U 86 The other input of U 86 is connected to D 7 Q in the Autonull Circuit 142 for application of the Null Output waveform.

* The output of NOR gate U 86 is coupled to the gate of N-channel transistor 59 whose source is con- nected to the resistance R 4 A-D in the Autonull Cir- cuit The drain of 59 is connected to the drain of P- channel transistor Q 69 whose source is connected to Vdd and whose gate is connected to Vref 8 in the Autonull Circuit.

Conduction of switch 59 allow Ns a 6 p A current to flow from current source Q 69 to R 4 A-D Transistor Q 69 is a P-channel transistor of 45/12 geometry, which has its source connected to Vdd and its drain connected to the drain of transistor switch 59 Transistor switch 59, an N-channel device of 45/4 geometry, has its source connected to the up- per terminal of R 4 A-D for return to IC ground The gate of 59 is connected to the output of U 86 The gate of Q 69 is connected to the voltage reference Vref 8 in the Autonull Circuit, which is adjusted to supply a 6 lLA (IST) current to the resistance R 4 A-D in the Autonull Circuit The current (IST) causes a negative output current of the same amount to oc- cur in the output of the Integrating Amplifier and insures the discharge of the capacitor C 5, should there be a tendency of the Amplifier 141 to hang up at a positive saturation during this start-up pe- riod.

The overall Power On Reset process takes place in the following manner The waveforms of great- est relevance are those provided in Figure 12 B The output of the comparator COM 8 is assumed to be low immediately (and active as soon as any other protected circuitry) upon turn-on of the power The output of U 120 whoseinput is coupled to COM 8, remains low and the POR waveform is in its active low state holding the Comparator Network 142, the Modulo 6 Counter 144, and the Forward/Reverse Logic 149 in theappropriate initial state More par- ticularly, the flip-flops D 16 and D 17 of the Compar- GB 2 177559 A 37 ator Network 142 are set (Q high) providing a "false" commutation signal causing the Reset wav- eform and the Null Clock waveform to be high The flip-flops D 1, D 2, D 3 of the Modulo 6 Counter 144 are reset to the 000 state (Qs low) and the flip-flop D 15 of the Forward/Reverse Logic 149 and returned to a state corresponding to the setting of the for- ward/reverse switch 51.

A further consequence of a valid low at the out- put of the comparator COM 8 is that the Output Drivers 146 are disabled immediately after turn-on.

This condition assumes that the S input of Ul 19 is low, the flip-flop (U 118, U 119) is "set" (Q output low) The Q low output of the flip-flop applies a low to the bottom output drivers BOBA, BOBB and BOBC in 146, precluding energization of the motor winding stages These drivers remain disabled so long as the flip-flop (U 118, U 119) is set.

A further consequence of a low at the output of COM 8 is that a negative offset current lST is sup- plied to R 4 A-D in the Autonull Circuit, which is in- tended to facilitate the Integrating Amplifier's discharge of C 5 below the 3 volt threshold of com- parator COM 2 when it is connected by U 85 to re- set and charge capacitor C 5 The Q low output of the threshold of flip-flop (U 118, U 119) is also cou- pled to one input of the NOR gate U 86, which has a high due to the Null Output waveform on the other input The output of U 86 is therefore low, causing transistor switch 59 to remain off until the initial Autonull (and next four) periods are over.

The Autonull period is defined to be the interval between the moment when the Null Clock wave- form goes high (at power on) and when the Null Output waveform goes low.

During the continuation of the active low of POR waveform, the states indicated above are main- tained In addition, the capacitor C 5, which influ- ences the state of the comparators COM 1, COM 2 and COM 3, is normally discharged at the start of energization, and is not likely to significantly charge for the duration of the active low of the POR waveform During this time the capacitor C 5 is disconnected from the amplifier output since U 85 is open because the Null Output waveform is high.

As soon as Vdd exceeds 4 or 5 volts and the Am- plifier is active, its output will swing to the positive saturation limit since the Autonull Circuit is now supplying it maximum positive offset current ( 15 T is off) This will cause Nuilset to go low and re- main low until after POR goes high and a null is detected.

When the POR waveform goes to an inactive high, the forced sets and resets are removed and the Modulo 6 Counter and Autonull Circuits are free to function in a more conventional repeating manner for the next four periods.

After the initial Autonull period has concluded (Null Out low), 59 turns on supplying current IST to R 4 A-D In respect to the Modulo 6 Counterthe C 55 waveform is NOR'd (U 115) with the D 14 Q output from the Forward/Reverse Logic, which is higb in the reverse direction, disabling U 115 The C 51 waveform is NOR'd (U 116) with the D 14 Q output If the Forward/Reverse Logic is operating in a forward sense, then D 14 Q is high, disabling U 116 If the Forward/Reverse Logic is operating in a reverse sense, then D 14 Q is high, 115 is dis- abled and U 116 is enabled Initially CSO is active and C 55 goes high This is true for five counts, un- til C 55 goes low When C 55 goes low, the output of U 115 goes high, forcing the output of U 117 low, resetting the flip-flop U 118, U 119, turning off the current IST.

The addition of IST assures that the amplifier off- set current remains negative during the time be- fore Vdd has stabilized The similar POR output waveform I start, which lasts for a five commuta- tion count duration, but is not interrupted during nulling, is coupled to prevent the application of power to the motor until five commutations have occurred.

The protection circuit gives the Autonull circuit five counts to stabilize, and insures adequate (neg- ative) integration current to discharge the timing capacitor C 5 should the Amplifier drift toward saturation in this interval.

The protection circuit acts on behalf of the con- trol circuit, and the power switches and, as earlier noted, operates both during power up and power down.

Upon turn on (POR active) the Amplifier 141 is disconnected from the integrating capacitor C 5, due to the high on D 7 Q Nulling of the Amplifier is initiated when the POR goes to an inactive state.

After nulling, the Amplifier is connected for the first time to C 5 The circuit thus insures that nulling will occur as the POR goes inactive and that the Amplifier will not be allowed to affect the timing until it is nulled.

Th invention has been used primarily with available neutral connections from the winding stages of the motor The available neutral connec- tion is not mandatory, however, and a synthetic neutral may be used instead In general, the re- quirements of the synthetic neutral are that switch- ing takes place in accordance with winding stage energization sequences, and that a resistance or reactance matrix be substituted for the actual windings The synthetic neutral should not degrade the system and must respond at the same level of accuracy as other elements of the system.

The motor control circuit herein described in uti- lizing a periodically balanced transconductance amplifier responding to the back emf of an unener- gized winding stage for commutation timing of an ECM need not be restricted to the illustrative ex- ample The invention need not be restricted to var- iable speed designs nor to the lower speed ranges characteristic of ceiling fan operation The nulling can be accomplished at higher clocking rates within shorter times to fulfill rpm requirements.

The transconductance amplifier with intensive distributed degeneration and self-balancing, is well suited to a maximally integrated motor control cir- cuit, in that it places a minimum requirement upon external components and upon external precision resistors, and has an extremely low power dissipa- tion The power dissipation on the IC is typically 18 milliwatts and on the control circuit is typically 38 GB 2 177559 A from 0 3 to 1 watt The resulting motor control cir- cuit thus represents a significant improvement in performance over non-integrated prior art electronic commutation circuits and does so with a sig- nificant decrease in cost.

Claims (1)

1 In a motor speed control circuit for an elec- tronically commutated motor adapted to be ener- gized from a DC power source, said motor having a multistage winding assembly and a magnetic as- sembly, the two arranged for mututi relative rota- tion upon application of a multi-stage energization sequence, the combination comprising:

power input terminals for connection to a supply suitable for motor operation; a waveform generator for supplying a repetitive low voltage waveform of substantially constant repetition rate, amplitude and configuration, said characteristics being substantially free of dependence on said motor, said waveform having a first slope of a first duration and a second slope of a second duration and of opposite sense to said first slope, and a repetition rate which is high in rela- tion to the commutation rate:

means for producing a substantially smooth ad- justable control voltage; a modulating comparator having a first input to which said repetitive voltage waveform is supplied and a second input to which said adjustable con- trol voltage is supplied, to produce output pulses when intersections occur between said inputs, said output pulses having an "active" on time equal to the interval between alternate pairs of intersections and occurring at said constant repetition rate; and control logic means responsive to the "active" on time of said modulator pulses for providing pulse width modulated signals for control of the energization of the winding stages in said multis- tate energization sequence whereby adjustment of said control voltage, ad- justs the active on time of each pulse and thereby the rate at which electrical energy is supplied to the motor for determination of the motor speed or torque.

2 In a motor speed control circuit for an elec- tronically commutated motor adapted to be ener- gized from a DC power source, said motor having a multistage winding assembly, and a magnetic as- sembly, the two arranged for mutual relative rota- tion, said motor in a given state of a multistate energization sequence having an unenergized winding stage in which an induced back emf is in- tegrated over time to determine the instant at which the mutual relative angular position has been attained suitable for commutation to the next state, and wherein in said given state, a second winding stage is energized in a first sense, and a third winding stage is energized in a second sense inverse to said first sense for serial energization of said second and third winding stages, the combi- nation comprising:

power input terminals for connection to a supply suitable for motor operation; a waveform generator for supplying a repetitive low voltage waveform of substantially constant repetition rate, amplitude and configuration, said characteristics being substantially free of dependence on said motor, said waveform having a first slope of a first duration and a second slope of a second duration and of opposite sense to said first slope, and a repetition rate which is high in rela- tion to the commutation rate; means for producing a substantially smooth ad- justable control voltage; a modulating comparator having a first input to which said repetitive voltage waveform is supplied and a second input to which said adjustable con- trol voltage is supplied, to produce output pulses when intersections occur between said inputs said output pulses having an "active" on time equal to the interval between alternate pairs of intersections and occurring at said constant repetition rate; and control logic means responsive to the "active" on time of said modulator pulses for providing pulse width modulated signals for control of the energization of the winding stages in said multis- tate energization sequence whereby adjustment of said control voltage, ad- justs the active on time of each pulse and thereby the rate at which electrical energy is supplied to the motor for determination of the motor speed or torque.

3 The combination set forth in claim 2 wherein the slope of any variation in said adjustable volt- age is small in relation to the variations of said re- petitive wave.

4 The combination set forth in claim 2 wherein the slope of any variations in said adjustable volt- age is small is in relation to the rate of motor com- mutation.

The combination set forth in claim 3 or 4 wherein said paired intersections embrace positive peaks of the repetitive voltage waveform and the modu- lator output pulses are essentially rectangular waves.

6 The combination set forth in claim 2 wherein the range of adjustment of said adjustable con- trol voltage is comparable to the amplitude of said repetitive voltage waveform to facilitate a large range of speed or torque adjustment.

7 The combination set forth in claim 2 wherein said adjustable control voltage has an adjust- ment range which, at one limit of adjustment, avoids intersection with said repetitive wave to cause said modulating comparator to produce an output which is substantially always on or always off.

8 The combination set forth in claim 2 wherein said adjustable control voltage has an adjust- ment range which, at the limits of adjustment avoids intersection with said repetitive wave to cause said modulating comparator to produce an output which at one limit of adjustment is substan- tially always on and at the other limit of adjust- ment is substantially always off.

9 The combination set forth in claim 2 wherein said first adjustable control voltage has a range GB 2177559 A 39 of adjustment overlapping the range of values of said repetitive wave to cause said modulating comparator to produce an output wave which at one limit of adjustment is substantially always on, at the other limit is substantially always off, and at intermediate adjustments is pulsed.

The combination set forth in claim 2 wherein:

the repetition rate of said repetitive wave is above audibility and below the value at which low frequency solid state switches exhibit significant switching losses.

11 The combination set forth in claim 2 wherein:

the frequency of said repetitive wave is in excess of 20 Khz.

12 The combination set forth in claim 11 wherein:

said repetitive wave is a sawtooth wave whose first slope is of long duration and whose second slope is of short duration.

13 In a motor speed or torque control circuit for an electronically commutated motor adapted to be energized from a power source, said motor hav- ing a multi-state winding assembly and a magnetic assembly, the two arranged for mutual relative ro- tation upon application of a multi-stage energiza- tion sequence, the combination comprising:

power inpuetterminals for connection to a power supply suitable for motor operation; first adjustable voltage reduction means for seri- ally connecting a load via said input terminals to the power supply to provide a variable output volt- age suitable for variable torque or variable speed motor operation; a low voltage dc supply suitable for energization of said speed control circuit, said low voltage dc supply comprising a second voltage reduction means for serially connecting said speed control circuit via said first voltage reduction means and said power input terminals to the power supply; the speed or torque control circuit comprising:

a modulating comparator having a first input to which a repetitive low voltage waveform is sup- plied and a second input to which an adjustable control voltage is supplied, said control voltage changing as said variable output voltage decreases to produce output pulses having an active on time which decreases as said adjustable control voltage decreases, said output pulses appearing when said repetitive voltage waveform and said adjustable voltage intersect, said output pulses occurring at said constant repetition rate and having an "ac- tive" on time equal to the interval between alter- nate pairs of intersections; control logic means responsive to the "active" on time of said modulator pulses for providing pulse width modulated signals for control of the energization of the winding stages in said multis- tage energization sequence; load output terminals for connection to the wind- ing stages of said motor, and power switches responsive to said pulse width modulated signals for connecting the winding stages of the motor via said first adjustable voltage reduction means and via said power input termi- nals to the power supply for winding energization in said multi-state energization sequence, whereby upon operation of said first adjustable voltage reduction means, both the magnitude of the applied voltage and the active on time of the output pulses of the pulse width modulator are simultaneously reduced.

14 In a motor speed or torque control circuit for an electronically commutated motor adapted to be energized from a power source, said motor hav- ing a multistage winding assembly and a magnetic assembly, the two arranged for mutual relative ro- tation upon application of a multi-state energiza- tion sequence, the combination comprising:

power input terminals for connection to a power supply suitable for motor operation; first adjustable voltage reduction means for seri- ally connecting a load via said input terminals to the power supply to provide a variable output volt- age suitable for variable torque or variable speed motor operation; a low voltage dc supply suitable for energization of said speed control circuit, said low voltage dc supply comprising a second voltage reduction means for serially connecting said speed control circuit via said first voltage reduction means and said power input terminals to the power supply; the speed control circuit comprising:

a modulating comparator having a first input to which a repetitive low voltage waveform is sup- plied and a second input to which an adjustable control voltage is supplied, said control voltage, after an initial reduction in motor operating voltage which occasions no change, changing as said vari- able output voltage decreases to produce output pulses having an active on time which decreases as said adjustable control voltage decreases, said output pulses appearing when said repetitive voltage waveform and said adjustable voltage inter- sect, said output pulses occurring at said constant repetition rate and having an "active" on time equal to the interval between alternate pairs of in- tersections, control logic means responsive to the active on time of said modulator pulses for providing pulse width modulated signals for control of the energi- zation of the winding stages in said multi-state energization sequence; load output terminals for connection to the wind- ing stages of said motor, and power switches responsive to said pulse width.

modulated signals for connecting the winding stages of the motor via said first adjustable voltage reduction means and via said power input terminals to the power supply for winding energization in said multi-state energization sequence, whereby after said initial reduction by operation of said first adjustable voltage reduction means, both the magnitude of the applied voltage and the active on time of the pulse width modulator are si- multaneously reduced.

In a motor speed or torque control circuit for an electronically commutated motor adapted to be energized from a power source, said motor hav- GB 2177559 A ing a multistate winding assembly, and a magnetic assembly, the two arranged for mutual relative ro- tation, said motor in a given state of a multistage energization sequence having an unenergized winding state in which an induced back emf is in- tegrated over time to determine the instant at which the mutual relative angular position has been attained suitable for commutation to the next stage, and wherein in said given state at least one other winding stage is energized in the appropriate sense to cause relative rotation, the combination comprising:

power input terminals for connection to a power supply suitable for motor operation; first adjustable voltage reduction means for seri- ally connecting a load via said input terminals to the power supply to provide a variable output volt- age suitable for variable torque or variable speed motor operation; a low voltage dc supply suitable for energization of said speed control circuit, said low voltage dc supply comprising a second voltage reduction means for serially connecting said speed control circuit via said first voltage reduction means and said power input terminals to the power supply; the speed control circuit, comprising:

a waveform generator for supplying a repetitive low voltage waveform of substantially constant repetition rate, amplitude and configuration, said characteristics being substantially free of depend- ence on said motor, said waveform having a first slope of a first duration and a second slope of a second duration and of opposite sense to said first slope, and a repetition rate which is high in rela- tion to the commutation rate, means for producing an adjustable, substantially smooth control voltage, a modulating comparator having a first input to which said repetitive low voltage waveform is sup- plied and a second input to which said adjustable voltage is supplied, to produce output pulses when intersections occur between said repetitive low voltage waveform and said adjustable voltage, said output pulses occurring at said constant repetition rate and having an "active" on time equal to the interval between alternate pairs of intersections; control logic means responsive to the "active" on time of said modulator pulses for providing pulse width modulated signals for the winding stages in said multistage energization sequence; load output terminals for connection to the wind- ing stages of said motor, and power switches responsive to said pulse width modulated signals for connecting the winding stages of the motor via said first adjustable voltage reduction means and said power input terminals to the power supply for winding energization in said multi-state energization sequence.

16 The combination set forth in claim 15, wherein the means for producing said adjustable control voltage comprises a voltage divider with a movable tap, the divider being connected across said low voltage dc supply, and the movable tap being connected to the second input of said modu- lating comparator whereby said first adjustable voltage reduction means or said adjustable tap provides adjustment of motor torque or speed.

17 The combination set forth in claim 15 wherein voltage stabilizing means is provided for said low voltage dc supply, and the means for producing said adjustable control voltage comprises means for deriving a voltage dependent on said variable output voltage sensed to decrease the active on time of said PWM pulses as said variable output voltage is reduced.

18 The combination set forth in claim 15 wherein voltage stabilizing means are provided for said low voltage dc supply, and the means for producing said adjustable control voltage comprises solid state means for deriving a voltage which after an initial reduction in said vari- able output voltage, which occasions no change in said control voltage, changes with additional de- creases in said variable output voltage in a sense to reduce the active on time of said pulse width modulated pulses.

19 The combination set forth in claim 17 or 18 wherein the means for producing said adjustable control voltage comprises a voltage divider with a mova- ble tap, the voltage divider being connected across said low voltage dc supply, and the tap being con- nected to the second input of said modulating comparator, the setting of said movable tap setting the maxi- mum motor torque or speed, and the setting of said first adjustable voltage reduction means re- ducing the speed or torque below the maximum setting.

The combination set forth in claim 18 wherein said solid state means comprises, a voltage divider with an output tap across which said variable output voltage is applied, and a transistor having the emitter connected to one terminal of said low voltage dc supply, the base connected to the output tap of said voltage divider, and the collector coupled to the second input of said modulating comparator.

21 The method of controlling the speed or torque of an electronically commutated motor en- ergized from a power source, said motor having a multistage winding assembly, and a magnetic as- sembly, the two arranged for mutual relative rota- tion, said motor in a given state of a multistate energization sequence having an unenergized winding stage in which an induced back emf is in- tegrated over time to determine the instant at which the mutual relative angular position has been attained suitable for commutation to the next state, and wherein in said given stage, at least one other winding stage is energized in the appropriate sense to cause relative rotation, comprising generating a repetitive low voltage waveform of substantially constant repetition rate, amplitude and configuration, said characteristics being sub- stantially free of dependence on said motor, said GB 2 177559 A 41 waveform having a first slope of a first duration and a second slope of a second duration and of opposite sense to said first slope, and a repetition rate which is high in relation to the commutation rate; adjusting a substantially smooth control voltage for speed or torque control comparing said repetitive voltage waveform to said adjustable control voltage in a modulator to produce output pulses when intersections occur between said inputs, said output pulses occurring at said constant repetition rate and having an "ac- tive" on time equal to the interval between alter- nate pairs of intersections; and providing pulse width modulated signals during the active on time of said modulator pulses for control of the electrical energy supplied in the energization of the winding stages in said multis- tate energization sequence.

22 The method of controlling the speed or torque of an electronically commutated motor en- ergized from a power source, said motor having a multistage winding assembly, and a magnetic as- sembly, the two arranged for mutual relative rota- tion, said motor in a given state of a multistate energization sequence having an unenergized winding stage in which an induced back emf is in- tegrated over time to determine the instant at which the mutual relative angular position has been attained suitable for commutation to the next state, and wherein in said given state at least one other winding stage is energized in the appropriate sense to cause relative rotation, comprising provid- ing a variable output voltage suitable for variable speed or variable torque motor operation by means of an adjustable voltage and reduction means serially connecting said motor to said power source; generating a repetitive low voltage waveform of substantially constant repetition rate, amplitude and configuration, said characteristics being sub- stantially free of dependence on said motor, said waveform having a first slope of a first duration and a second slope of a second duration and of opposite sense to said first slope, and a repetition rate which is high in relation to the commutation rate; providing an adjustable substantially smooth control voltage for motor speed or torque control and comparing said repetitive voltage waveform to said adjustable control voltage in a modulator to produce output pulses when intersections occur between said inputs, said output pulses occurring at said constant repetition rate and having an "ac- tive" on time equal to the interval between alter- nate pairs of intersections; applying energy from said power source to said motor during the active on time of said modulator pulses; and selectively adjusting said variable output voltage or said adjustable control voltage for motor speed or torque control.

23 The method of controlling the speed or torque of an electronically commutated motor en- ergized from a power source, said motor having a multistage winding assembly, and a magnetic as- sembly, the two arranged for mutual relative rota- tion, said motor in a given state of a multistate energization sequence having an unenergized winding stage in which an induced back emf is in- tegrated over time to determine the instant at which the mutual relative angular position has been attained suitable for commutation to the next state, and wherein in said given state at least one other winding stage is energized in the appropriate sense to cause relative rotation, comprising providing a variable output voltage suitable for variable speed or variable torque motor operation by means of an adjustable voltage reduction means serially connecting said motor to said power source generating a repetitive low voltage waveform of substantially constant repetition rate, amplitude and configuration, said characterstics being sub- stantially free of dependence on said motor, said waveform having a first slope of a first duration and a second slope of a second duration and of opposite sense to said first slope, and a repetition rate which is high in relation to the commutation rate; providing an adjustable substantially smooth control voltage for motor speed or torque control and comparing said repetitive voltage waveform to said adjustable control voltage in a modulator to produce output pulses when intersections occur between said inputs, said output pulses occurring at said constant repetition rate and having an "ac- tive" on time equal to the interval between alter- nate pairs of intersections; applying energy from said power source to said motor during the active on time of said modulator pulses; and simultaneously adjusting said variable out- put voltage and said adjustable control voltage for motor speed or torque control.

24 The method of controlling the speed or torque of an electronically commutated motor en- ergized from a power source, said motor having a multistage winding assembly, and a magnetic as- sembly, the two arranged for mutual relative rota- tion, said motor in a given state of a multistate energization sequence having an unenergized winding stage in which an induced back emf is in- tegrated over time to determine the instant at which the mutual relative angular position has been attained suitable for commutation to the next state, and wherein in said given state at least one other winding stage is energized in the appropriate sense to cause relative rotation, comprising providing a variable output voltage suitable for variable speed or variable torque motor operation by means of an adjustable voltage reduction means serially connecting said motor to said power source; generating a repetitive low voltage waveform of substantially constant repetition rate, amplitude and configuration, said characteristics being sub- stantially free of dependence of said motor, said waveform having a first slope of a first duration and a second slope of a second duration and of 42 GB 2 177559 A opposite sense to said first slope, and a repetition rate which is high in relation to the commutation rate; providing an adjustable substantially smooth control voltage for motor speed or torque control and comparing said repetitive voltage waveform to said adjustable control voltage in a modulator to produce output pulses when intersections occur between said inputs, said output pulses occuring at said constant repetition rate and having an "a;,- tive" on time equal to the interval between alter- nate pairs of intersections; applying energy from said power source to said motor during the active on time of said modulator pulses; and adjusting only said variable output voltage for a small reduction in motor speed or torque, and for a further reduction simultaneously adjusting said variable output voltage and said control voltage for motor speed or torque control.

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Published by The Patent Office, 25 Southampton Buildings, London, WC 2 A 1 AY, from which copies may be obtained.