GB2141888A - Electronically commutated motors - Google Patents

Abstract

A control circuit for an electronically commutated motor (102, 120) performs essential internal commutation and control functions and responds to external controls, usually user operated. In one embodiment a ceiling fan (100-102) is subject to controls over motor speed or torque, and direction of rotation. The control circuit uses a differential transconductance amplifier (141), which is periodically balanced (143), for commutation timing. Control logic (145) includes a bidirectional counter arranged for uniformity in count duration irrespective of the count, direction of counting, or changes in direction of counting, and a five rank decoding structure which selects an unenergized motor winding stage for sensing, selects the energized winding stages for suitable sensed emergization, and responds to both direction and energy controls. Circuit protection (150) is provided when power is first turned on. <IMAGE>

Description

SPECIFICATION Electronically commutated motors This invention relates in general to domestic appliances powered by an electronically commutated motor (ECM), a method of operating an ECM, and more particularlyto a control circuitforan ECM. The invention further relates to control circuits for ECMs suited to fabrication in solid state electronic form to a large degree utilizing monolithic integrated circuitry, to integrated circuits having application to such control circuits for ECM motor powered appliances, and to an ECM powered variable speed fan incorporating such control circuitry.

Control circuits for electronically commutated motors have hitherto been fabricated using discrete electronic components, and yet the desirability of fabricating such control circuits in solid state electro nicform,to a large degree utilizing monolithic integrated circuitry, is widely honored in discussions among electrical industry spokesmen if not by an equally wide presence of products incorporating such monolithic integrated circuitry in the actual market place.

The electronically commutated motors for which such control circuitry would have application is exemplified by those ECMs disclosed in U.S. Patent Nos. 4,005,347 and 4,169,990to David M. Erdman, and U.S. Patent No. 4,162,435 to Floyd H. Wright. These motors are characterized by having a multistage winding assembly, and a magnetic assembly, the two arranged for mutual relative rotation, the motor in a given state of a multistate energization sequence, having an unenergized winding stage in which an induced back emfappears, which when integrated overtime to a predetermined value indicates the instant at which the mutual relative angular position has been attained suitable for commutation to the next state.In the most common examples, the multistage winding assembly is stationary, with the magnetic assembly arranged within the winding assembly, and arranged to rotate with respect to the immediate environment by means of bearings attached to a frame, mechanically common with the winding assembly. The mechanically opposite arrangement in which the winding assembly rotates within the magnetic assembly is less common, but makes many ofthe same requirements ofthe control circuitry, and in general the control circuitry has equal application to such motors. In addition, the more common, magnetic assembly in such motors is a permanent magnetic assembly. However, an arrangement in which the magnetic assembly is electromagnetic makes many of the same requirements of the control circuitry, and in general, the control circuitry has equal application to such motors.

The common requirements of the control circuitry for electronically commutated motors, may be divided into fourcategories, which in a sense, place differing requirements upon theirfabrication. The appliance is installed in the house, and controls located when practical in the appliance, and when not practical, located at wall locations convenientto the user. In the practical case of a combined ceiling fan, lighting fixture, which is the practical product exemplified herein, the "fan" includes a motor, a light and user operated controls for the same. The controls are both integral with the lighting fixture and remote. The remote control may be located upon a convenient wall location and it may embody largely duplicate user operated controls.The usual functions ofthe user operated controls include turning on orturning off the fan or light, regulating the intensity ofthe light, regulating the speed of rotation, or direction of rotation ofthefan.

The user operated controls, particularlythose on the wall controls, are themselves constructed similarlyto other wiring devices used in the home, and they are interconnected by electrical cable typical of the customary 1 AC house wiring. In general, the requirement placed upon such "control systems" is thatthe interconnections be minimal, and if possible not require additional special wiring. Ideally, the wiring installation would permit complete communication within the "control systems" by the minimum two wire cable. Ideally,the user operated control circuitry exemplified herein should require no more than two wires between the wall control, the fixture, and the house wiring for minimum installation expense. In this category, the control circuit is fabricated in the form typical of house wiring systems.

A second category of electrical control circuit fabrication is utilized within the enclosure of the ceiling fixture or ofthe wall control. This usually is "point to point" wiring, and the electrical connections are made with mechanical bonds, including solder, rivets, or electrical terminals. Here, the stress is often upon compactness, and ease of on-site assembly.

Athird category of electrical control circuitfabrication, which is often practiced in thefixture itself or in the wall control, is that which is usually performed in the factory, and which is called "printed circuit board" (PCB) wiring. This wiring is of moderate density, and allows for ampere level currents, voltages in excess of the customary house level voltages (120-240, etc.), and heat dissipation levels comparable to the needs of the customary home appliances. This wiring is used to interconnect-- by a factory process, discrete electronic components, such as resistors, capacitors, inductors, discrete solid state devices, such as transistors, diodes, diacs, triacs, SCRs, etc. on the printed circuit board.

When the control application of the control circuitry is as complicated as the provision of electronic commutation of an ECM motor and the imposition of user operated controls, and automatic protection functions incidental to user operated controls, then the complexity ofthe control function required of the control circuitry tends to transcend the practical limits offabrication by the assembly of discrete electrical components upon a printed circuit board. In the printed circuit mode offabrication for such control circuitry, the volume weight, and costs of printed circuit fabrication are greater by a factor of at least a hundred, and often by a factor of a thousand times the comparable measure of a circuit of monolithic inte- grated circuitfabrication of like complexity.

The thrust of these practical considerations upon control circuitfabrication is to perform all of the control functions that can be performed, taking into accountthe limitations on allowable current levels, voltage levels and power dissipations, with monolithic integrated circuitry.

Present day limitations upon the application of integrated circuitry are less restrictive than some time ago, and more restrictive than one would expect some time in the future. In general, circuitry complexity required forthe control function herein contemplated can be handled with MSI (Medium Scale Integration) or LSI (Large Scale Integration). In the usual case, the component count of the motor control system is on the order of 102to 103.

The current, voltage and power dissipations ordinarily dictate special interfacing circuits between the monolithic integrated circuit and the user operated controls, the motor, the light and the power mains. In general, this dictates that voltages applied to the IC not exceedthevoltage rating ofthe integrated circuit process, typicallyfrom 5 to 40 volts, that currents should not exceed tens of milliamperes and that power dissipation not exceed 100s of milliwatts.

Because of voltage limitations, it is necessary to use voltage dividers coupled to the winding stages ofthe motors to reduce the back emf sensed on the winding stages to several volts (e.g. about3 volts) before application to the integrated circuit. Similarly, the control of powerto the winding stages of the motor requires current and power dissipation levels that can only be performed by discrete solid state switches.

The integrated circuit, accordingly, has terminal pads supplied by internal drivers, with the powerto control either directly orthrough additional buffers, the solid state powerswitches energizing the winding stages of the motor. A similar practical problem relates to the non-integrable components, which are primarily large capacitors, inductors, and the user operated controls.

these may usually be coupled to the pads ofthe monolithic integrated circuit with no other transition than the terminal pads ofthe integrated circuit and a demountable 16 pin connection on the printed circuit board.

There is a need to use a standard package with ICs in orderto keepthecostminimum.This istypically 16 pins. There is also a need to keep outboard ofthe IC, components which control parameters which may changefrom productto product such as the inertia of the fan blades. In otherwords, the IC must be able to adaptto expected changes and must use a standard low cost package. Some components which could be integrated are sometimes not put in the IC forthese good engineering reasons.

To date, "maximally" monolithically integrated control circuits for electronically commutated motors are not in common use in the market place.

Accordingly, it is an object ofthe present invention to provide a maximally monolithically integrated control circuit for an electronically commutated motor.

It is another object of the invention to provide an improved control circuit for an electronically commutated motor.

It is still another object ofthe invention to provide a control circuit for an electronically commutated motor with improved commutation.

It is an additional object of the invention to provide a control circuitforan electronically commutated motor with improved speed or torque control.

It is a further object ofthe invention to provide a control circu it for an electronically commutated motor with improved reversing.

It is another object ofthe invention to provide a control circuitforan electronically commutated motor with improved starting performance.

It is an additional object ofthe invention to provide a control circuit for an electronically commutated motor in which the commutation timing circuitry is improved.

It is a further object ofthe invention to provide a control circuit for an electronically commutated motor in which starting performance is improved.

It is another object ofthe invention to provide in a control circu it for an electronically commutated motor, a commutation timing circuit that is self balancing.

It is an additional object ofthe invention to provide an improved control circuitforan electronically commutated motor combining reversal of the motor with speedltorque control It is another object ofthe invention to provide a circuit for reversing an electronically commutated motor providing means for protecting the power switches during reversal.

It is another object ofthe invention to provide an improved integrated control circuit for an electronical lycommutated motor.

It is still another object ofthe invention to provide an integrated control circuit for an electronically commutated motor with improved commutation.

It is an additional object of the invention to provide an integrated control circu it for an electronically commutated motor with improved speed or torque control.

It is a further object ofthe invention to provide an integrated control ci rcuit for an electronically commutated motor with improved reversing.

It is another object of the invention to provide an integrated control circuitfor an electronically commutated motor with improved starting performance.

It is an additional object of the present invention to provide a maximally integrated control circuit for an electronically commutated motor, providing economical remote control.

It is a further object ofthe invention to provide an improved method of operating an electronically commutated motor.

It is an additional object ofthe invention to provide an improved method of timing the commutation of an electronically commutated motor.

It is another object of the invention to provide a method of improving the starting operation of an electronically communtated motor.

It is a further object ofthe invention to provide an improved method of controlling the speed ortorque of an electronically commutated motor.

It is another object ofthe invention to provide an improved method of remotely controlling the speed ortorque of an electronically commutated motor.

It is a further object of the invention to provide an improved method of reversing an electronically com mutated motor.

It is another object ofthe invention to provide an improved method of control of an electronically commutated motor combining reversing with speed/ torque control.

These as well as other objects of the invention will be dealt with in the description which follows. They are achieved in a control circuitforan electronically commutated motor adapted to be energized from a DC powersource,the motor having a three stage winding assembly, and a magnetic assembly, the two arranged for mutual relative rotation. In a given state of a six state energization sequence causing relative rotation, the motor has one winding stage energized in one sense, a second winding stage energized in an opposite sense and serially connected with the first winding stage, and a third winding stage unenergized.

The inventive combination comprises input terminal meansforconnection to the winding stages and to the neutral motor connection orequivalentforderiving the back emf induced in successive unenergized winding stages, input switching means for selecting an unenergized winding stage responsive to an unenergized winding-stage selection signal; a two input, differential transconductance amplifier means for conversion ofthe voltage supplied to a corresponding current; capacitive integration means for providing a voltage substantially proportional to the integral ofthe back emf; and timing comparison means for comparing the voltage at the integration meanstoavaluesuitableforcommutation,and upon sensing equality generating a timing signal atthe instantforcommutation.

Continuing, the inventive combination includes control logic means for generating winding stage selection signals in a first six state sequence for forward motor rotation, and in a second six state sequence for reverse rotation, in each state of which a signal is generated for selecting one winding stage for energization in one sense, a signal is generated for selecting one winding stage for energization in the other sense, and a signal is generated for selecting an unenergized winding stage for selecting an unenergized winding stage for sensing the induced back emf, the motor energization state changing in response to the timing signal atthe instantfor commutation to the next state in the sequence.The control logic means is responsive to a direction control signal for selection of the first or second energization sequence and to an energy control signal in a form including periodic pulse width modulated (PWMed) pulses, having a repetition rate which is high in relation to the commutation rate, winding stage energization occurring only during the active on time of the pulse of the energy control signals.

The inventive combination also includes a threefold plurality of power switching means responsive to thewinding stage energization signals for approp riately sensed energization of the winding stages in the multistate sequences.

In accordance with another facet ofthe invention means are provided for periodically resetting the integration means to an initial state suitable for initiating the succeeding integration; and for periodically nulling the output current ofthe amplifier means, the nulling being timed to occur after the instantfor commutation, but priorto reset. The nulling means comprising means for incrementing an offset current at the input ofthe amplifier means to a value which corrects imbalance in the output current, and means for sustaining the corrective offset current until nulling again occurs. Typically the nulling occurs once per commutation.

The input to the differential amplifier is coupled from the individual winding stages and the neutral connection by means of a four part voltage dividerfor scaling down the induced back emf to a value that the control circuitry can accommodate.

In accordance with a facet ofthe invention, control logic means comprises counting means having one count for each of the (6) states of the motor energization sequence (e.g., 0-1; 1-2; 2-3; 3-4; 4-5; 5-0; 0-1; etc.) and at a constant rate of rotation allocates equal time for each count in a repeating sequence. The counting means comprises a minimum number of flip-flops for defining the states, the flip-flops being positive (or negative) edge triggered flip-flops; which are clocked simultaneously by the timing signal.

The duration ofthe timing signal is long in relation to the propagation delays in the control logic means, and is long enough to null the amplifier means and reset the integration means.

The winding stage selection signals are derived from the states ofthe counting means. The input switching means to which the unenergizedwinding selection signals are applied, consists of a six-fold plurality of gates. Accordingly,the control logic means includes a first rank of six gates connected to the outputs of the (three) flip-flops, and a second rank of six gates connected to the outputs of said first rank of gates.

The first rank of gates produces a first succession of six equal duration pulses having an active period equal tothe duration of one motorenergization state, and are used for operation ofthe input switching means.

The second rank of gates produces a second succession of six equal duration pulses having an active period equal to the duration of two motor energization states, the second succession occuring in an overlapping sequence. The double duration signals are used for operation ofthe power switching means.

As earlier noted, the control logic is responsive to direction control signals and to energy control signals, having three ranks of gates for that purpose.

The 6-fold plurality of gates, responsive to direction and energy control signals, consists of two ranks of three input gates, one rank ofgatesfortransmission of the forward multistate sequence, one rank of gates for transmission ofthe reverse multistate sequence, and a third rankof two input gates for "oring"the outputs of said forward and reverse ranks of gates. One input of each of the forward and reverse ranks of gates is coupled to an output of the second rank of gates, a second input of each ofthe forward and reverse ranks of gates is for application ofthe PWMed energy control signal.

In accordance with another facet of the invention, the control logic means includes means responsiveto the timing signal to applythe PWMed energy control signal atthe beginning of the first half ofthe energization period of a winding stage forthe duration of said timing signal, and atthe beginning of the second half ofthe energization period of a winding stage, delaying for the duration of said timing signal, before applying said PWMed energy control signal, for the remainder ofthe energization period.

Atthe output ofthe control logic means, six output drivers are provided for coupling the energized winding stage selection signals to the power switching means. Three ofthe output drivers are for control of power switches connecting individual winding stages to oneterminal (e.g. positive) ofthe power source; and three of said output drivers are for control of power switches connecting individual winding stages to the other terminal (e.g. negative) ofthe power source.

In accordance with a furtherfacet of the invention, the control circuit is provided with a power on reset circuit for producing an active output responsive to the voltage ofthe low voltage DC supply ofthe control circuit for gating off the drivers when the voltage has been below a first value when power is turned on or below a second value when power is turned off. The voltage values being set such that normal circuit operation is assured at supplyvoltages exceeding the first and second values.

In operation, the protective circuit gates off the drivers when power is turned on for a period oftime required for stabilization of the operation of the control circuit. It is accomplished by generating an artificial timing signal when power is turned on, signalling an artificial instantfor commutation, nulling the amplifier means and causing the generation of at least a partial sequence ofwinding stage selection signals and nulling before the drivers are gated on.

According to another aspect ofthe invention, the above objects are achieved in a control circuitforan electronically commutated motor adapted to be energized from a DC power source, the motor having a multistate winding assembly, and a magnetic assembly, the two arranged for mutual relative rotation. In a given state of a multistage energization sequence, the motor has an unenergized winding stage in which induced back appears which when integrated overtime to a predetermined value indicates the instant at which the mutual relative angular position has been attained suitable for commutation to the next state.An inventive combination in the control circuit comprises a solid state transconductance amplifier means adapted to be coupled to an unener gizedwinding stage in the motorforconvertingthe voltage appearing in the winding stage to a corresponding output current, integration means coupled to the output ofthe amplifier means for integrating the output current to obtain an output voltage substantial- ly proportional to an integral ofthevoltage appearing in the winding stage, and comparison means for comparing the outputvoltage of the integration means to a value corresponding to the mutual relative angular position suitable for commutation, and upon sensing equality generating a timing signal atthe instantfor commutation.

In accordance with one facet of the invention the transconductance amplifier means has current series feedback to stabilize amplifiertransconductance.

In the principal embodiment, the motor has a multistage winding arrangement with a neutral con nection. Thetransconductance amplifier means is, accordingly, a two input differential amplifier means, with one input adapted to be coupled to an unenergized winding stage and the other input adapted to be coupled to the neutral connection orthe equivalent.

The input stage of the amplifier means, is a differential input stage, which determines the transconductance of the amplifier means, with significant current series feedback being provided for stabilizing this parameter in that stage.

The subsequent stages of the transconductance amplifier means are arranged to exhibit unity current gain and a first and a second solid state current mirror are included. The output currentfrom one transistor in the inputstage is coupled to one current mirrorand the output current from the othertransistor in the input stage is coupled to the second current mirror.

Thetransconductance amplifier means is completed with a first and a second solid state buffer amplifier, and a third, polarity inverting, current mirror.

More particularly,thefirst buffer amplifier comprises a third transistor having the control electrode common and a first principal electrode coupled to the output ofthe first current mirror, and the second principal electrode coupled to the input of the polarity inverting current mirror. The second buffer amplifier comprises a fourth transistor having the control electrode common and a first principal electrode coupled to the output ofthe second current mirror.

The third current mirror comprises a fifth, output transistor having its control electrode coupled to the second principal electrode ofthe third transistor and a first principal electrodethereofconnected to the second principal electrode ofthefourth transistor, the fourth and fifth transistors being connected to provide a push-pull output in which output current is either supplied orwithdrawn.

In accordance with a further aspect ofthe invention, means are provided for periodically resetting the integration means to an initial state suitable for initiating the succeeding integration. In addition, means are provided for periodically nulling the output current of the transconductance amplifier means, the nulling being timed to occur after the instant for commutation, but prior to resetting the integration means. The nulling means comprises means for incrementing the offset current ofthe current mirror to a value which corrects imbalance and sustains the corrective offset current until nulling again occurs.

More particularly, the nulling means comprises means for zeroing the differential input voltage applied between the inputs of the transconductance amplifier means and for establishing a desired output current level in the first and second transistors of the input stage amplifier, output switching means for disconnecting the output ofthe transconductance amplifier means from the integration means during the nulling interval, and a nulling comparator coupled to the output of the transconductance amplifier means for detecting a change in sense of the outputcurrent, as the amplifier goes through balance to terminatethe incrementing process and initiate resetting the in tegration means.

More particularly, the offset current incrementing means comprises means for supplying a clocking single (e.g. 20Khz) having a period which is short in relation to the commutation period and a nulling counter counting atthe rate ofthe clocking signal. The stateofthenullingcountercontrolsthesum ofthe increments of offset current, and is preset in response to the timing signal. Subsequent counting during nulling adjusts the current offset toward balance until a null is detected bythe nulling comparator.

In accordance with a further aspect ofthe invention, a lowvoltage DC supply is provided suitable for operation ofthe control circuit, the voltage of the supply changing at a finite rate when power is turned on or off. A protection circuit is provided for producing an active output responsive to the voltage ofthe low voltage DC supplyfor holding at least a portion ofthe control circuit in an inactive state when the voltage is below a first value when power is turned on or below a second value when power isturned off. When the voltage has exceeded the first value as power is turned on, the circuit portion is released at a predetermined initial state. The voltage values are set such that normal circuit operation is assured at supply voltages exceeding the first and second values.

Preferably, the protection circuit, upon termination ofthe active output as power is turned on, releases the circuit "portion" in a state to null the amplifier means to insure balance of the output current ofthe amplifier means before integration of its output current. The protection circuit during said active output, presets the nulling counter, and upon termination ofthe active output, as power is turned on, releases the circuit portion in a state for nulling the amplifier means. The state for nulling comprises activation of the zeroing means atthe input ofthetransconductance amplifier means, activation of the amplifier output switching means for disconnection, and the release ofthe nulling counter.

The protection circuit further comprises means to cause a starting offset in the output current of the amplifier means to insure integration of the output current to a voltage sufficient for generating the commutation timing signal, the starting offset current, except during said nulling interval(s) extending over a sufficient period after power is applied to allow for control circuit stabilization. This period is typically five commutation periods.

In accordance with a further aspect ofthe invention a novel method oftiming the commutation of an electronically commutated motor is disclosed, the principal steps ofwhich comprise converting the differential voltage appearing in the unenergized winding stage to a corresponding bidirectional output current by means of a two input solid state differential transconductance amplifier means, integrating the outputcurrentto obtain an output voltage substantial- ly proportional to an integral ofthe differential voltage; and comparing the outputvoltage of the integration means to a value corresponding to the angular position ofthe rotor suitable for commutation, and upon sensing equality, generating a timing signal attheinstantforcommutation.

Subsequent steps of the timing method comprise resetting the integration means to an initial state suitable for initiating the succeeding integration subsequent of each timing signal, and periodically nulling the output current of the transconductance amplifier means.

In a preferred method of operating an electronically commutated motor, in which a differential transconductance amplifier is used fortiming the instantfor commutation, the steps comprise nulling the amplifier means upon turning on powerforthe control circuit prior to turning power on for the motor. Then the differential voltage appearing in the unenergized winding stage is converted to a corresponding bidirectional output current, integrated to obtain an output voltage, and compared to a stored value for generating atiming signal atthe instant suitable for commutation. After a delay, power is applied to the motor in response to the nextorasubsequenttiming signal, selected to allow adequate time forthe control circuitto stabilize.Next the integration means are resettoan initial state suitableforinitiating the succeeding integration, which occurs subsequent to each timing signal. Thereafter the output current of thetransconductance amplifier means is perioidically nulled.

According to a further aspect ofthe invention, the above objects are achieved in a motor speed ortorque control circuitfor an electronically commutated motor adapted to be energised from a power source, the motor having a multistage winding assembly, and a magnetic assembly, the two arranged for mutual relative rotation, the motor in a given state of a multistate energization sequence having an unenergized winding stage in which an induced back emf is integrated overtime to determine the instant at which the mutual relative angular position has been attained suitable for commutation to the next state, and wherein in said given state, at least one otherwinding stage is energized in the appropriate sense to cause relative rotation.

An inventive combination in the control circuit comprised power input terminals for connection to a supply suitable for motor operation; a waveform generator for supplying a repetitive low voltage waveform of substantially constant repetition rate, amplitude and configuration, the characteristics being substantiallyfree of dependence on said motor, the waveform having a first slope of a first duration and a second slope of a second duration and of opposite sense to said first slope, and a repetition rate which is high in relation to the commutation rate; means for producing a substantiallysmooth adjustable control voltage; a modulating comparator having a first input to which said repetitive voltage waveform is supplied and a second input to which said adjustable control voltage is supplied, to produce output pulses when intersections occur between said inputs said output pulses occurring at said constant repetition rate, having an "active" on time equal to the interval between alternate pairs of intersections; and control logic means responsive to the "active" on time of said modulator pulses for providing pulse width modulated signals for control of the energization ofthe winding stages in the multistate energization sequence.In operation, adjustment of the control voltage, adjusts the active on time of each pulse and thereby the rate at which electrical energy is supplied to the motorfor determination ofthe motor speed or torque.

The repetitive voltage waveform is preferably a saw tooth waveform, having a repetition rate above 20Khz.

The adjustable voltage is smooth in relation to the motorcommutation rate and in relation to the repitition rate ofthe repetitive voltage waveform. The inputs supplied to the modulating comparator are selected in the preferred case to produce an output waveform which at one limit of adjustment is substantially always on, at the other limit is substantially always off, and at intermediate adjustments is pulsed rectangular waveform ofvariable width.

A second means of variable speed ortorque control is provided byan adjustable voltage reduction means serially connecting the motorto the power supply.

This voltage reduction means in the power circuit is preferably used in concert with the adjustable control voltage affecting the active on time ofthe pulse width modulation pulses used to control the application of powerto the motor.

In a preferred embodiment, the adjustable voltage reduction means, is independent of the adjustable control voltage to produce a first reduction in motor speed ortorque, butforfurther reductions, means are provided to make the adjustable control voltage applicable to the pulse modulator dependent upon its reduced voltage for powering the motor. This brings about a joint reduction in both the voltage and duty cycle ofthe PWMed energy supplied to the motor.

This permits a full range of speed or torque control down to stalling speed, with a smaller reduction in motor voltage, and permits the reduced voltageto remain large enough at all times to sufficiently power the control circuit.

In accordance with a further aspect ofthe invention, a novel method of controlling the speed or torque of an electronically commutated motor is disclosed. The steps entail providing a variable output voltage suitable for variable speed or variable torque motor operation by means of an adjustable voltage reduction means serially connecting the motortothe power source, generating a repetitive low voltage sawtooth waveform of substantially constant parameters; providing an adjustable substantially smooth control voltage for motor speed ortorque controls comparing the repetitive voltage waveform to said adjustable control voltage in a modulator to produce output pulses when intersections occur between said inputs, the output pulses occurring at the repetition rate ofthe sawtooth waveform and having an "active" on time equal to the interval between alternate pairs of intersections; applying energy from the power source to the motor during the active on time of the modulator pulses, and adjusting onlythe variable output voltage for a small reduction in motor speed or torque, and for a further reduction simultaneously adjusting the variable output voltage and the control voltage for motor speed or torque control.

According to still another aspect ofthe invention, the above objects are achieved in a motor control circuit for an electronically commutated motor adapted to be energized from a power source, said motor having a multistage winding assembly and a magnetic assembly, thetwo arranged for mutual relative rotation. In a given state of a multistate energization sequence, the motor has an unenergized winding stage in which an inducedbackemfis integratedovertimetodeterminethe instantatwhich the mutual relative angular position has been attained suitable for commutation to the next state of the sequence. In each state ofthe sequence at least one other winding stage is energized in the appropriate sense to cause relative rotation.In the practical example herein treated, one sequence is designed for clockwise operation and a second sequence for counterclockwise operation.

The control circuit combines a first adjustable voltage reduction means for seriallyconnecting the motor to the powersupplyto provide a variable output voltage suitableforvariable speed ortorque operation; with means for producing a substantially smooth control voltage, dependent on the variable output voltage. The control voltage, upon passing through an intermediate value corresponding to a useful limit of the adjustable means, continues monotonicallytoward a final value. Means are provided responsive to a value of said control voltage between the intermediate and final values for generating a signal for control of the direction of motor rotation.

Preferably, the intermediate value of control voltage correspondsto the desired minimum motor speed or torque, typicallywhen the motor stalls in a ceiling fan application, and the change in direction occurs past stalling toward the minimum output voltage.

In accordance with a furtherfacet of the invention, the rate of downward adjustment of energy per unit change in output voltage is enhanced by means of a pulse width modulator also responsive to the control voltage. The pulse width modulator produces output pulses of constant rep-tition rate, the reptition rate being high in relation to the commutation rate, but with variable on times under the control of the control voltage. The energy, which is supplied to the motor during the active on times ofthe pulses, is thus reduced when a reduction in output voltage occurs, both by virtue of the voltage reduction, and by virtue of a reduction in the averagetime thatthevoltage is applied (i.e., the width of the PWMed pulses controlling energy supplied to the motor are concurrently reduced).

In effecting the desired range of speed or torque control,with a highervoltageatthe minimum desired setting (i.e., the motor stall setting) it becomes possible to energize the control circuit through a voltage dropping network connected in parallel with the motor circuit. This then facilitates remote control operation, in that a simple wall control can achieve full range control ofthe motor speed ortorque, and atthe minimum setting effect a reversal also remote.

In the preferred embodiment,the motor direction control logic has two outputs, one for facilitating forward operation (clockwise rotation) by means of an active high in the output state, and the otherfacilitating reverse operation (counter clockwise rotation) by means of an active high in the output state. The internal logic precludes the output states from being active simultaneously, and when a state is changed, delaying the appearance of the new active state, after discontinuance ofthe prior active state, by a time long enough to protectthe power switches. This period is typically in excess of the period of one pulse ofthe modulator.

The motor direction may be controlled by a switch coupled to the direction control logic, and normally on the fixture incorporating the fan. This switch, in accordance with a fu rtherfacet ofthe invention functions with a protective circuit active during power up and power down to determine the motor direction when powercomes backon afteran interruption.

In accordance with a further aspect ofthe invention, a novel method of controlling an electronically commutated motor is disclosed. The steps entail reducing the outputvoltage supplied to the motor through a range of values suitable forvariable speed ortorque operation, producing a substantially smooth control voltage, dependent on the variable output voltage,the control voltage, upon passing through an intermediate value corresponding to a minimum useful reduction, continuing monotonicallytoward a final value, and generating a signal for changing the direction of motor rotation at a value of the control voltage between said intermediate and final values.

In accordance with a further aspect ofthe inventive method the rate of downward adjustment of energy per unit change in output voltage supplied to the motor is enhanced and the range of voltage reduction required forthe desired minimum setting (e.g., motor stalling) reduced by means of a pulsewidthmodula- tor. The pulse modulator, produces output pulses whose "on" time also controls the rate at which energy is supplied to the motor.

As a further variation of the inventive method, the generation ofasignalfor motor reversal entailsfirst generating a signal for suspending the energization for motor rotation in one sense, and after a short interruption for protection of the motor switches, generating a signal for motor rotation in an opposite sense.

The novel and distinctive features of the invention are setforth in the claims appended to the present application. The invention itself, together with further objects and advantages thereof, may best be understood by reference to the following description and accompanying drawings described below.

Figure 1 is an illustration ofthe installation of a ceiling fixture combining a fan and a light, and including manual controls, the ceiling fan being designed to be driven by an electronically commutated dc motor.

Figure 2 is a wiring diagram of the electronic circuitry providing electronic commutation of the fan motor and giving effecttothe manual controls. More specifically, Figure 2 is a wiring diagram of a printed circuit board, including the interconnections with the fan motor, the ceiling light, the manual controls and a custom integrated ci rcuit for motor control.

Figure 3 illustratesthe control and commutation waveforms ofthe motor control integrated circuit.

Figure 4 is a block diagram ofthe principal functional subdivisions or blocks ofthe motor control integrated circuit and thefunctional interconnections between said functional blocks. Figures 5A, 6, 7, 9, 1 OA and 1 1A are logic diagrams and/or circuit diagrams of the functional blocksforthe motor control integrated circuit.

Figure 5A is a logic diagram ofthe Input Gating and a circuit diagram including device parameters of the Integrating Transconductance Amplifier blocks of Figure 4. Figures 5B, 5C and 5D are simplified electrical circuit descriptions ofthe Integrating Transconduct anceAmplifier. Figure 5B illustrates a slightly extended and slightly simplified circuitofthe Integrating Transconductance Amplifier including the inputcon- nectionsto an exemplary winding stage and the nulling resistances also treatable as a partofthe Automull circuit;Figure 5C illustrates an equivalent circuit representation of the Integrating Transconduct anceAmplifier(withoutfeedback); and Figure 5D illustrates the equivalent circuit representation of the Amplifier employing series current feedback for stabilizing the amplifiertransconductance, a mode of feedback comparable to that herein employed.

Figure 6 is a logic diagram of the Comparator Network and ofthe Modulo 6 Counter blocks of Figure 4.

Figure 7 is a circuit diagram including device parameters in part and a logic diagram in part ofthe Autonull Circuit block of Figure 7.

Figure 8 is the output waveform of the Integrating Transconductance Amplifierfor a single commutation period. The waveform illustrates the time allocated between integration and reset of a capacitor used to time the commutation instant and the nulling of the Amplifier.

Figure 9 is a logic diagram ofthe Control Logic and Output Drivers blocks of Figure 4.

Figure 1 OA is a combined circuit and logic diagram of the oscillator, PulseWidth Modulator and the Forward/Reverse Logic blocks of Figure 4. Figure 10B are waveforms explanatory of operation of the Pulse Width Modulator block; Figure 10C is a plot ofthe effect of manual operation ofthewall control upon motor speed and direction of rotation; and Figure lOD is a simplified showing of a switchablewall control for motor speed and direction.

Figure 1 0E is a block diagram illustrating an open loop pulse width modulation motor control arrangement according to the invention.

Figure 1 OF is a detailed representation of one of the motor control waveforms in Figure 3.

Figure 1 1A is a circuit diagram including device parameters in part and a logic diagram in partforthe Power On Reset block of Figure 4; Figure 11 B is a graph illustrating the setting of the release voltage of the Power On Reset block.

Figu res 1 2A and 12B contain the principal internal waveforms incident to operation of the motor control integrating circuit. Figure 1 2A deals with commutation and balancing of the Integrating Amplifierfor an exemplary commuttion period; and Figure 1 2B deals with overall operation during the power on sequence.

COMBINED LAMPAND CEILING FAN MIXTURE US ING ELECTRONICALLY COMMUTATED DC MOTOR Referring nowto Figure 1, an installation of a combined lamp 100 and ceiling fan 101 fixture is shown, together with the appropriate manual controls. The fan motor, which is housed in housing 102, is, in this embodiment, an electronically commutated dc motor (ECM) driving the 4-bladed fan. Astationary assembly of the motor comprises a ferromagnetic stator having a multi-stage winding arrangement associated therewith which includes a plurality of stages, each in turn formed of a plurality of coils inserted into a plurality of slots spaced about a core of thestator. A rotatable assembly of the motor is arranged in selective magnetic coupling relation with the winding stages of the stator and comprises a rotor having a plurality of permanent magnet elements disposed thereon.

Although a specific ECM is illustrated herein for purposes of disclosure, it is contemplated that other types of ECMs having various other constructions and electrical characteristics may be utilized within the scope ofthe invention. For example, some of the ECMs which may be utilized are disclosed in U. S.

Patent Nos. 4,005,347 and 4,169,990 to David M.

Erdman, and U.S. Patent No. 4,1 62,435 to Floyd H.

Wright.

Theconnectionstothemotortraversea hollow shaft in the motor permitting a stationarytubeto carry wires between a conduit pipe 103, mounted on the upper surface ofthe motor housing 102 and a control box 1 supported upon the undersurface ofthe housing. The conduit pipe 103 may be used to carry wires to a connection box (not shown) mounted on the ceiling. The conduit pipe 103 may also supportthe fixture. The control box 104 contains the control circuitryforthe operation ofthe motor, including three manually operated controls. The lamp assembly 100 is supported on the undersurface ofthe control box 104.

The control circuitry is supported upon a circular printed circuit wiring board, fitted within the control box. The controls for the fixture include a three-way switch S2, operated by a pull chain, for mode selection, a forward-reverse slide switch S1, and a speed adjusting potentiometer R40. The mode selection switch permits four modes: fan on; lamp on; fan and lamp on; and fan and lamp off. The ceiling fixture is energized from a 115V ac main, connected in series with a wall mounted control 105 which also contains manual controls.

lntheexample,thewall control includes manual controls for both fan and motor. These also include an on and off switch forthefixture, a motor speed, forwardireverse control, and a lamp dimmer.

The control circuitryfor operation ofthe ceiling fixture is illustrated in Figure 2, which is awiring diagram ofthe Figure 1 installation. Figure 2 contains as its principal features, the lamp 100, the three winding stage motor 120,the wall control 105, the wiring mounted on the printed circuit board, which includes as five majorfeatures, a motor control integrated circuit 121,three principal solid state switches 122,123, 124 and afoursection, precision resistance voltage divider 125. In addition to these five principal features, the printed circuit board includes the circuit elements for supplying power to the lamp, the motor, the motor control IC, and the timing and the manual controls coupled to the integrated circuit.

Operation of the fixturetakes place in the following manner. The lamp receives power during "positive" half cycles ofthe ac main. Lamp (only) operation takes place when the three-way mode selection switch S2 is rotated to the lamp only position. Let it be further assumed that the wall control is "on" providing a low resistance bi-directional current path between its two external terminals.Assuming thatthe 11 5Vac main is energized, ac current follows a path from the first ac terminal 126,viathewall control 105, the demount able connector E4,the lamp 100, the demountable connector E2,the anodefirstandthe cathode second ofdiodeCR4,thedemountableconnectorEl,the switch S2, and finallythe second acterminal 127.

The motor and the IC receive powerduring "negative" half cycles ofthe ac main. Assuming that switch S2 is rotated to the motor only, or motor and fan on position, current from terminal 127 progresses via the switch S2, the connector E5, to a 150V dc power supply, consisting of a fuse F1,a current limiting resistance R22, a diode CR5, and a filter capacitor C1 connected between the cathode ofthe diode CR5, and the common ground connection of the supply.The transistorswitches 122,123, 124 each have a power inputterminal connected via a protective network (L1, CR12, CR13) to the 150+ volt bus ofthe supply originating atthe cathode of diode CR5, and a load terminal connected respectively via the connectors E6, E7 and E8to one end ofthe motorwinding stages A, B and C respectively. The other ends ofthe motor winding stages are connected to a neutral node 128, which is not an external connection point for motor energization.The switchesA, B and C, which are identical, operate with one switch (for instance A) conductive high, another (for instance B) conductive low, and the third switch (C) in a high impedance (non-conductive) state.In this instance, current flows from the 150V B+ bus via switch 122, connector E6 into the winding A, via the winding node 128 into winding B, into the connector E7, via switch 123 to the common ground. The common ground, also the negative terminal of filter capacitor C1 is returned via connector E4,and the wall control 105tothe other terminal 126 ofthe ac main. As has been indicated, power is supplied to the motor 120 and the motor control IC 121 only during the negative half cycle ofthe ac main because of unidirectional conduction by the diode CR5. Power is supplied to the lamp only during the positive half cycles of the ac main because of the unidirectional conduction ofthe diode CR4.

The motor control IC 121 receives its power (Vdd) at the output ofthe protective network (L1, CR12, CR13) via a voltage dropping resistor R23, a filter capacitor C2, and a voltage limitingzenerdiodeCRl,which is coupled to the pad P13. The IC ground (Vss) is returned via the pad P6 to the system ground, to which the capacitorC2, and the zener CR1 are also returned. The arrangement provides an approximately +9.0 volts Vdd potential for operating the IC. The IC is manufactured of silicon using a complementary (C) metal oxide semiconductor (MOS) process. The CMOS process readily produces P-channel field effect transistors (FETs), N-channel field effect transistors, single diodes, and resistances.

The control IC provides the appropriate output signalstocommutatethethreewinding stage motor 120, and affectuates control over the motor giving effect to the manual controls in the motor mounted control box 104 and in the wall control 105. The IC derivesthetiming information used for commutation from the individual winding stages ofthe motor, the non-energized winding being sensed for back emf, to define the instantfor commutation. The ends ofthe winding stages A, B and C, including the winding node 128, are connected respectively via the connectors E6, E7, E8 and E3, to one end terminal of each offour separate, precision, two resistor voltage dividers.The other end terminal of each divider is interconnected at node 129 and returned via two series connected, forward sensed diodes CR2 and CR3 to ground. The diodes are shunted by a filter capacitor C3. A resistance R28 connects the node 129 to the B+ output at CR5, C1.Thetaps on thefourvoltage dividers, which are set at a division ratio of 1 to 41, are coupled respectivelyto the input pads ofthe motor control IC labeled P5 (VA); P4 (VB); P3 (VC); and P2 (VN). The voltage division ratio is designed so thatthe voltage swing about neutral (VN) atthe IC inputs does not exceed the input capabilities ofthe motor control IC.

The foregoing configuration, which is used for sensing the back emf in the momentarily non-energized winding stage, allows the voltage on the neutral winding node 128, which ideally equals half the apparent B+ supply, and which is also divided down to 1 part of 41 to form a reference voltage (VN). The voltages VA, VB orVC referenced to the voltage (VN) form a suitable signal for application to the differential input ofthe IC.

For assured starting in the face of error in the Single In-line PLastic (SIP) resistance matrix 125, a discharge mechanism (092, R41 ) at P1 for capacitor C5 is provided, which still maintains an essential minimum time constant of 0.20 sec. The collector of 092 is connected to P1 ,the emitter via R41 (240 K) to system ground, and the base to node 129 so asto provide a 21/2,ua current drain at P1 The selection provides a starting period of 0.25 seconds and a margin for a 211a system error. The offset error in timing becomes negligible at medium and high rpms.

The switches 122, 123 and 124 are designed to respond to control signals supplied by the IC at the pads P7 (AT); P8 (AB); P9 (BB); PlO (BT); P11 (CT); and P12 (CB). The initial letters, A, B and C designate the winding stage ofthe motor 120. The second letter "T" denotes that "on" signals from the pads so designated onthe IC will produce switch conduction to the +150 volt bus (TforTop) in relation to system ground potential orto a point +75 volts in relation to the voltage on the neutral winding node 128. The second letter "B" denotes that "on" signals from the pads so designated on the IC will produce switch conduction to system ground (B for Bottom) orto a point -75 volts in relation to the voltage on the neutral node.

The circuit of the switch 122, which controls the A winding ofthe motor, is shown in Fig. 2. It comprises three bipolartransistors Q82, Q88, Q85, Q85,whichfunc- tion to couple the non-neutral terminal ofwinding A terminal to B+ when AT at P7 is high and a single FET 091, which functions to couple that winding terminal to system ground when AB at P8 is high. The switches represent a low cost design, with the base of the input NPN transistor Q82 being coupled to the pad P7, and the emitter connected via R37 to ground. The signal appearing atthe collector of Q82 is developed in the load resistor R31, serially coupled via the protective diode CR6 cathode first, anode second to the 1 50V B+ bus.A PNPtransistor 088, connected in the emitter common configuration, has its base connected to the collectorof082, its emitter coupled to the cathode of diode CR6. The collector of 088 is connected to the base ofthe NPN output transistor 085, and via a collector load resistance R34to the emitter of 085. The collector of 085 is connected via diode CR6 to the +150 volt bus. The emitter of Q85 is coupled via connector E6 to the A winding stage. Transistor Q88 serves to shift the level and provide the correct sense for driving the output transistor Q85. The diode CR9, which has its anode coupled to the emitter of Q85, and its cathode coupled to the B+ output at CR5, Cl, is a flyback diode, reducing the inverse switching transients.The Q82, Q88, 085 combination provides a low resistance, high current capacity connection of winding stage Ato the + 150V bus when the voltage AT at pad P7 goes to an active high.

The field effecttransistor 091 is an N-channel device, which couples winding stage Ato system ground. The gate of Q91 is coupled to pad P8, the source is connected to system ground, and the drain is connected to the emitter of 085, and via connector E6 to the non-neutral terminal ofwinding stage A.

Transistor Q91 provides a low resistance, high current capacity connection of winding stage Ato the system ground when the voltage AB at pad P8 goes to an "active" high. The high currents under discussion are those appropriate for a 50 watt fan motor.

The inductor L1, as a part of the protective network (L1,CR12, CR13), prevents the extremely high switching current peakswhich would stress the solid state power switches. In this application, the problem is more acute in the bottom rank FETs (091 in switch A, orthe counterparts of Q91 in switches B and C). These peak currents would ordinarily occur when selected upper rank bipolartransistor switches (085 in switch A, orthe counterparts of Q85 in switches B and C) are turned on, while the currentfrom the motor is flowing in the diode portion ofthe FET (drain-source connection).The recovery ofthis "diode" (structurallythe base-collectorjunction of a bipolartransistor inherent in the FET) determines this current and the "safe" recovery of the device.

The two serially connected diodes CR12 and CR13 shunt L1,sothatthevoltagetransientsappearing on the 150V bus will be clamped to the main filter capacitor Cl. Therefore, the B+ connection to these switches will not fly back significantly above the B+ voltage established by the filter capacitor. For the circuitto be effective, one ofthe diodes (e.g. CR12) should be a fast recovery diode. The protective circuit protects against the "shoot thru" current mentioned above, during PWM switching, which could otherwise result in dangerously high peak currents in both ranks of the transistor switches.

An alternative protective scheme for the lower rank FETs is to use two diodes, one connected between the drain and the system ground in shunt with the lower rank FET (e.g. Q91), the diode being poled to conduct when the FET is back-biased, and a second diode inserted in the drain poled to conduct when the FET is forward biased.

As the drawing ofthe switch implies, if both pads P8 and P7 are low, the switch A is in a high impedance state, or non-conductive state, with the non-neutral lead atthe winding stage A, now unenergized, free to reach whatevervalue is produced bythe back emf as thewinding stage A is subjected to the field produced bythe rotating permanent magnet rotor.

The sequence in which switching occurs is shown in the commutation waveforms of Figure 3. The waveforms available at the pads P7-P12 on the IC for control of the switches 122,123,124 are the six lowermost waveforms (AT, AB, BT, etc.), with those to the left representing FORWARD motor rotation and those to the right representing REVERSE motor rotation. The two waveforms denoted the "FOR"forforward or "REV" for reverse waveforms are internally generated on the IC, and are affected by the setting of SPDT S1, connected to the FOR/REV pad P16, and the wall control. With the IC in a Forward state, (FOR active high),the switching waveforms allow a first sequence from the left margin to the center ofthe drawing.

Should the forward signal go low and the reverse signal go high, the switching signals will resume a second sequence.

The Commutation OutputWaveforms orenergized winding selection signals, occur in a sequence of 6 waveforms (AT, AB, BT, BB, CT, CB) for energization of the winding stages A, B or C. The "highs" of each waveform (for purposes of initial discussion, the vertical markings under highs on the waveform, which denote duty cycled operation, are ignored.) have a duration of two counts ofthe least significant bit (BO) of a three-bit (BO, B1, B2) Modulo 6 Counter.

The motor, taken as a whole, has 6 distinctive energization states, in each of which one winding (A, B orC, e.g.A) is connected to B+, one remaining winding (B or C, e.g. B) is connected to ground, and the remaining winding (e.g. C) is not energized. < ach motor energization state lasts for one count of the least significant bit (BO) ofthe Modulo 6 Counter, and each motor energization state ends by definition at the commutation instant The commutation output waveforms, as will be described, are logically derived from the counts (B0, B1, B2) ofthreeflip-flops in the Modulo 6Counter which lead to six counter output states CS0, CS1, CS2, CS3, CS4, CS5, (the overlining denoting that the low is active).The counter output waveforms (CS0, etc.) are used to derive the commutation output waveforms and are unenergized winding selection signals used forselectingtheunenergizedwinding attheinputof the control lCforcommutationsensing.

The order of active lows ofthe CS0-CSS waveforms to the left ofthe margin ascend to the right (from CS0 to CS5 before reversal, and descend to the right (from CS5 to CS0) after reversal. The BB and CTwaveforms are undefined until the POR (power on reset) goes to an inactive high, releasing the counterfromthe CS0 state (B0=0; By =0; B2=0). At the next count, CS0 goes high and CS1 goes low, AB goes on, BB and BT are off, and CTcontinues on. Atthe next count, CS2 goes low,AB stays on, BTgoes on and CTand CB are off. The described sequence of winding energizations continue to the center ofthe figure until FOR goes low, at which the sequence reverses as illustrated.

The production ofthe correct sequence of switching waveforms to produce forward rotation, reverse rotation, orfaster or slower motor rotation, and to commutate the stator assembly at the correct angular position ofthe rotor isthefunction ofthe motor control IC 121, whose internal design will now be described.

MOTOR CONTROL IC 121 FOR ELECTRONICALLY COMMUTATED DC MOTOR The principal functional subdivisions of the motor control IC 121 are shown in Figure 4. The detailed logical and/orcircuitdesigns ofthefunctional blocks are shown in Figures 5A, 6, 7, 9, 1OAand 11A.

The control IC consists of 11 interconnected blocks 140to 150 interconnected to the circuitry on the printed circuit board by the 16 pads P1 to P1 6 as already noted. The rotational position ofthe rotor is "identified" bythe Modulo 6 or Commutation Counter 144, which has six states (CS0-CS5). The permanent magnet rotor, due to magnetic coupling rotates in synchronism with the rotation of the magnetic field produced by the stator assembly. Depending on the number of "poles" of the motor, the count may repeat once, twice, three times, fourtimes, etc. per revolution. The actual embodiment herein described employs a 6 pole permanent magnet rotor with an 18 coil, 3 winding stage, 36 "tooth" stator assembly.The 6 count is repeated three times per revolution.

The Modulo 6 Counter 144controlsthe sequential switching of the Output Drivers 146 for sequential energization of the winding stages, and forthe sequential enabling ofthe Input Gate 140forselecting the appropriate unenergizedwindingforcommuta- tion timing. The Counter is subjectto control for a forward or a reverse count by means ofthe Forward waveform (FOR) derived from the Forward/Reverse Logic 149. When power is first applied, the Counter is held in a preset state by means of the Power On Reset waveform (POR) derived from the Power On Reset Waveform 150.The commutation instant for the electronically commutated motor is defined by means ofthe positive going edge Reset 1 waveform supplied bythe Comparator Network 142 to the Counter 144.

The Reset 1 waveform "clocks" the Counter 144,thus defining the instantthat the energization stage of the rotorchanges and the instantthatthewinding stage being sensed for commutation timing is changed.

The Modulo 6 Counter 144 controls the energization sequence ofthe winding stages A, B and C by means ofthe Control Logic 145, the Output Drivers 146, and the switches 122,123 and 124. The output from the Counter 144 in the form of six NANDed combinations of adjacent counter states (CS0, CSl; 21 OCS1, CS2; etc.) and the least significant bit (B0) of the counter memory is coupled to the Control Logic 145. The Control Logic 145, decoding the outputs from Counter 144, derives high or low control signals for application to the six individual drivers, which make up the Output Drivers 146.

The Control Logic 145 is subjectto control for a forward or a reverse count by means of the FORWARD Waveform (FOR) and the REVERSE Waveform (REV) derived from the FORWARD/REVERSE Logic 149. It is also subjectto a control which inverts the sense ofthe driver output on alternate counts. This invention is achieved by means ofthe B0 waveform derived from the least significant bit ofthe Counter memory, and NORed with the RESET 1 waveform derived from the Comparator Network 142.The Control Logic, by means of the PWM Output Waveform derived from the Pulse Width Modulator 148, effects a pulse width modulation of a 20KHz oscillation from Oscillator147, which affects the conduction duty cycle of the output drivers in the manner indicated in the vertically lined areas of the driver waveforms (AT, AB, etc.) of Figure 3.

The Output Drivers 146 to which the waveforms (AT, AB, etc.) are applied provide signal gain atthe pads P7-P1 2 of the Motor Control IC adequate to drive the separate switching transistors in the solid state switches 122,123,124 on the printed circuit board. The output drivers 146 by means ofthe I start waveform derived from POR 150, deferthe actual application of powerto the motorwindings until 5 commutation intervals have taken place after power is initially turned on. This allows the commutation timing circuitryto stablilize before the actual application of powerto the windings.

The Modulo 6 Counter 144sequentially enables the Input Gating 140 for selecting the appropriate unenergized winding stage for connection to the Integrating Transconductance Amplifier 141 and Comparator Network 142 for commutation timing. In timing the commutation, the back emf developed in the unenergized winding stage (as a result of rotation ofthe permanent magnets on the rotor pastthe stationary, un-energized winding stage) once selected by the Input Gating 140, is amplified in the Amplifier 141, and integrated and measured in the Comparator Network 142 to determine the correct commutation angle. The selection of the appropriate unenergized winding stage by the Input Gating 140 is synchronized with the selection ofthe other two ofthe three winding stages by the Control Logic 145for energization.

The Input Gating 140 iscoupledvia pads P2-P5to the voltage divider matrix in the printed circuit board connected to the non-neutral terminals of each of the three motorstatorwinding stages (A, B, C) and to the neutral terminal for selection of the appropriate timing information. The Modulo 6 Counter controls the Input Gating 140 in identifying and selecting the stator winding stages which are unenergized, by providing the six counter output waveforms (CS0, CS1, etc.)totheenabling inputsoftheGating,which have an active lowwhen the Gating should be enabled.The output of the Input Gating is connected to the input ofthe Integrating Transconductance Amplifier 141,which has two differentially connected inputs. The Input Gating selects a single identified unenergized winding stage taking one input (e.g.VA) from the non-neutral terminal of the winding stage, and one input (e.g. VN) from the neutral winding node 126. The counter stages (CsO, etc.) are assigned to cause alternation of the sense ofthe connections between the non-neutral terminals of the winding stages and the Amplifier inputs on successive counts.

The alternation of the connection sense between the common neutral terminal and the Amplifier inputs is achieved by means ofthe least significant bit (BO) derived from the Counter memory.

This alternation bythe Input Gating 140 of the sense ofthe connection between the winding stages and the Integrating Amplifier 141 is necessaryto insure that the polarity of the Amplifier output is always the same.

The waveform ofthe backENFappearing on one winding stage has a first slope (e.g. positive) while the waveform of the next winding stageforthe next period of integration has an opposite slope. The inversions produced by the Input Gating thus keep the sense of the Amplifier output the same for successive integration periods.

The Input Gating 140 isthusthe input switching means ofthe ICwhich couples the back EMF wavefrom via the matrix 125 from the winding stage.

This waveform, which indicates the instantaneous angularvelocity of the rotor is next coupled to the blocks 141,142,143 for integration to obtain the angulartranslation ofthe rotor. These blocks, and more particularly the Comparator Network 142 (including C5), produce an output pulse, i.e. the Reset 1 pulse, atthe instantthe correct rotoranglefor commutation has been reached. The Reset 1 pulse is used to clockthe Modulo 6 Counter 144. The Reset 1 waveform is also coupled to disable the Input Gating during the nulling ofthe Amplifier 141 and during resetting ofthe integrating capacitor (C5), connected to the Comparator Network 142.

The Integrating Transconductance Amplifier 141 is a difference amplifier to the two inputs ofwhich the signal from the selected winding stage in the form of a voltage are differentially applied. The Integrating Transconductance Amplifier 141 converts the differentially applied input voltage to an output current which is integrated in the Comparator Netword 142 in determining the correct commutation angle. The output currentfrom the Amplifier is coupled to an integrating capacitor C5 coupled to pad P1. Capacitor C5, in storing the Amplifier output current, develops a voltage derived from the selected unenergized winding stage, which is an appropriate means of determining the instantaneous rotor angle.Thevoltage integral is a measure ofthe angular position ofthe rotorwhich is substantially independent ofthe rate of rotation of the rotor over a 10/1 range of rotational rates. The voltage appearing on the capacitor C5 as a result of integrating the Amplifier output current provides an accurate duplication ofthe voltage integral to the extent that the Amplifier output current is proportional to the differential inputvoltage and to the extentthata time integral ofthe Amplifier output current is equal to the time integral of the input voltage. The voltage integrated by the capacitor C5 is then compared with a standard voltage (Vref 3) corresponding to a known optimum rotor commutation angle to determine the instantthat commutation should take place.

The accuracy of this method of rotor angle determination depends on the stability ofthe transconductance ofthe Integrating TransconductanceAmplifier, and, sincetheAmplifier isa direct coupled difference amplifiersusceptibleto imbalance, it also depends on the accuracy with which any imbalance may be compensated.

The output of the Amplifier 141 is coupled to a ComparatorNetworkl42,which detectswhenthe voltage stored in the capacitor C5 as a result of current integration has equaled the standard voltage corresponding to the correct angular position of the rotorfor commutation. When equality is sensed, the Comparator Network signals (RESET 1), the commutation instantto the Modulo 6 Counter 144.Upon this signal, the Counter advancesto the next count, and the Input Gating 140 and Output Drivers 146 are advanced to implementthe commutation and commence the energization, de-energization and voltage sensing for the three winding stages appropriate to the next count Thethird blockactive in commutation timing isthe Autonull Circuit 143, which provides an offset to correctanyimbalance in output current ofthe Integrating Amplifier. "Nulling" of the Integrating Amplifier occurs on each commutation.As illustrated in Figure8,nullingtakesplaceafterthecapacitor integration period has ended, signaled by the RESET 1 pulse, but before the timing capacito r C5) is reset (during RESET 2) preparatory to the next capacitor integration period. The Amplifier 141 is placed in a condition to be nulled, and then causes reset ofthe integrating capacitor by the application ofthe RESET 1 and RESET2 waveforms, respectively. The RESET 1 waveform shorts the differential input ofthe Amplifier, and thus provides a zero differential input signal essential to nulling.The Reset 2 waveform is active after nulling, and sets the amplifier output into a state in which the integrating capacitor (C5) is rapidly rechargedtowardVdd.lnaddition,during nulling, certain controls are applied to the resistances R3A-D and R4A-D, which for certain purposes, form a portion ofthe Amplifier. These will be discussed in connection with the Autonull Circuit.

The nulling oftheAmplifier 141 produces a periodically verified current offset which is applied to one amplifier channel to nulltheamplifieroutputcurrent for a zero input signal. The Autonull Circuit 143 produces this offset current in small (3/4 pA) incre ments which are applied to a current offset one channel ofthe amplifier. The increments are designed to raise or lower the currenttransfer ratio of a mirror in one channel oftheAmplifierto bring the output current ofthat channel into balance with the output currentofthe otherchannel.The nulling takes a small time,typicallylessthan a millisecond,butnot exceeding a maximum of 1.4 milliseconds.After nulling, the timing capacitor C5 is reset (during RESET 2), which takes 3-5 milliseconds, to prepare for the next capacitor integration period to time the next commutation. It is also necessary to provide this time delay after commutation has taken place to assure that all of the stored energy in the now unenergized winding (which was energized priorto commutation) has time to dissipate. This is necessary to assure that stored energy is not incorrectly interpreted as backemf causing a large errorinthe commutation instant.

The Autonull Circuit 143 and its relationship to the otherfunctional blocks will be described in detail below.

The remaining blocks in the control IC deal primarily with implementing the manual control functions.

When the ceiling fixture is turned on, and power is to be applied to the fan motor, the "Power On Reset" (POR) is active.

The POR 150 is a protection circuitfor other portions of the ECM control circuitwhich becomes active when power is turned on orturned off. It insures that the protected circuitry is held in a desired sage inactive state when the supply voltage on the protected circuit is belowafirstvalue when power is turned on, or below a second value (usually slightly lower) when power is turned off. When power is turned on, it releases the protected circuit in a desired initial state.

The interaction ofthe POR with otherfunctional divisions ofthe Motor Control IC is in part illustrated in the waveforms of Figure 3 and Figure 12B.

In consequence ofthe appearance of the active output ofthe POR when power is turned on, the Amplifier 141 is disconnected from capacitor C5, and the Comparator Network 142 and theAutonull Circuit 143 are preset. This produces an initial state, akin to the occurrence of a commutation instant in preparation for nulling the amplifier. The POR presets the 3 bit memory of the Commutation Counter 1 44 in an initial (000) state. It presets the Forward/Reverse Logic to the state set in by the switch S1 on the printed circuit board. The presetting occurs immediately after power has been applied to the POR and last until Vdd is high enough (e.g. 7.0 volts) to insurethattheanalog and logic circuitry is valid.

When the active POR output terminates, the autonull circuit is released for nulling, insuring thatthe Amplifier is nulled before it is used for integration timing. Afterthis,the POR 150, now acting by means ofthe IST waveform coupled to the Autonull Circuit, influences starting forfive artifical counts ofthe Commutation Counter 144 by introducing an offset current in the resistance network of the Amplifier 141, which facilitates discharge ofthe integrating capacitor C5 to the voltage set to mark the commutation instant and nulling.Forthe same 5 count period, the POR, acting by means ofthe I start waveform, turns offthe "bottom" switches of the output drivers, precluding the coupling of energy to the winding stages ofthe motor until the Amplifier 141, Comparator Network 142 and the Autonull Circuit 143 have stabilized.

The Forward/Reverse Logic 149 is responsive to the setting ofthe switch S1 coupled to the pad P1 6 on the IC. It is also responsive to a controlled diminution in the B+ supply effected by the operation ofthe wall control to reducethe B+ voltage belowthe desired threshold. In addition, when power is reapplied, after having been turned off, the POR 150 circuit presets the Forward/Reverse Logic to the state that corresponds to the setting of switch S1. A change in the outputfrom 149 which causesthe Forward waveform to go to an active High from a prior Low, and the Reverse waveform to go to an inactive Lowfrom a prior High, orviceversa, produces a reversal in the direction of rotation ofthe motor. These waveforms, which are illustrated in Figure 3, are the means bywhich a reversal in motor rotation is achieved. The Forward waveform is coupled to the Commutation Counter 144 to effect both a forward and a reverse count. The Forward and Reverse waveforms are coupled to the control logicforenabling the Forward gates (U42-U47) or the Reverse gates (U36-U41 ). The Forward or Reverse waveform is also coupled to the POR for decoding the five count interval for simulated com mutation. When the Forward/Reverse Logic is in a Forward state, the POR is enabled to count forward to the CS5 state, and when the Forward/Reverse Logic is in a Reverse state, the POR is enabled to count "backwards" to the CS0 state, both of which provide the required delay.

Control ofthe Forward or Reverse state ofthe Logic 149 is achieved through operation of the wall control 105. If reversal is desired, the motor speed control is moved in the direction of reducing speed pastthe point at which the motor will stall. The effect of so moving this control isto reduce the B+ below a threshold. This in turn is sensed on the regulate pad (p1 4) via the action of transistor 081, thus raising the regulate voltage above the peak sawtooth voltage.

This is sensed in the Logic and used to cause a reversal in the state of the Forward/Reverse setting. The sensing is achieved by comparing the B+ using circuitry on the printed circuit board including Q81, R25, R26, R27, R29 and R30, with a Zener stabilized voltage reference, also on the printed circuit board, but divided down on the Motor Control IC 121. The Logic includes a comparator which compares a voltage proportional to the B+ voltage with a voltage proportional to the Zener voltage, and includes a circuit on the IC for introducing hysteresis in the threshold to make the switching action positive.

Finally, the Forward/Reverse Logic is provided with a delay based on the use of a 20KHz pulse for the Oscillator 147, in the actual changeover from forward to reverse operation. The Clock waveform CLK is coupled to the Forward/Reverse Logic to effect this delay.

The Oscillator 147 and the Pulse Width Modulator 148 enter into the regulation of the speed. The motor is designed to run at a speed established by the amount of electrical power supplied to the motor and the amount of mechanical power required to rotate the fan and drive the air impinging on its blades. When greater power is supplied, the rate of rotation increases, and when lesser power is supplied, the rate of rotation decreases. The speed is thus controlled bythe amountofpowersupplied, and that power is subject to a continous control. The commutation is designed to be at the correct angle irrespective ofthe speed of rotation and is not intentionally varied with adjustment ofthe speed.

The oscillator 147 and Pulse Width Modulator 148 providethe means for adjusting the powersuppliedto the motor over a range of substantially all offto all on.

In practice, the arrangement permits the motor to operate over a 20 to 1 range of speeds. As earlier explained, the motor is energized by simultaneous energization of two serially connected winding stages.

Should only one winding stage be energized as when the I start waveform is applied, the motor receives no electrical energy.

The control of the motor speed is exerted by pulse width modulating one of the two switches which are enabled at each count of the counter. This is best seen from an examination of Figure 3. The waveforms derived by the output drivers (AT, AB, etc.) and coupled to the output of pads P7-P12 illustrate these properties. Each waveform (AT, AB, etc.) has an active high oftwo counts duration with the same two highs being on simultaneously for only a single count. In addition to the two highs that are on, one is always shown with the vertical lines indicative of pulse width modulation. Thus, by pulse width modulating one of the two active switches, pulse width modulation occurs at all times.In addition, dueto the classic nature of the pulse width modulation, the one time of the pulsewidth modulated waveform mayvaryfrom 0 to 100% which thus provides a full range of power control.

The Oscillator 147 is a relaxation oscillatorwhose principal circuitry is onthe IC butwhich has an external capacitor C6 and a resistance R24 mounted on the printed circuit board and connected to the IC at pad 15. The internal oscillator waveform is a unidirectional pulse having an approximately 20 KHz repetition rate with an on time of 300 nanoseconds for the narrower portion of the pulse. The CLK output of the oscillator derived from a flip-flop (U94-U91 is coupled to the Forward/Reverse Logic 149, as earlier noted, for effecting a delay when the direction of motor rotation is changed equal to at least one pulse width interval. The inverse of the oscillatorwaveform CLK is coupled to theAutonull Circuit 143 where it controls the incrementing rate in the nulling process.

The output of the Oscillator 147 is modulated by the Pulse Width Modulator 148. The components ofthe PulseWidth Modulatorare in parton the integrated circuit and in part on the printed circuit board being interconnected bymeans ofthe pad P14(REG).The external components are largely shared with the Forward/Reverse Logic. they include the potentiometer R40,the resistances R25, R26, R27, R29, R30, and capacitor C4.

The Pulse Width Modulator is a classical modulator which provides an output which in the limiting cases is on all of the time or off all of the time, and in intermediate cases is on part ofthe time and off partof the time, as illustrated in Figure 1 OB. The output of the PulseWidth Modulator (PWM out) is coupled to the Control Logic 145 by means of which it introduces a pulse width modulation into the switching waveforms in either of the forward bank (U42-U47) or the reverse bank (U36-U41) of gates.

TheAutonull Circuit 143 nulls the Integrating Transconductance Amplifier to remove any error in timing ofthe commutation instant attributable to Amplifier input offset and to improve motor starting performance. The Autonull Circuit is located entirely on the Integrated Circuit and requires no pads for external connection.

The Autonull Circuit includes two digitally subdivided resistive elements R3A-D and R4A-D, which are the resistive elements in a current mirror in one ofthe two channels ofthe Amplifier 141 following the differential input stage. The current mirror is modified bythe inclusion of means for introducing an offset current which may be digitally stepped in 3/41lA increments on eitherthe input or output side of the current mirror, and which in effect brings one channel ofthe Amplifier into balance with the other. The incrementing occurs underthe control of a 5 bit counter, which counts at the 20KHz rate of the Oscillator 147 (CLK). In the nulling process, the 5 bit counter is preset to a maximum offset current condition and is then decremented atthe clock rate until a balance is detected.When the balance is detected, the counter stops and the offset current is maintained until nulling is again instituted.

The Autonulling Circuit functions once for each commutation. The waveforms that are involved in nulling for normal operation are illustrated in Figure 12A. The nulling period starts afterthe Comparator Network 142 (COM 2, U80, D16 Q) has signalled the commutation instant (see Figure 9), causing the RESET 1 waveform to go high (D16 Q). When the RESET 1 waveform goes high, the inputto the Integrating Amplifier 140 is referenced to a voltage reference (Vref 1 ) suitable for nulling andthedifferen- tial amplifier inputs are shorted together. Atthe same timethe Null Clockwaveform is generated bythe Comparator Network 142 (D17 O).This waveform is coupled to a 5 bit counter in theAutonull Circuit (D8, Do 2) which forces the Autonull Circuit into a PRESET condition in which the maximum offset current, earlier mentioned, is injected into the Amplifier 141. At substantiallythe same time, the Autonull Circuit generates the Null Output waveform (D7,0) which is coupled to atransmission gate U85) at the inputtothe Comparator Network 142. This disconnects theAmpli- fierfrom the external integrating capacitor (C5), leaving the Amplifier output connected only to third comparator (COM 3) in the Comparator Network.The input conditions cause the Amplifier output voltage to climb past the threshold Vref 2 ofthe third comparator (COM 3) causing the Null Setwaveform originating at COM 3 U81 to go low. This waveform, when coupled back to the Autonul I Circuit, releases the PRESETS on the counter, and allows the counterto decrement at the clock rate. Decrementing is accompanied by a stepped reduction in the offset current applied to the Integrating Amplifier. When the comparator COM 3 senses that the voltage atthe output of the Amplifier, which had been nearVdd changes in direction, signalling the null, the Null Setwaveform goes high.

On the following clock pulse the Null Output (D7 0) waveform goes low. The Null Outputwaveform (D7 Q) is coupled to the Comparator Network which generates the RESET 2 waveform, which converts the Amplifier 141 into a maximum current supply state. At the same time the Null Output waveform operates the transmission gate U85to reconnectthe Integrating Amplifierto the integrating capacitor C5. When the uppervoltage reference (Vref 4) is crossed, both RESET 1 and RESET 2 terminate and the next capacitor integration period commences.

During start conditions the Autonull sequence is affected by the Power On Reset 150. The Power On sequence is illustrated in the waveforms of Figure 1 2B.

When power is first applied,the POR waveform is in an active lowwhich causes the Null Clockwaveform (D17 Q) to go high. This causes the Autonull counterto be preset in a high offset current condition. When the PORwaveform goes to an inactive high subsequently, the Null Clockwaveform falls, allowing the counter in the Autonull Circuitto decrement. The autonulling is further affected by the application of an offset current IST which is interrupted during nulling, but active during capacitor resetting and integration. The offset current 1ST adds to the discharge current of the Integrating Amplifier and causes the integrating capacitor to discharge more rapidly and more positivelytoward the threshold of comparator COM 2.

Underthe influence of the logic contained in the POR block, the IST cu rrent continues until 5 autonull sequences are completed. During the same 5 count sequence,the lowerdrivers BOBA-C are also disabled so that no power is applied to the motorwindings. On the sixth count, the ISTand I Start highs are terminated, the motorwindings are energized and autonulling continues in the normal manner.

THE INPUT GATING 140 The Input Gating 140 is the input switching means of the Control IC 121 which selectsthecorrectunenergized motor winding stage for determination of the next commutation instant. The Input Gating 140 is coupled to the pads P5, P4, P3 and P2, respectively designed for connection via thefoursection voltage divider 125 to the VA, VB, VC and VN motorwinding terminals earlier identified. The voltage divider 125 is the means immediately connected to the winding stages for deriving voltages proportional (1/41) to the voltages induced in the winding stages reduced to valuessuitableforapplication ofthelC.

The Input Gating 140 couples the outputvoltage from the selected winding stage to the input terminals 150,151 of the Integrating Transconductance Amplifier 141 in the correct sense to keep the correct Amplifier output polarity over successive commutation periods. The Input Gating consists of eight bidirectional transmission gates U58, U60, U62, U64, U66, U68, U70 and U72, each associated with an inverter U57, U59, U61, U63, U65, U67, U69 and U71, respectively, three gates U54, U55 and U56 used to control the sense of the selection ofthe Neutral (N), and six gates U73-U78 used to control the sense of selection of the three non-neutral winding stage terminals (A, B, C). The output voltage from the selected winding is coupled between the input terminals 150, 151 ofthe Integrating Transconductance Amplifier 141.The control signals for operating the input gates are derived from the Comparator Network (RESET 1) and the Modulo 6 Counter 144 (B0, CS0-S).

The Input Gating 140 is connected as follows. The transmission gates are bidirectional conductive devices, each consisting of two complementary field effect transistors connected in parallel between the signal inputterminal and the signal outputterminal.

Each transmission gate hastwo control terminals requiring oppositely sensed control voltages. In the illustrated configurations, a signal is coupled directly to one control terminal, and through an inverter to the other control terminal, so that there is in fact only a single control connection assigned to each gate. The transmission gates are enabled with a high control signal, and not enabled with a low control signal. The signal input terminals to the gates U58 and U60 are coupledtothe pad P2 for application of the VN voltage. The output terminal ofthe gate U60 is connected to the input terminal 150 of the Integrating Transconductance Amplifier, while the signal output terminal ofthe gate U58 is connected to the input terminal 151 of the Integrating Transconductance Amplifier. Similarly, the signal input terminals ofthe gates U62 and U64 are connected to pad P5 for application oftheVAvoltage.Thesignal output terminal ofthe gate U64 is connected to the amplifier inputterminal 150, while the signal output ofthe gate U62 is connected to the amplifier inputterminal 151.

The signal inputterminals ofthe gates U66 and U68 are connected to the pad P4for application ofthe VB voltage. The signal outputterminal ofthe gate U68 is connected to the amplifier input terminal 150. The signal output terminal ofthe gate U66 is connected to the amplifier inputterminal 151. The signal input terminals ofthe gates U70 and U72 are connected to the pad P3forapplication ofthe VC voltage. The signal outputterminal ofthe gate U72 is connected to the Amplifier inputterminal 150. The signal output terminal ofthe gate U70 is connected to the amplifier inputterminal 151.

As already indicated, each transmission gate has an associated inverter, which inverts the applicable control signal. The uninverted control signal for each transmission gate is directly coupled via the associated invertertothe other control inputofthe transmission gate. The inverter U54 amd two input NOR gates U55 and U56 are connected to the control inputs oftransmission gates U60 and U58. The control signals for these gates are the RESET 1 waveform derived from D1 Q ofthe Comparator Network 142, and the least significant bit (BO), from the flip-flop Dl O ofthe Modulo 6 Counter 144. The RESET 1 pulse is coupled to one input of NOR gate U55 and to one input or NOR gate U56.The least significant bit (BO) from the Modulo 6 Counter is directly coupled to one input ofthe NOR gate U56, and indirectly coupled via the inverter U54 (whose input is connected to D1 O) to the other input of NOR gate U55. The two input NOR gates U73to U78 each have one input coupled to D16 Qfor application ofthe RESET 1 pulse, and one input coupled respectively to the Counter 144 for application of the CS5-CS0 waveforms. The outputs of the NOR gates U55, U56 and U78 to U73 are connected to the control inputs of the transmission gates U58, U60, U62, U66, U68, U70 and U72, respectively.

The Input gating 140 is designed to sense the voltage ofthe selected winding during the capacitor integration period, when the RESET 1 waveform is low (see Figure 8). Thus, each NOR gate (U55, U56, U73-U78), which has one input coupled to Do 6 for application ofthe RESET 1 waveform, inhibits all eight transmission gates (U58, U60, U62, U64, U66, U68, U70, U72) when the RESET1 waveform ishigh.When the RESET 1 waveform is low, however, corresponding to the capacitor integration period, the NOR gates may be selectively energized in accordance with the state of the Modulo 6 Counter.

The transmission gates ofthe Input Gating are arranged to successively invert the polarity of the signal coupled from the motorwinding stage to the input terminals 150,151 ofthe Integrating Amplifier 141. Assuming that the counter is in the CS0 state (and thatthe RESET 1 waveform is low), CS0 is low, the output of gate U78 is high, enabling transmission gate U62, which couples VA at pad P5 to terminal 151. At the CS0 state, the least significant bit is also low. NOR gate U56, with two lows at the input, has a high at the output, enabling transmission gate U60 to coupled VN at pad P2 to terminal 150. Atthe next count, the CS1 state, the output of U75 is high, enabling U68, and coupling VB at pad P4toterminal 150.The least significant bit is now high, and NOR gate U55, with two lows at the input, has a high atthe output, enabling transmission gate U58 to couple VN at pad P2to terminal 151. Similarly, atthe next cou nt, the CS2 state,the outputof U74 is high, enabling U70, and coupling VC at pad P3 to terminal 151. The least significant bit is now low, and the output of U56 is high, enabling U60, and coupling VN at pad P2 to terminal 150.Each succeeding countforthe states (CS3, CS4, CS5, CS0, etc.) which follows, connects an unenergized winding to the input of the Integrated Amplifier, and does so in a polarity which is opposite to that ofthe preceding connection (i.e., with neutral connection to terminal 150 on even counts, and to terminal 151 on odd counts).

Figure 3 illustrates the winding stage selection which is made bythe input gating as a function of the counter states. During CS0, both winding stages B and C are energized; therefore winding stage A, which is unenergized is sensed via gate U62. During CS1, both winding states A and C are energized; therefore winding stage B is sensed via gate U68. During CS2, both winding stages A and B are energized; therefore winding stage C is sensed via gate U70. During CS3, winding states B and C are energized; therefore winding stage A is sensed via transmission gate U64.

During CS5,winding stagesAand Bare energized; therefore winding stage C is sensed via gate U72.

INTEGRATING TRANSCONDUCTANCEAMPLIFIER 141 The Integrating Transconductance Amplifier is illustrated in Figures 5A, 5B, 5C and 5D. Figure 5A illustrates all the active circuit elements of the amplifier less the resistances in the amplifier current sink into which offset currents are introduced to null the amplifier. Figures 5B, 5C and 5D are provided to explain the operation of the Transconductance Amplifier, emphasizing those measuresfor stabilizing the amplifiertransconductance. The current sink resistances (R3, R4) are made a part of the Figure 5B illustration without the offsetting means used for nulling the amplifier.In addition, to complete the Transconductance Amplifier, the connections VA and VN to a representative motorfield winding stage (A), are shown coupled via two appropriate pairs of voltage dividing resistors, and via two transmission gates to the inputs 150,151 oftheTransconductance Amplifier. The grounding circuit to the divider network including diodes CR2, CR3 and capacitor C3 are also shown in Figure 5B.

As shown primarily in Figure 5A, the Integrating Transconductance Amplifier consists ofthe transis tors Q1 to 01 1 ; 016, 017; Q18 and Q23 to 029 and the resistances R1 to R8. The Amplifier consists essentially of a differential input stage (01,02, Q3. 04, Q5, Q6) a first current mirror (Q10, 01 coupled to one output (Q5) of the differential input stage; a second current mirror (Q1 6, 017) coupled to the other output (Q6) of the differential input stage; a common gate buffer Q24 coupling the output of the first current mirror to a high output impedance inverting current mirror Q26-Q29; and a common gate buffer Q25 coupled to the output ofthe second current mirror.The input signal is coupled to the positive (150) and negative (151) input terminals ofthe differential input stage (Q5, 06), where the positive input is defined to be the one which drives the upper output device (Q27) and the negative input drives the lower output device (Q25). The output of the inverting current mirror (026-029) appears at the drain ofthe transistor Q27 and the output ofthe buffer 025 appears at the drain of 025. The drains of push-pull connected transistors 027,025 form the output terminal 152 ofthe Integrating Transconduct ance Amplifier.

Thefivetransistors 07, 08, Q9, Q18 and 023 control the IntegratingAmplifierduring nulling and capacitor reset. The transistors 07 and 08 provide a means for shorting outthe differential inputto the Integrating Amplifierduring nulling and reset of the capacitor C5.

They become operative during the Reset 1 pulse. The transistors Q9, Q18 and Q23 arethe meansforcausing rapid reset ofthe capacitor C5 after nulling is complete. During the Reset 2 pulse, transistor 09 disables the current sink 010,011; 018 disables the current sink 016, Q17; while Q23 enables the upper current mirror 026-Q29 to supplythe desired charging currentvia Q27.

The input differential amplifierstage oftheTransconductance Amplifier consists of the differentially connected P-channel transistors Q5 and 06. The input signal atthe positive terminal 150 is coupled to the gate of 05, and atthe negative inputterminal 151 is coupled to the gate of 06. The source of OS is connected via a degenerating 2000D resistance R1 to the drain ofP-channel transistor 04forthe supply of cu rrentto 05. The source of 06 is connected via a degenerating 2000O resistance R2 to the drain of Q4 forthe supply ofcurrentto 06.The resistances R1 and R2 provide current series feedback as symbolized in Figure 5D for stabilizing the AmplifierTransconductance.

The transistors 01,02,03,04 supply a fixed current (typically 250iA) to the sources oftransistors OS and 06. Serially connected N-channel transistor 01 and P-channel transistor02 are current references establishing the output current of the current source. The transistor Q2 has its source connected to Vdd, and its drain connected to the drain oftransistor O1.The drain and gate of Q2 are connected together. The source of 01 is connected to the IC ground and the gate of 01 is connected to Vdd to establish conduction in the series connected 01,02 transistor pair. The geometry selection 200/4 gate (gate width to gate length) for 02 and 414 four 01 establishes a current of typically 2501lA in Q1 and Q2.The output P-channel transistor Q3 of the current mirror, which has its source connected to Vdd, has its gate connected to the gate of 02.

Transistor 03, which has similar geometry (200/4) to Q2, is held at a gate to source voltage equal to that of 02, and tendsto "mirror" an outputcurrent equal to the current in the reference at its drain. The drain of Q3 is coupled to the source of current source buffer P-channel transistor Q4. Transistor Q4 is of large design (500/4) to obtain a lowdrain to source saturation voltage, and has its gate coupled to a 5.8V reference (formed of a plurality of series connected transistors) setto establish conduction in 04.The current output ofthe current source (01-04) appears at the drain of buffer transistor 04, which is coupled, as already noted, to supply current (250pA) to the transistors OS and 06 of the differential input stage.

The signal voltage coupled between the gates of OS and Q6producestwo output signal currentsatthe drains of Q5 and Q6, respectively. As earlier defined, the gate of Q5 may be regarded as the inputto the positive "channel" oftheTransconductance Amplifier since it controls the conduction of outputtransistor 027. Conduction of 027, which is the upper member ofthe push-pull output pair, "supplies" currentfrom the positive (Vdd) supplytothe load. Forsimilar reasons the gate of Q6 may be regarded as the inputto the negative channel ofthe amplifier, since it controls the conduction of Q25, which "withdraws" current from the load toward (Vss) at IC ground.

The signal current appearing atthe drain of OS is coupledto the drain of N-channel transistor 01 0, the input current reference of the first current mirror (010, Q11) in the positive channel. The source of 010 is connected through a tapped 2000 ohm resistance R3 (best shown in Figure 7) to the IC ground. The gate of 010 is coupled to the drain oftransistor 010. The configuration tends to establish a series current bias of approximately 125,uAin Q10 (half ofthe Q output current) and in Q5. The gate of 010 is coupled to the gate of the mirror output N-channel transistor Q11, whose source is connected through a tapped 2000 ohm resistance R4 (best shown in Figure 7) to the IC ground.The appearance of a signal current in 010 produces a nearly equal mirrored signal output current in the mirror outputtransistor 011. The currenttransferaccuracyofthe mirror is in part due the magnitude ofthe degenerating resistances R3 and R4.

The signal currentappearing atthe drain of Q6 is coupled to the drain ofthe N-channel transistor 016, the input current reference ofthe second current mirror in the negative channel. The source of 016 its connected through a 2000Q resistance RSto the IC ground. The gate of Q16 is connected to the drain of Q16. The configuration tends to establish a series current bias of approximately 125us in 016 (half of the 04 current) and in Q6. The gate of Q16 is coupled to the gate of the mirror output N-channel transistor 017, whose source is connected through a 2000 ohm resistance R5 to the IC ground.The appearance of a signalcurrentin Ol6producesa nearlyequal mirrored signal output current in the mirror outputtransistor Q1 7. The currenttransfer accuracy of the mirror is in part due to the magnitude ofthe degenerating resistances R5and R6.

The output current appearing atthedrain of transistor 011 in the first current mirror in the positive channel is connected to the source ofthe large geometry (500/4) N-channel buffer transistor Q24. The gate of Q24 is returned to a 3.2 volt reference voltage supply. The output current of buffer transistor Q24 is coupled from the drain of Q24 to the input of the polarity inverting current mirror Q26-Q29 from which a part ofthe amplifier output is derived. The common gate configuration of 024 accurately preserves a unity currenttransfer ratio between the source of 024, which is held to equality with the output current ofthe first current mirror Q11 and the current at the drain of Q24 into which the currentfrom the polarity inverting current mirror is drawn.

The output current appearing atthe drain of the transistor 017 in the second current mirror in the negative channel is connected to the source of the large geometry (500/4) N-channel buffer and output transistor 025. The gate of 025 is returned to the 3.2 volt reference voltage supply shared with the gate of Q24. The output current of buffertransistor 025 enters the drain of 025 from the Integrating Amplifier output terminal 152. The common gate configuration of Q25 accurately preserves a unity current transfer ratio between the source of 025,which is held to equality with the output current ofthe second current mirror Q17, and the current atthe drain of 025, connected to the output terminal 152 ofthe Integrating Amplifier.

The output current appearing atthe drain of the buffer transistor 024 in the positive channel is coupled to the input of the modifiedWilson current mirror employing transistors 026 to Q29. These transistors are all P-channel devices of 200/4 geometry. The mirror, which has a currenttransfer ratio very closely approximating unity, inverts the signal current direction, and exhibits a high output impedance. The drain of Q24 is connected to the gate ofthe P-channel transistor 027 whose drain is connected to the amplifier output terminal 152. The drain of 024 is also connected to the gate ofthe P-channel transistor Q26, whose gate and drain are joined. The transistor 027 is serially connected with the P-channel transistor 029.

The source of Q27 is connected to the drain of Q29, with the source of Q29 being connected via the 3000Q resistance R8to the Vdd supply, and the gate and drain of 029 being joined. By these connections the current in Q29 is forced into equality with the current in 027.

Continuing, P-channel transistor Q28 has its gate connected to the gate of Q29, and its source connected via the 3000Q resistance R7to the Vdd supply. By these connections Q28 tends to mirror the current in Q29. The mirror is completed bytheconnection ofthe drain of Q28to the source of 026. The serial connection of Q24, 026, and 028 forces the current in all three transistors into equality with the positive channel signal current in Q24. The result of the foregoing fourtransistor configuration is to transfer the positive channel signal currentfrom the drain of 024 in inverse polarity to transistor 027, where it is of polarity to supply current from Vdd to the output terminal 152.

The Transconductance Amplifier output stage may also be regarded as two current sources (Q26-029; and Q16, Q17, 025) in push-pull with outputtransistor 027 tending to supply currentto the outputterminal from a source at Vdd potential, and the output transistor 025 tending to withdraw current from the outputterminal of the IC ground. The consequence of the serial connection of two current sources is that the outputvoltage is not defined until a currentexchanging load has been connected to the Amplifier output terminal.In the eventthatthe circuit load is the gate of an FET, which draws negligible current, any slight asymmetry in current gain or dc imbalance between positive and negative channels will force the output potential toward eitherthe Vdd or Vss determined limits. If the load is of relatively low impedance in relation to the output impedance of the Amplifier, such as a relatively "large" capacitor operating with a relatively "short" time constant, and further assuming that the input impedance oftheAmplifier is large relative to the source impedance (which is true for FETs), then the Transconductance Amplifier is operated in the natural mode, and the output current closely equals the input voltage timesthe design transconductance ofthe Amplifier.Further, we may assume that the differential input stage, and the three current mirrors have a high dependency on processed resistances rather than on Gm dependent parameters alone for defining the Gm ofthe initial stage and for maintaining equality in the current ratios ofthe subsequent current mirrors. The uncertainty in amplifier Gm may be reduced by a factor greaterthen two using the indicated parameters. These measures on the IC have provided an accurate amplifier Gm, avoiding the need for compensation external to the integrated circuit.

Matched pairs of resistors used in the Amplifier mirrors are implemented using interdigitated polysili contunnelswhich are readily available on the conventional gate array. These tunnels are located in a column between the input/output cells and the body of the array. In a custom IC design, these resistances would be produced using polysilicon in an interdigitated configuration. This process improves the ratio matching of the individual resistances and improves the accuracy of the current mirror.

Means are also provided on the IC for offsetting any imbalance between the positive and negative channels of the Transconductance Amplifier (i.e. the Autonull Circuit 143).

The five transistors Q7, 08, 09, 018 and Q23 earlier mentioned control the Integrating Amplifier during nulling and reset of the capacitor C5. The transistors 07 and Q8 are two N-channel devices of 100/4 geometry having their drains connected, respectively, to the amplifier input terminals 151 and 150, and their sources connected together to a 3 volt voltage reference (Vref 1). The gates of 07 and Q8 are connected together for application ofthe Reset 1 waveform available from the Comparator Network (D16 Q). They short outthe differential input, and maintain both channels at a normal level of conduction, when the Reset 1 pulse is high for nulling the Amplifier, and for facilitating reset ofthe capacitor C5.

The transistors 09, 018 and 023 are designed to create a high outputcurrentduringresetofthe ca pacitor C5, underthe control of the Reset 2 waveform.The tra nsistors Q9 and Q18 are two N-channel devices of 200/4 geometry. Transistor Q9 has its drain connected to the gates of the transistors 010,011 in the first current mirror and its source connected to the IC ground. Transistor 018 has its drain connected to the gates ofthetransistors 016 and 017 in the second current mirrorand its source connected to the IC ground. The transistor Q23 is an N-channel device of 4/10 geometry having its drain connected to the gates ofthetransistors Q26 and Q27 ofthe inverting current mirror, and its source connected to the IC ground. The gates of transistors 09, Q18 and Q23 are connected togetherfor application of the Reset 2 waveform available from the Comparator Network. When transistors Q9 and 018 are conductive as by application of the Reset 2 waveform, the gates of the current mirrors 010,011 and 016, Q17 are held at near IC ground potential, and the output sinking currents are turned off.When transistor Q23 is conductive, as by application ofthe Reset 2 waveform, the upper current mirroristurned on, and a large current becomes available via transistor Q27 for resetting capacitorC5.

COMPARATOR NETWORK 142 The Comparator Network 142 accepts the output current from the Integrating Transconductance Amplifier 141, "integrates" that current in the integrating capacitor C5, and by measuring the change in voltage on the capacitor by comparisons to internal voltage references determines the commutation instant As earlier noted, the amplifier output current is proportional to the reverse electromotive force (orvoltage) inducedintheunenergizedwinding. lfthatvoltageis integrated form the reference rotor position, where the voltage reverses in direction, or zero, an accurate measure ofthe actual rotor position may be obtained with respectto reference position.Since the amplifier produces an outputcurrentproportionalto input voltage, an integration ofthe amplifier output current equals an integration ofthevoltage (assuming appropriate limits of integration). The Comparator Network 142 produces an output pulse (Reset 1) when the measured voltage change has reached the correct value, and causes commutation. In addition, the Comparator Network, in cooperation with the Auton ull Circuit 143, is used to sense the correction of imbalance in the Integrating Amplifier. In nulling the Integrating Amplifier, which occurs once for each commutation in the present arrangement, an offset current is incremented until the output current ofthe Transconductance Amplifier reverses in direction (passes through zero).When that occurs, the Comparator Network produces an output pulse (Reset 2) terminating the nulling process, causing "reset" of the integrating capacitor C5 and re-instituting timing for the next commutation event.

The Comparator Network 142, which performs the foregoing functions in timing the commutation and amplifier nulling, consists of a transmission gate U85 and accompanying inverter U84, three comparators (COM 13), each followed by a hysteresis gate U79-U81, respectively, two flip-flops D16, D17; and a NOR gate U83.

The Comparator Network 142 is connected as follows. The output terminal 152 ofthe Integrating Amplifier is coupled to the signal inputterminal ofthe transmission gate U85, and to the negative input of the comparator COM 3. The transmission gate is a bidirectional device consisting of two complementary field effecttransistors connected in parallel, and requiring oppositely sensed control voltages at the control terminals. The control voltage for U85 is derivedfromtheAutonull Circuit (D7Q) and is coupled to one control terminal uninverted and tothe other control terminal inverted by means ofthe inverter U84.The signal output of the transmission gate U85 is connected to the pad P1 for connection to the integrating capacitor C5, to the positive input terminal ofthe comparator COM 1, and to the negative input terminal ofcomparatorCOM 2.

The individual comparators, which monitor the voltage on the capacitor C5 and/orAmplifier output, are respectively COM 1, the reset comparator, which terminates capacitor reset; COM 2, the comparison meansfortiming the commutation instant; and COM 3,the nulling comparator.

The inputs ofthethree comparators COM 1-3 are connected asfollows. The positive input of COM 1 is connected to the signal output of the transmission gate U85 and via the pad P1 to the integrating capacitor C5. The negative input of COM 2 is also connected tothe signal output ofthe transmission gate U85andthe integrating capacitorC5.The negative input of COM 1 is connected to the high (e.g.

6.5 volts) voltage reference Vref 4. The positive input of COM 2 is connected to the low (e.g. 3.0 volts) voltage reference Vref 3. These voltage references (Vref4andVref3) setthe difference involtagethrough which the capacitor C5 is discharged to time the commutation degrees from zero winding voltage. The amplifier output 152 is connected to the negative input to comparator COM 3. The positive input of COM 3 is coupled to an intermediate (e.g. 5.5 volts) voltage reference Vref 2.Comparator COM 3 senses the output voltage ofthe Integrating Amplifier during nulling (when the Integrating Amplifier is disconnected from the integrating capacitor), and detects when the output voltage of the Integrating Amplifier isfalling from Vdd saturation toward Vss to terminate nulling.

The outputs ofthe comparators COM 1-3 are coupled to the hysteresis gates U79-U81,flip-flops D16 and D17, and the NOR gate U83 ofthe Comparator Network as follows. The output ofthe comparator COM 1 is coupled via the inverting hysteresis gate U79 to the reset (R) terminal of theflip-flop Do 6. The output ofthecomparatorCOM 2 is coupled via the inverting hysteresis gate U80 to the clocking terminals (C) of D16 and D17. Both D16 and D17 are designed to trigger on the negative going edge of a clocking waveform.

The output ofthe comparator COM 3 is coupled through the non-inverting hysteresis gate U81 to the reset (R) terminal off17, and to the Autonull Circuit 143 (D7; D input). The output of U81 is denominated the "Null Set" waveform. It is used to signal that the Amplifier output, initially set to maximum offset by theAutonull Circuit, has increased from Vref2 atthe input to COM 3, and is now readyto decrementthe initial offset, toward whatever lesservalue is required to achieve a null. The data (D) inputs of D16 and D17 are both coupledto Vdd.The set (S) terminals of D16 and D17 are coupled tothe POR 150 (POR outputof Us 20). The 0 output of flip-flop Do 6, denominated "Reset 1", is a waveform coupled to the Modulo 6 Counter 144 (D1-D3 C inputs); to the Input Gating 140 (U55, U56, U73-U78); to the Integrating Transconductance Amplifier 141(07,07); and to the Control Logic 145 (U13). The Q ourput of D16 is connected to one input of NOR gate U83. The NOR gate U83 "NQRs"the "Null Output" signal oftheAutonull Circuit 143 (D7; 0) with (D16; Q) to produce the "Reset 2" waveform which is coupled to the Integrating Amplifier 141 (Q9, 018, Q23). The D17; 0 output, denominated the "Null Clock" waveform is coupled totheAutonull Circuit 143 atthe input to inverter U92. The output of U92 (Null Clock Inverted), is coupled to the C input of D6 and to the R inputs of D7-D12. The Null Clockwaveform resets and holdstheflip4lopsD7-D12 untiltermina- tion of the Null Clock interval which ends when the amplifier output exceeds Vref 2, and is ready to decrementtoward a null.

The operation ofthe Comparator Network is illustrated in Figure 8. The commutation period varies from 17to 170 milliseconds depending on motor speed. The capacitor integration period begins when the voltage at the output of the Integrating Amplifier exceedsVref4 (the threshold of COM 1), and reset of the capacito r C5 is complete. The transmission gate U85 became conductive 3 to 5 milliseconds earlier, allowing resetto commence. When U85 is conducting the output ofthe Integrating Amplifier 141 is connected to the integrating capacitor C5, to the positive and negative inputs respectively of the comparators COM 1 and COM 2.

The transmission gate U85 is turned on when reset ofthe capacitor C5 is occurring at the conclusion of nulling. The transmission gate U85 remains conductive during the period that capacitor integration is occurring, and is non-conductive during amplifier nulling (Null Outputwaveform: D7, Q high). The gate U85 becomes non-conducting when the Comparator COM 2 signals thatthevoltage on the ca pacito r C5 has fallen belowVref3, causing the Reset 1 pulse to be generated and the nulling oftheAmplifierto commence.

During amplifier nulling (Null Output D7 Q high), the output ofthe Integrating Amplifier 141 is disconnected by transmission gate U85 from the integrating capacitor C5, and from the positive and negative inputs respectively to the comparators COM 1 and COM 2, but the amplifier output remains connected to the comparatorCOM 3. During nulling (as will be explained) the Integrating Amplifier is initially driven to force the output to go high. The balancing process decrements the offsetto the point where a current reversal occurs atthe output of the Integrating Amplifier, causing the amplifier output voltage to fall precipitously toward Vss.The fall is intercepted at Vref 2 by COM 3 which generates a pulse as the null is achieved, which terminates the nulling sequence upon the next 20KHz clock pulse. Thetransmission gate U85 also re-connects the integrating capacitor at the same 20KHz clock pulse and the charging "reset" of capacitor C5 toward Vdd commences. The duration ofthe nulling period is a variable depending upon the amplifier imbalance. The maximum count available in the present design allows for 32 counts at the 20KHz clocking rate or approximately 1.5 milliseconds for a maximum duration for nulling. Assuming a resettime of about 5 milliseconds, the nulling is designed to accommodate a motor of the indicated design rotating at 20-200 rpms, allowing an interval of from 17to 170 ms between commutations.

The Figure 8 waveform illustrates both the approximatetime scale (for a fast rotation) and the approximate values ofthe critical voltages in the commutation timing and nulling process. The voltage of Vref 4 is set slightly less than the Vdd supply voltage less onethreshold drop plus "one Vds on" (i.e. Vdswhich occursfor Ids=0). The voltage of Vref 4 is set close to but below the upper saturation voltage of the Transconductance Amplifier. The voltage of Vref 4 should be small enough to assurethatthe amplifier saturation voltage is greater than that value.The amplifier output will be forced all the way to positive saturation by the positive back-emf signal which is occurring during thistime. An error in commutation degrees may occur if the back emf does not saturate the Transconductance Amplifier priorto the zero crossing ofthe back emf, and the capacitor does not starttodischargefrom a full charge. The typical value for a Vdd of 9. volts is 6.5 voltsforVref4.

The voltage of reference Vref 3 is somewhat arbitrary, and is selected to be significantly below Vdd/2. The voltage of Vref 3 should stay above the negative saturation voltage ofthe amplifier. Atypical valueforVref3 is3volts.

The value if Vref 2 is chosen belowVref4, but the exact value is not critical. Vref 2 is selected to signal the end of the nulling process. Since the Amplifier 141 is disconnected from the capacitor C5 during nulling, the load on th Amplifier is very light, and the amplifier output voltage falls very rapidly after the null has been crossed. The nulling interval is timed by 20KHz clock counts. Setting Vref 2 too low may allow additional countstooccurafterthe null, which lessens the accuracy of nulling. A reasonable value for Vref 2 is about 5.5 volts.

A more complete understanding ofthe Comparator Network 142 requires resortto the timing diagrams of Figure 12A, in particular, which illustrates the outputs ofthe comparators COM 1-3 already described, on a time scale large enough to show the individual 20KHz clock pulses, and assumes a nulling procedure requiring only a few increments. The Null Set waveform is alternately the COM 3 output. The drawing also showsthe20KHzclocking pulses,the Null Clocking Signal (D17 Q), the Null Output Signal (D7 which is high during nulling; the Reset 2 waveform (U83 Output) which is high during capacitor C5 reset; and the Reset 1 waveform (D16 Q) which is high during nulling and the reset of capacitor C5.

Starting consideration of Figure 1 2Afrom the commutation instant when comparatorCOM 2 goes high (as the voltage on C5 falls belowthe 3 volts on Vref 3), the output of comparator COM 2 goes high; and the U80 output goes low. With both D inputs of D16 and D17 high by the Vdd connection, the negative going edge from U80outputclocksthe0 outputs of Do 6, D17 high. The Q output of D16 supplies the Reset 1 waveformtothe Modulo 6 Counter 144, and the Input Gating 140. The 0 output of D17 (Null Clock) is connected via the inverter U92to the C input of D6 and to the R inputs of D7 and ofthe counter D8-D12. When the Null Clockwaveform goes high, Q1 to Q5 go low; andOl to or go high. The flip-flops set SSto S8 high and set S1 to S4 low, acting via gates U99-U106. As will be explained, this forces the output (152) ofthe Integrating Amplifierto swing from low starting from Vref 3 (e.g. 3 volts) toward high (6.5 volts) as shown in Figure 8.

The Null Clockwaveform going high also resets flip4lop D7 (O low), which in turn disables the gate U85, disconnectign the Integrating Amplifier 141 from the integrating capacitor C5, allowing the autonulling sequenceto begin.

As the voltage atthe output (152) ofthe Integrating Amplifier increases through Vref 2 (5.5 volts), see Figure 8, the output COM 3 (U81) goes low, resetting D17 (O low), removing forced resetfrom the Autonull Circuit, and the autonulling process begins (which will be treated subsequently). When the output of U92 goes high, flip-flop D6 is set by its positive going edge. This enables U93, which allows the clock signal to reach the counter D8-D1 2.

When the decrementing causes a downward swing in the Amplifier output (see Figure 8) below Vref 2 at the input to COM 3, a balance has been detected, and nulling is terminated. The output of COM 3 (U81) and the Null Set waveform goes high. This causes the D inputto D7to go high. The clock inputto D7 is coupled to the output of U93, which NANDS the 20KHz clock (CLK) with the output of D6 (now high). When the next 20KHz pulse occurs after D7:D has gone high, U93 clocks D7, and the null output (D7 Q) goes low. The immediate effect of this (D70) low output is to enable the transmission gate U85. This connects the Integrating Amplifierto CS. Simultaneously, with both D16, Q low, and D7, Q low, NOR gate U83 goes low, initiating the Reset 2 pulse.When D7, 0 goes low, D6 is reset (Q low). This disables U93 removing the clock signal from the counter "freezing" the count at its presentvalue.

As Reset 2 goes high, the Integrating Amplifiervia Q9, 018and 023 begins to supply charging currentto reset C5. The capacitor continues to charge until Vref 4is exceeded atthe inputto C1 (see Fig. 8). When COM 1 goes high (in about4 milliseconds), D16, Q goes high, and Reset 2 is also terminated, discontinuing the resetting of C5, and allowing the capacitor integration period to begin.

In the event of significant imbalance "off" the IC, e.g. due to errors in the resistance ratios ofthe resistor divider network 125, a discharge means should be provided for C5 to prevent th is imbalance from halting the application of successive starting commutations to the motor and preventing starting.

The NPN transistor Q92, having its collector con nectedto the pad P1, its emitter returned to ground through 240K resistor R41,and its base coupled to node 129 to provideforward bias, is the preferred discharge means. A resistor could be used (approximately 2 meg.) but it has the disadvantage of having a relatively small current nearthe lowerthreshold of Vref 3 (2-1/2 to 3 volts). The current error produced in the single in line package "SIP" resistor network 125 could be as high as 2pampas, which is enough to preventthe circuit from reliably starting.

The transistor current source herein provided has the same average current as the currentthat is generated when the trip voltage is reached and should always be capable of (1) overcoming the error in the single in line package (SIP) resistor network, and (2) providing a commutation period in excess of 0.2 seconds for good starting performance. The current is setfor at least 2-1/211amps which provides a commutation period of 0.3+ sec. with the indicated .151if capacitor C5 and provides a margin overthe swamp SIP error.

The upper limitfor current drain is approximately 3.511amp because this will provide a starting period of 0.2 sec., the smallest permissible to guarantee smooth starting performance. The lower limitfor current drain is approximately 211amps, which is set bythe current error dueto the SIP resistortolerance.

The offset error in commutation timing caused by the current source Q92 becomes negligible at medium and high RPM.

THE AUTONULL CIRCUIT 143 TheAutonull Circuit"Nulls" the Integrating Transconductance Amplifier 141 to remove any error in timing the commutation instant attributable to ampli fierinputoffsetandtoimprove motor starting performance. As shown in Figure 8, the autonulling circuit is operative after the commutation instant The commutation instant occurs when the voltage on the CapacitorC5falls belowVref3appliedtoCOM 2, which causes D16 Q, at which the Reset 1 waveform is derived, to go high, and the Null Clock waveform derived at D17 Qto go high.

When the Reset 1 waveform goes high,the switches Q7 and Q8 atthe inputto the Integrating Amplifierareturned on, shorting out any differential inputvoltage atthe gate ofthe inputtransistors OS and Q6. Atthe same time, the gates of both Q5 and Q6 are returned to a 3 volt reference (Vrefl), selected to be equal to an average value ofthe amplifier common mode voltage over the normal operating range.

The Null Clockwaveform from D17 O is coupled to theAutonull Circuit. It causes D7 Qto produce the Null Output waveform which is coupled back to the input to the transmission gate U85, disabling the gate and disconnecting the output ofthe Integrating Amplifier from the Capacitor C5 and the Comparators COM 1 and COM 2.

The Null Clockwaveformfrom Dl70also resets and holds the Autonull Circuit in a preassigned initial state in which a maximum offset (+1 2pa) is applied to the Integrating Amplifier sensed to produce an assured current supply at the amplifier output.

By these three events, the output voltage ofthe amplifier previously at 3 volts, begins to climb, and when it exceeds 5.5 volts at Vref 2, COM 3 produces a low in the Null Setwaveform.The low in the Null Set waveform is accompanied by a low in the Null Clock waveform at Do 70. This releases the Autonull Circuit from its initial state, and allows decrementing ofthe offset atthe amplifier input. Decrementing occurs at the rate of the 20KHz clock coupled to the input of gate U93. When the outputvoltage ofthe amplifier falls below Vref 2, balance is achieved.

Atthe nextclockpulse,the Null Output waveform (D70) goes low, enablingthetransmission gate U85, and causing the generation ofthe Reset2 pulse, which as earlier noted, turns the Integrating Amplifier into a maximum current supply mode (lSOpa)for charging Capacitor C5. When the uppervoltage reference Vref of 6.5 volts is crossed, both Reset 1 and Reset 2 terminate, and the next capacitor integration period commences.

The Autonull Circuit 143 is depicted in Figure 7. It includes the resistive elements (R3, R4) of a modified current mirror (010,011), which is in one channel of the two channel differential input Integrating Transconductance Amplifier 141. The current mirror is modified by the inclusion of means for introducing a digitally controlled offset current (S1-S8,065-068), a counter (D8-D12) for achieving a large initial current offset followed by an ordered decrementing ofthe offset current to the desired final value, the counter also storing the final decremented state, a decoder (U99-U 106) fortranslating the counter state to appropriate offset current settings, and control logic interfacing with the remainder of the control IC for initiating the nulling process and for terminating the process when a null in the amplifier output has been produced.

The digitally controlled current mirror consists of a first set of 4 digitally scaled resistances R3A, R3B, R3C and R3D, and a second set of 4 digitally scaled resistances R4A, R4B, R4Cand R4D; afirstsetoffour N-channel transistor switches S8-S5 associated with the first set of resistances R3A-D; a second set of four N-channel switches S4-S1 associated with the second set of resistances; a set of four P-channel current source transistors Q68-Q65, each associated with the supply of currentto a switch in each setofswitches; and a current reference made up of transistors Q59-Q64forthe current sources 065-068.

The elements ofthe decrementing current sink are interconnected as follows. The resistances R3A, R3B, R3C and R3D are serially connected in the order recited between the source ofthe reference transistor 010 in the current mirror Q10, 01 1 and the IC ground, while the resistances R4A, R4B, R4C and R4D are serially connected in the order recited between the source of the output transistor 011 in the current mirror. and IC ground. The "A" resistors are of 4 units magnitude, e.g., 100062; the "B" resistors are of 2 units magnitude, e.g. 500fl and the "C" and "D" resistances are of 1 unit magnitude, e.g. 250fl.

A current source is provided for supplying current via a first transistor switch to each tap on R3, or via a second transistor switch to a corresponding tap on R4. Starting from thetaps above R3D and R4D,the current source 065 has its source connected to Vdd, and its drain jointly connected to the drain of transistor switch S5, whose source is connected to the series resistance R3 above R3D, and to the drain of transistor switch S1 whose source is connected to its series resistance R4, above R4D. The current source 066 has its source connected to Vdd, and its drain jointly connected to the drain of tra nsistor switch S6, whose source is connected to the series resistance R3 above R3C, and to the drain of transistor switch S2 whose source is connted to the series resistance R4, above R4C.The current source 067 has its source connected to Vdd, and its drain jointly connected to the drain of transistor switch S7, whose source is connected to the series resistance R3 above R3B, and to the drain of transistor switch S3 whose source is connected to the series resistance R4 above R4B. The current source 068 has its source connected to Vdd, and its drain jointly connected to the drain of transistor switch S8, whose source is connected to the series resistance R3 above R3A, and to the drain of transistor switch S4 whose source is connected to the series resistance R4, above R4A.

The current sources 065-068 are of 45/12 geometry and have four gates tied to a common current reference comprising the transistors Q69-064. The current reference transistors are connected in two series paths. The P-channel transistor Q59 has its source connected to Vdd and its drain connected to the drain and gate of N-channel transistor 061. The source of 061 is connected to the drain and gate of N-channel transistor Q62. The source of Q62 is connected to the drain and gate of N-channel transistor Q63, whose source is connected to IC ground. Transistor Q59 is of 4/40 geometry, while transistors Q61-Q63 are of 25/4 geometry. The second series path in the reference comprises a P-channel transistor 064 having its source connected to Vdd and its gate and drain tied together and to the drain of N-channel transistor Q60.The source of Q60 is connected to IC ground and the gate is connected to the interconnection between 059 and 061. The arrangement establishes a current of about 18 microamperes in the reference and because of the geometry ratio, currents of about 6 pa in each ofthe current sources Q68-Q65.

A current offset between input and output current in the Q10, Q11 current mirror ofthe Integrating Amplifier is achieved by the settings of the respective switches S1 to S8. The gate to ground voltage ofthe transistor Q11 is held into equality with the gate to ground voltage of Q10. If all switches S1-S8 areoff, and assuming that the resistances R3 and R4 are equal, then the current in 011 will accurately mirror the current in 010. If, however, a 6pa current is injected into a part of R3 (e.g., R3D by conduction of switch S5,) a small increase in gate to ground voltage will occur in Q10; and the increase in cu rrent should cause an equal IR drop in R4.Since R3D is 1/8th of the total resistance of R3, which equals R4, the 6pa current injected by Q65 in R3D produces a positive offset of approximately 6/8pea in the output current of the mirror. If all switches SSto S8 are conductive, a positive offset of approximately 1 2pea in output current in 011 may be expected with respect to the input current in 010.

If switches S4to S1 are operated, it being assumed that switches S8 to S5 are open, then the output current is decreased in relation to the input current by comparable decrements: 6/8pea when S1 is conductive, and negative offset of approximately 1 2pea when S1-S4 are all conductive. The result is to give a control range of approximately 24via for nulling the amplifier.

The immediate control of the states ofthe switches S1-S8, which control the offset current in the current mirror is provided by the 5 stage counter D8-D12, and thedecoderconsisting of 8 NOR gates U99-U106 interconnecting the output stages ofthe counter to the gates of the individual switches. The counter is in turn controlled by the control logic which comprises the gates U92-U94 and theflip4lops D6 and D7. The decrementing of the counter occurs at the 20KHz clock rate ofthe Oscillator 147.

The switches, counter, decoder and control logic of the Autonull Circuit are interconnected and exchange control waveforms as follows. the two control waveforms applied to the Autonull Circuit are the Null Clockwaveform derived from D17 Q and the Null Set waveform derived from the comparator COM 3 (i.e., U81 ) both in the Comparator Network 142. The Null Clock waveform is connected to the input of inverter U92, whose output is coupled to the C input of the flip-flop D6 and to the R input oftheflip4lop D7 and to the R inputs of the counter D8-D1 2. The D input ofthe flop-flop D6 is connected to Vdd. The 0 output of D6 and the 20KHz clocking waveformnfrom Oscillator 147 are each coupled to one ofthetwo inputs of NAND gate U93.The output of the NAND gate U93 is directly coupled to the C input of D7, and after inversion by inverter U94, is coupled to the C input of D8, the firstflip-flop in the 5 stage counter.

The Null Setwaveform is coupled to the D input of theflip-flop D7. The Q output of D7 is coupled to the R input of D6. The Null Outputwaveform ofthe Autonull Circuit, responsive to detection of a Null by the COM 3 in the Comparator Network, is derived from doh In the 5 stage counter, the count is propagated by connecting the Ol output of D8 to the C input of D9.

Similarly, the 02 output of D9 is connected to the C input of D10; the 03 output of Dl 0 is coupled to the C input of D11, and the Q4 output of D11 is connected to the C input of D12. Also on the Counter,theDand01 terminals of D8 are joined, as are D and Q2 terminals of D9. Similarly, the D andO3terminals of D10 are joined, the D and04terminals of D11 are joined, and the D and 05 terminals of D12 are joined.

The 8 NOR gates (U99-U 06) form the decoder which translates the states of the counter D8-Dl 2 to appropriate settings for the switches S1-S8 in achieving the desired offset current. The 4 NOR gates U103 to U106 couplethe Ol to Q5 inputs to the switches S5-S8. More particular, the NOR gate U103 has one input connected Q1 and one input connected to Q5 and its output connected to the gate of S5. NOR gate U104 has one input connected to 02 and one input connected to OS and the output of U104 is connected to the gate of S6.Similarly, one input of NOR gate U105 is connected to 03 and one input is connected to 05, and the output of U105 is connected to the gate of S7. Similarly, one input of NOR gate U106is connected to Q4 and one input is connected to Q5 and the output of U106 is connected to the gate of S8. If Q5 is low, the NOR gates Ul 03-Ul 06 are enabled so that a low on any of the Q1-Q4 counter terminals will produce a high at the output of the appropriate NOR gate and turn on the appropriate switch S5-S8.

The4NORgatesU99to U102 couple the Q1 to Q5 outputs of the counterto the switches S1-S4. More particularly, the NOR gate U99 has one input con- nected to Q1 and one input connected to OS and its output connected to the gate of S1. NOR gate 100 has one input connected to Q2 and one input connected to Q5 and the output of U100 is connected to the gate of 52. Similarly, one input of NOR gate U101 is connected to Q3 and one input is connected to Q5 and the output of U101 is connected to the gate of S3.

Similarly, one input of NOR gate U 102 is connected to Q4 and one input is connected to Q5 and the output of U102 is connected to the gate of S4. If Q5 is low, the NOR gates U99-U102 are enabled so that a low on any of the Q1 -Q4 counter terminals will produce a high at the output ofthe appropriate NOR gate and turn on the appropriate switch S1-S4.

Resetting the counter produces a maximum positive offset current (12 a) in the current mirrors by initiallyturning switches S5 to S8 on and S1 to S4 off.

The effect of "clocking" the current from a Reset condition ofthe counter is to decrement the max imum positive offset current in 3/4ua decrements through zero offset current until all switches S5 to 58 are off and then to progressively more negative offset currents until a maximum negative offset current (1211a) is produced when switches S5 to S8 are off and S1 to S4 are on.

The state ofthe switches and offset currents resulting from resetting the counter and then decrementing may be explained asfollows.Thefirst counter stage D8 is associated with the lowest (first) rankswitches S1 and S5. The second counterstage D9 is associated with the second rank switches S2 and S4. The third counter stage D9 is associated with the third rank switches S3 and S7. The fourth counter stage is associated with the fourth rank switches S4 and S8.

If the counter D8-Dl 2 is reset, the Q1-Q5 outputs are set to zero and the 01-Q5 outputs are high. Under these conditions, the switches S1-S4 are open and the switches S5-S8 are closed. Accordingly, a maximum positive offset current (121la) is caused in the output current of the current mirror 010, Q1 1 (and the output ofthe Integrating Transconductance Amplifier goes high).If the counter is now clocked periodicallyfrom the C input of D8, with the stages Q1-Q4 initially at zero, the first clock pulse (aftertransferto Q1) will cause the first stage of the counterto go high, which turns off S5 and which produces a 6/8ua decrement in the offset current. The counter state is 00001. The next clock pulse will produce a low at Ol and a high at 02.

This will turn switch S5 back on and turn off S6, causing a decrement in current of 1 -1/2pa. The counter state is 00010. This process will continue for 16 counts until all switches S1 -S5 are turned off and the counter state is 01111.

The transferto a negative offset current occurs at this point in the count. On the next count, Q5 goes high, disabling the gates U103 to U106 and the counter state, as seen atthe Q1 to OS outputs is 10000. On the same 10000 count, Q5 (complementary to Q5) goes low, enabling the gates U99 to U102 so that additional counts will progressivelyturn on switches 81 through S4. On the same 01111 count, as seen atthe Q1 to Q5 outputs, the switches S5 to 58 are turned off. On the next count, the counter state will be 01110, as seen at the Q1 to Q5 outputs and switch S1 will be turned on. The countwill now proceed as before, until all switches S1-S4 have been turned on, producing a maximum negative offset current 12 a, and the counter state is 00000 as seen from the Q1 to OS outputs. In normal operation, the countwill be suspended at some point in the counting sequence by detection of a null that will halt the count between the maximum positive offset current and the maximum negative offset current.

Assuming thatthe comparator COM 2 has gone high to signal the commutation instant, D16Q, at which the Reset 1 waveform appears, goes high. The Reset 1 waveform shorts out the differential input to the Integrating Transconductance Amplifier input, readying itto begin the nulling process. Clocked also bythe outputof COM 2, D16 Q, atwhich the Null Clock waveform appears, goes high. The Null Clock waveform is coupled via the inverter U92 to the clock input of Duty the resets of D7 and the counter stages D8 through D12.

The D inputto D7, which is coupled to the output of COM 3 (i.e., U81) has been high since the amplifier output fell below 5.5 volts. Thus, the Null Clock waveform at the reset input of D7 produces a high at the D7 output at which the Null Outputwaveform appears. The Null Outputwaveform is coupled back to one input of the NOR gate U83 and to the control input ofthe transmission gate U85. While no change occurs at the NOR gate U83, the transmission gate is disabled, and the output ofthe Integrating Amplifier is now disconnected from the integrating Capacitor C5 and from the inputs to the Comparators COM 1 and COM 2. The amplifier output is now readyfor nulling.

With the Null Clock waveform high, the counter is reset and held in a reset state in which a maximum positive offset current is produced. At this point, the differential amplifier input is shorted, a maximum positive offset current is introduced at the input, and the amplifier output, disconnected from the Capacitor C5, is coupled to the comparator COM 3, and the counter (D8-D12) is reset, holding the offset current at the maximum value. The output voltage of the amplifier which was near 3 volts upon commutation, begins to increase. When the amplifier output voltage exceeds 5.5V, COM 3 goes low, resetting D17 O (i.e., O goes low), and the Null Clockwaveform appearing at D17 0 goes low.The Null Clockwaveform coupled via U92 and inverted to a high, releases D7, and releases the counter D8to D12, allowing the counterto increment in a direction to reduce the offset current, whenever 20KHz clocking pulses are supplied.

Meanwhile, the 20KHz clock pulses from Oscillator 147 have been coupled to one input ofthe NAND gate U93, whose other input is coupled to the Q output of D6. The 0 output of D6 went high when D7 was reset, enabling NAND gate U93, and coupling clock pulses directlyto the C input of D7, and after inversion in U94 coupling inverted clockpulsesto the C input of the counters D8-D12. The incrementing can now pro ceed.

The counter continues to decrementthecurrent offset at the 20KHz clocking rate, and the comparator COM 3,towhich the amplifier output is connected, senses a drop in the amplifier outputvoltage. When the the voltage falls below 5.5 volts (Vref 2), the Null Set waveform (COM 3 output) goes high, coupling a high to the D input of D7. Upon the next positive going edge of the 20KHz clock pulse (CLK) from U93, coupled to the C input of D7, D7 Q, which provides the Null Output waveform, goes low. When D7 Q goes low, it resets D6. (D6 0 goes low.) This effectively disables U93from coupling clock pulses to D7 and D8.

The output of U93, which is now high, is forced to remain high bythe application of a low to one input.

This also forces the clock input of D8to remain low, inhibiting another positive going edge from occur ring and assuring thatthe counter state is "frozen" at the value which resulted in the null just detected.

The inversion in U94 delays the response to D8 by approximately 300 nanoseconds relative to the response of D7. This inversion assures that the positive going clock edge of the CLK waveform supplied to D7 occurs about 300 nanoseconds before the positive going clock edge of the CLKwaveform supplied to D8.

(The difference is due to the width of the narrow portion of the CLK waveforms. The clock pulse has a duty cycle of less than 1%.) The Null Output waveform (D7,O) having gone low, is coupled tothetransmission gate U85, and to the NOR gate U83. U85 is now enabled and reconnects the output of the Integrating Amplifierto C5, and to the comparators COM 1 and COM 2. Simultaneously, U83with two lows upon its input (D17 0 low and D7 Q low) goes high, generating the Reset 2 pulse. The Reset 2 pulse turns on the upper output portion (027) ofthe Amplifier 141, and with the connection made via U85 to the capacitor, the resetting ofthe capacitor is undertaken as shown in Figure 8.When comparator COM 1 detects the Vref4 is exceeded, the next capacitor commutation period begins again.

MODULO 6 COUNTER 144 The Modulo 6 Counter is a reversible counter, which maintains a count ofthe rotor commutation events and position so that the winding sensing sequence and the winding energization sequence keep in step. The Modulo 6 Counter, consistently with a 6 state succession of energization states, repetitively counts to 6, and each counter state corresponds to one ofthe 6 energization states illustrated in Figure 3.

As earlier noted, the forward sequence and reverse sequences are both illustrated. The eventwhich steps the counter is the production of the Reset 1 pulse from D16, at the commutation instant. One output of the counter (the unenergized winding selection signals), in the form of one unique state at one of 6 sequential positions, is coupled via a 6 conductor connection to the enabling gates U73-U78 of the input gating 140. Another output of the counter deals with two state combinations, suitable when applied to the control logic 145 forforming the energized winding selection signals, jointly energizing two windings in the stepping sequence illustrated in Figure 3.A third output ofthe counter is the "Least Significant Bit" (B0; D1 0) used to invert the sense of the neutral winding connection to the input gating (U55, U56) in synchronism with the gating waveforms applied to U73-U78. The controls applied to the modulo 6 counter include a Forward waveform from Forward/ Reverse Logic 149 (U1 12), and a Power on Reset waveform (POR; U120).

The Modulo 6 Counter 144 consists of the following logical elements: threeflip-flops D1, D2, D3forming the memory ofthe counter; three two input NAND gates U8, U9, U10, associated with D2 for decoding from the counter output stages the correct next state for D2 in either a forward or reverse counting sequence, three two input NAND gates U20, U21, U22 associated with D3 for decoding from the counter output stages the correct next state for D3 in either a forward our a reverse counting sequence; a first rank ofthreeinputNANDgates U24-U29, for decoding the memory states of Dl -D3 to obtain a unique state (low) which follows the counting sequence; and a second decoder rank of two input NAND gates for detecting 2 state combinations for application to the control logic 145. Finally, a pairofinverters U12, U7 is provided for introduction ofthe Forward waveform to the Counter.

The elements ofthe Modulo 6 Counter 144 are connected as follows. The R inputs ofthe D1-D3 flip-flops are connected for power on resetto POR 150 (U120 POR). In starting, POR is low, holding D1, D2, D3 in a Q lows high state. When POR goes high, the count may proceed. The D16, Q output (Reset 1) is connected to the clock (C) inputs of D1, D2 and D3.

The 0 output of D1 is connected to the D input of Dl.

The 0 output of Dl is coupled to one input of NAND gates U25, U27 and U29. The Q output of D1 is coupled to one input of U24, U26 and U28. The O output of D2 is coupled to one input of U26 and U27.

The Q output of D2 is connected to one input of U24, U25, U28 and U29. The 0 output of D3 is connected to one input of U28 and U29. The Q output of D3 is connected to one input of U24, U25, U26 and U27.

The three input NAND gates U24-U29 inthefirst rank of memory decoders are arranged bythe foregoing connections to provide a consecutive repeating succession of unique lowstatesofU24, U25, U26, U27, U28, U29, U24, U25, U26, etc ate memory of D1, D2, D3, is incremented. Atthe initial state ofthe memory, U24 is low. The zero binary state (000) may be verified by noting that U24 has its three inputs connected to D1,O; D2,Oand D3,O. When the inputs are high, the U24 output is low (and all other NAND gates are high). This is the "CSO" state.

Assuming that one count has occurred, and D1, Q is now high, U2Swhich has itsthreeinputs connected to Do, 0; D20; and D3 Q (all high),the U25 output is low and the other NAND gates are high. This may be called the binary state 001 orthe "CS 1" state. That this decoding continues may be verified as to each successive counter state. At the next binarystate (010 orthe "CS 2" state): U26 connected to Dl (high); D2, O (high); and D3, O (high) goes (low). Atthe next binary state (011, U27 goes low, etc).The low state remains unique in the NAND gate U24-U29 outputs, which are connected respectively via NOR gates U73-U78to the inputs of transmission gates U62, U64, U66, U68, U70, U72, respectively, so that only one ofthe above transmission gates is enabled at one time, and it is enabled in the desired consecutive repeating succession.

The two input NAND gates U30-U35 in the second rank of memory decoders aid in transferring the state of D1 to D2 to D3 in forward and reverse counting and in commutating the sequence in either a forward ora reverse count. This requires "ORing" two successive states in the first rank of NAND gates for coupling to the second rank. The second rank is also used to furtherthe decoding required for the Control Logic and Output Drivers. In particular, U30 NANDing the outputs ofthe U24 and U25, is high on the firsttwo states and goes low on the third state when U24 and U25 are both high, and it remains low until the end of the count.U31 NANDing the outputs of U25, U26 (CS1, CS2) (equivalentto ORing the active high states CS1, CS2), is 1Gw on the first state, high on the next two and low on the lastthree states. NAND gate U32 NANDstheoutputsofU26, U27; NAND gate U33 NANDsthe outputs of U27, U28; NAND gate U34 NANDs the outputs of U28, U29; and NAN D gate U35 NANDs the outputs of U29, U24.

Onlythe Forward waveform is applied to the Modulo 6 Counter, and both low and highs of that waveform are used to control the Counterfor a forward or reverse count. The Forward waveform from U112 is applied two U12, U7. It is inverted in U12, and re-inverted in U7. The U8, U9, U10 gate assembly associated with counter D2 sets the next state for D2 depending on whetherthe counter is in a forward or reverse mode. Similarly, the U20, U21 and U22 gate assembly associated with counter D3 sets the next state for D3 depending on whether the counter is in a forward or a reverse mode. The gates U8 and U9 have their outputs coupled to NANDgateU10,whose function isto "OR" the inputs into the D input of D2.

Similarly, the gates U20 and U21 havetheir outputs coupled to NAND gate 22, whose function isto "OR" the inputs into the D input of D3. When the counter is in a forward mode, the gate U9 is driven by U31, which decodes states CS1, CS2 if a "low" is present on either state it produces a high atthe input of U10, which is coupled via UlOto the D input of D2. At the same time the outputfrom U12,which is in the inverse ofthe output of U7, is coupled to U8 and to U20. This signal which puts a low on the input of U8 and U20, inhibits the decoded output stage (if low) from being fed backto the D inputs of D2 and D3, respectively.

The transfer of states between flip-flops Dl -D3 and formation ofthe desired consecutive repeating succession is performed in the following manner. In the Forward state, the Forward waveform is high (see Figure 3), and U12 out is low, U7 is high, making U9 and U21 active in transferring the count D2 and D3. U9 NANDsthe output of U7 and the output of U31. U31 is high on the 001 (CS1 low) and 010 (CS2 low) states.

On the state 001, U9 goes low, and U10, irrespective ofthe input, goes high,which is coupled to the D input to D2. Upon the next commutation, Reset 1 clocks a high into the Q output of D2 and D1 increments again to 010 (CS2 low). On the state 010 (CS2 low), U31 remains high and U9 goes low again, and U10, irrespective of its other input, goes high at the D inputto D2. Upon the next commutation, Reset 1 clocks the second high into D2, and D2 Stays high (011; CS3 low). Upon the nextcount, U33 goes high, U21 goes low, and U22 goes high. The next Reset 1 pulse clocks a high into D3, Qout, and a low into the D1 Outfor a (100: CS4 low).The next Reset 1 pulse, U33 remains high and a high is reclocked into D3; Q low into D2, 0; and a high into D7, Q(10'1 : CS5 low). In the next Reset 1 pulse lows are clocked into D3 and D2 and D1 changes stateto (000: CS0).

In the reverse state, the Forward waveform is low (see Figure 3) and U12 is high, U7 is low making U8 and U20 active intransferring the countto D2 and D3.

The sequence is now inverted with U29 becoming lowfirst (CSS low); U28 low next (CS4 low), etc. until U24 is low last. Assuming the D1, D2 and D3 are low at the start of the count, U29 which is tied to the Q outputs of D1, D2, D3, goes low on the first count corresponding to CS5 low state. (The backward count will continue in the same manner already explained.) The NAND gates U30-U35 also aid in decoding the states CS0 to CS5 for application to the Control Logic 145.As noted above, U30, which NAN Ds the U24, U25 outputs, is in an active high state during CS0 and CS1; U31 is in an active high state during CS1 and CS2; U32 is in an active high state during CS2 and CS3; U33 is in an active high state during CS3 and CS4; U34 is in an active high state during CS4 and CS5; and U35 is in an active high state during CS5 and CS0. In short, by a 6 count 6 overlapping timing waveforms have been created, ordered in correspondence to the high durations of CT; AB; BT; CB; ATand BB (shown in Figure 3), respectively. These timing waveforms can be coupled to the Control Logic 145 for ti ming the output signals coupled to the Output Drivers 146.

The Modulo-6 commutation counter (144) is vir- tuallytwo counters in one, an up counter and a down counter sharing both theflip-flops D1, D2, D3 and parts of the decoding logic (U10, U22, and U29-U35).

The up or down counter is enabled/disabled bythe Forward control signal. When the forward gates U9, U21 are enabled, they decode the outputs of the counterflip-flops D1, D2, D3 and setthe inputs of these flip4lopsto the values required forthe next state. Atthe rising edge ofthe RESET 1 signal, these inputs are transferred to the output side ofthe positive edgetriggeredflip-flops (D1, D2, D3). Since this transition occurs simultaneouslywith the edge of the incoming RESET 1 signal, each flip-flop is clocked at exactly the same time. This prevents the outputs from changing at different times (i.e., not in synchronization) and causing voltage spikes (glitches) to appearatthecounteroutputs.

When the outputs of the flip-flops change state at the rising edge ofthe RESET 1 pulse, they are decoded into a variety of state signals (CSO,CS1...

CS5) by gates U24 to U29. Combinations of these states are also decoded by U30 to U35. This decoding occurs substantially simultaneously with the rising edge of the RESET 1 signal. Any slight delay due to propagation delays (e.g., < 100 nanoseconds) through the gates, is several orders of magnitude less than the time it takes forthe next rising edge of RESET 1 to occur (milliseconds). Because ofthis, these signals (which are fed back to the inputs of D1, D2 and D3 to setthe next state) will attain a steady value by thetimethe next rising edge of RESET 1 occurs.

Having this stable input available atthe inputs ofthe flip-flops ensures proper "Glitch-free" operation of the counter.

The decoding of each state and synchronous clocking of the flip-flops causes the length of each state to be fixed, and dependent on the length ofthe RESET 1 pulse and not on the specific state that the counter is in. This is especially important when, in the forward direction, the count reaches Sand must then go to0. This countertreatsthe 5 to 0 transition as just another state transition rather than causing the counterto be RESETwhen the counter reaches the end of its count. Simply resetting the counter at the end ofthe count would result in the unwanted shortening ofthe lasf state or "Glitches" when performing the RESET. The state transitions for the forwardcaseareOtol,lto2,2to3,3to4,4to5,5to 0 .. .,etc.Thenecessaryoutputsforthe"next" state are available from the gates U24to U29 which decode the individual states and combinations of these states which are available from gates U30-U35 and returned via gates U8, U9, U10, U20, U21, U22.

The gates U24-U35, serve the dual function of providing the next state to the commutation counter as well as providing an indication of the present state, or combination of states, to other circuits on the chip.

The reverse gates U8 and U20 operate in a similar fashion when enabled bytheforward signal. In the reverse mode though, the state transitions are O to 5, 5to4,4to3,3to2,2tol,1toO . . .,etc.As mentioned before,thecountercan only change state on the rising edge of the RESET 1 signal. This ensures that even if the count direction is changed from forward to reverse by switching the "Forward" signal line, no pertubations (glitches) will occur in the output ofthe counter. The counter will stay in the present state for its correct amount of time and will then continue counting in the opposite direction upon the next rising edge of the RESET 1 pulse.

All of the flip-flops ofthe counter are equipped with an asynchronous RESET. This RESET is controlled by the Power On RESET circuit (150). When thePOR line is low, the counter is held in its 000 (zero) start state.

When the RESET line POR is released (allowed to go high), the counterwill start counting on the next rising edge of RESET 1 and transition to the next correct state after 0 (5 for reverse direction, 1 for forward direction).

Since there are three memory elements in the counter D1, D2, D3, there are 8 possible states that could occur (0-7). In the eventthatthe counterwould find itself in one ofthe unused states (6 or7) the counter is designed so that itwill transition to a correct state (into the regular counter loop) should one of these states occur. Also the decoder logic U24-U29 has been designed notto decode these two states should they occur. This is so their occurance does not cause problems to any other logic con nected to this circuit.

THE CONTROL LOGIC 145 The Control Logic 145 acceptsthetiming information from the Modulo 6 Counter at the outputs of gates U30to U35, and converts that information into a collection of waveforms suitable for application to the Output Drivers 146 on the IC for application to the three power switches 122, 123 and 124 on the printed circuit board. The Control Logic is timed by a first connection to the Comparator Network 142for response to the (Reset) waveform (D16 0), to cause commutation oftheswitches 122,123 and 124atthe commutation instants.The Control Logic is control ledfor aforward or reverse sequence bytwo connections to the Forward/Reverse Logic 149 (U1 12 Forward, Us 11 Reverse). The output (PWM) from the Pulse Width Modulator 148 is coupled to the Control Logic two modify the output driving waveforms coupled to the output drivers to permit control ofthe powerapplied to the motorwindings.The least significant bit (BO) is sensed by a connection to the Modulo6 Counter 144 (D1 Q)forfurther use in connection with power control.

The output waveforms of the Control Logic 145 are the six waveforms AT, AB, BT, BB, CT and CB illustrated atthebottom of Figure3.Thesewave forms, whose sequences are reversed through operation ofthe Wall Control 105 or the Forward/Reverse Switch S1 on the printed circuit board (Figure 2), provideforforward and reverse rotation ofthe motor.

Similarly, the lined portions ofthe outputwaveforms illustrate those periods during which the respective output switches may be subjected to a duty cycle control through operation of the wall control or potentiometer R40 also on the printed circuit board (Figure2)foradjustmentofthe motorspeed.

The Control Logic 145 consists of a first rank 3 input NAND gates U36-U41 associated with reverse operation ofthe motor, a second rank of 3 input NAND gates U42 - U47 associated with forward operation ofthe motor, a third rankoftwo input NAND gates U48to U53 acting to multiplexthe forward or reverse sequences to the Output Drivers 146. The Control Logic is completed by the gates U13 to Ul 6, which respond to the least significant bit and to the pulse width modulation signals in achieving a continuous control of output power.

The logic elements ofthe Control Logic are- connected as follows. The inputs ofthe Exclusive NOR gate U13are coupledto D16 Q and D1 Q as previously noted. The output on gate U13 is coupled through inverter U14to one input ofthe two input NAND gate U15 and to one inputofthetwo input NAND gate U16. The other inputs of NAND gates U15 and U16 are connected to the pulsewidth modulator 148(U89).The output of NAND gate Ul 5 is connected to one input of each of the three input NAND gates U37, U39 and U41 in the first rank of NAND gates associated respectivelywith the AB, BB and CB switching output pads of the IC and to U42, U44 and U46 of the second rank of NAND gates associated respectivelywith the AT, BTand CTswitching output pads ofthe IC. The output of NAND gate U16 is coupled to one input ofthe NAND gates U36, U38 and U40 in the first rank of NAND gates associated respectively with the AT, BT, CT switching output pads ofthe IC, and to one input ofthe NAND gates U43, U45 and U47 in the second rank of NAND gates associatedwiththeAB, BB,CB switching output pads of the IC.

One input of gate U36 and one input of gate U43 are connected to the U31 output of the Modulo 6 Counter 144. One input of gate U37 and one input of gate U42 are connected to U34 in the Modulo 6 Counter; one input of gate U38 and one input of gate U45 are coupledtotheoutputofgate U35 in the Modulo 6 Counter. One input of gate U39 and one input of gate U44areconnectedtogate U32inthe Modulo 6 Counter. One input of the gate U40 and one input of gate U47 are connected to the output of U33 in the Modulo 6 Counter. One input of gate U41 and one input of gate U46 are coupled to the output of NAND gate U30 in the Modulo 6 Counter.Finally, one input ofthe gates ofthefirst rank U36-U41 are coupled to the Forward/Reverse Logic (Ulll)for reverse operation; and one input ofthe gates in the second rank U42-U47 are coupled to the Forward/Reverse Logic (Ul 12) forforward operation. The outputs of NAND gates U36 and U42 are connected to the inputs of the two input NAND gate U48. The outputs of NAND gate U37 and U43 are connected to the inputs of NAND gate U49; U38 and U44 outputs to the input of U50; U39, U45 outputs to the inputs of USI; U40, U46 outputs to the input of U52; and the outputs of U41, U47to the input of U53.The outputs ofthe NAND gates U48-U53, as will be explained, are coupled to the Output Drivers for eventual connection to the separate output pads P7 (AT), P8 (AB), P10 (BT), P9 (BB), P1 1 (CT), P12 (CB) respectively. As earlier noted, these are the six waveforms illustrated atthe bottom of Figure 3.

The production ofthe output waveforms listed above may be explained as follows. The Q outputs of theflip4lops Dl, D2, D3 forming the memory of the Modulo 6 Counter and illustrated in Figure 3 establish thetiming and duration oftheWaveformsCS0,CS1, CS2, etc. of the Modulo 6 Counter. Logical combinations of these waveforms taken two at a time by the gates U30-U35 in the Modulo 6 Counter produce waveforms having high portions of double count duration corresponding to the high portions of the output waveforms. At the separate stages ofthe three stage motor, this means that in the middle ofthe energization period for one stage (e.g., A), a second stage (e.g., B) is being de-energized while a third stage (e.g., C) is being energized so that two stages are being energized at all times.

The logical combination of the CS1, CS2 states, which appears atthe output of gate U31 is coupled for forward operation of Switch Ato one input of gate U43, the output of which is coupled via gate U49, in forming the AB drive waveform, and via output driver BOBAto the Pad P8. For reverse operation ofthe Switch A,the output of gate U31 is coupled to one input of gate U36, whose output is coupled via gate U48, in forming the AT drive waveform, and via output driverTOBAto the Pad P7.

The logical combination ofthe CS2, CS3 states, whichappearsattheoutputofgate U32 is coupled for forward operation of Switch Bto one input of gate U44, the output of which is coupled via gate U50, in forming the BT drive waveform, and via output driver TOBB to the Pad P10. For reverse operation ofthe Switch B, the output of gate U32 is coupled to one input of gate U39, whose output is coupled via gate U51, forming the BB drivewaveform, and via output driver BOBB to the Pad P9.

The logical combination ofthe CS3, CS4 states, which appears atthe output of gate U33 is coupled for forward operation of Switch Cto one input of gate U47,theoutputofwhich is coupled via gate U53,in forming the CB drive waveform, and via output driver BOBC to the Pad P 2. For reverse operation ofthe Switch C, the putput of gate U33 is coupled to one input of gate U40, whose output is coupled via gate U52, in forming the CT drive waveform, and via output driverTOBC to the Pad P 1.

The logical combination ofthe CS4, CS5 states, which appears at the output of gate U34 is coupled for forward operation of Switch Ato one input of gate U42,the output of which is coupled via gate U48, in forming the AT drive waveform, and via output driver TOBAto the Pad P7. For reverse operation of the Switch A, the output of gate U34 is coupled to one input of gate U37, whose output is coupled via gate U49, in forming theAB drivewaveform, and via output driver BOBAto the Pad P8.

The logical combination of the CS5, CS0 states, which appears at the output of gate U35 is coupled for forward operation of Switch B to one input of gate U45, the output of which is coupled via gate U51, in forming the BB drive waveform, and via output driver BOBB to the Pad P9. For reverse operation of the Switch C, the output of gate U35 is coupled to one input of gate U38, whose output is coupled via gate U50, in forming the BT drivewaveform, and via outputdriverTOBB to the Pad P10.

The logical combination ofthe CS0, CS1, states, which appears at the output of gate U30 is coupled for forward operation of Switch C to one input of gate U46, the output of which is coupled via gate U52, in forming the CT drive waveform, and via output driver TOBC to the Pad P 1. For reverse operation of the Switch C, the output of gate U30 is coupled to one input of gate U41 ,whose output is coupled via gate U53, in forming the drivewaveform, and via output driver BOBC to the Pad P12.

As already noted, forward rotation of the motor is provided when the Forward waveform is high and the Reverse waveform is low. Since the Forward waveform is high in the lefthand portion of Figure 3, the waveforms ofthe counter states (CS0, CS1, CS2, etc.) and the output switching waveforms (AT, AB, BT, etc.) to the left ofthe center ofthe figure illustrate forward operation. To the right ofthe center of the figure, the Forward waveform goes low and the Reverse waveform goes high. Accordingly,thewave- forms ofthe counter states and output switching waveforms are reversed in sequence. Forward operation is provided by means of the gates U42-U47.

Forward operation is enabled with a high due to the Forward waveform coupled to one input of each of the gates U42-U47. When all three inputs of U42-U47 are high, at selected times in forward operation, the outputs of selected pairs of these gates go low, and assist in forming the forward sequence ofthe output waveforms. During forward operation, all ofthe gates U36-U41 are quiescent due to a low of the reverse waveform on each of these gates.

Similarly, reverse operation is provided by means ofthe gates U36-U41. Reverse operation is enabled with a high duetothe Reverse waveform coupled to one input of each ofthegates U36-U41.When all three inputs of the gates U36-U41 are high at selected times in reverse operation, the outputofselected pairs ofthese gates go low, and assist in forming the reverse sequence of the outputwaveforms. During reverse operation, all ofthe gates U42-U47 are quiescent due to a low from the forward waveform on each of these gates. The two input NAND gates U48-U53 are enabled for eitherforward or reverse operation and couple an inputto the output drivers from eitherthe active forward orthe active reverse gates.

The output switching waveforms AT, AB, BT, etc.

will be virtually as shown in Figure 3 bythe solid line high portions in a setting ofthe manual speed controls R40 and 105 (see Fig. 2) in which a maximum of power is applied to the motorwindings. The amount of powerthat is applied is variable from a lower limit of no powerto an upper limit of full power.

Full power operation occurs when the two serially connected winding stages are energized 100% of the time. Duty cycling operation in the individual switching waveforms occurs in those regions defined by a solid line high in the outputwaveform and a dotted line low. For instance, the forward AT output switching waveform, has a high coincidental with the CS4 low and the CS5 low. The AT waveform has a dotted low for one Reset 1 pulse (equal to the width of the Reset(1)pulse)atthe beginning ofthe CS41Owora dotted low delayed one Reset (1) pulse at the beginning oftheCSSlow,and continuing to the end of the CS5 low.These two periods, as will be shown, are periods during which a 20KHz waveform is subjected to pulse width modulation, which in one limit is not applied at all for a zero duty cycle and in the other limit losesthe periodic component and becomes continuousforthe 100% duty cycle. In the customary intermediate values of duty cycle, a square wave is produced having a 20KHz repitition rate, and some ON and some OFF time.

The production ofthe dotted line "lows" in the output switching waveforms, during which duty cycled operation occurs, involves the gates U13, U14, U15 and Ul 6. The waveform B0 (the least significant bit) from the memory D1 ofthe Modulo 6 Counter, is "exclusive NORed" with the Reset 1 pulse from the Flip-Flop (D16Q) of the Comparator. The Reset 1 waveform (referring to Figure 8), commences at the commutation instant, and has a duration of about 1/3 of one commutation period in the fastest motor speed setting. In the slowest motor speed setting, the Reset 1 pulse has a duration of about 1/30th of one commutation period.The "exclusive" NORing of the two waveforms produces a high when both waveforms are low and a low when both waveforms are high, and produces a waveform at the output of gate U13which is a delayed inversion ofthe BOwaveform having the same high and low durations, but delayed by the duration of the Reset 1 pulse as shown in Figure 3. The output of gate U13 is then coupled to the input ofthe gate Ul 6 and through the inverter U14to the input ofthe gate Us 5. The duty cycled waveform (PWM) is also supplied to the inputs ofthe gates Ul S and U16.The U13waveform is NANDedwith a PWM output in U16 and the output of U16 is applied to the reverse gates (U36-U41).Similarly, the Ul 3 wave- form after inversion in Ul4isNANDedwitha PWM waveform in gate U15 and the output of gate U15 is coupled to the input offorward gates U42-U47.

Duty cycled operation occurs in the following manner when forward motor rotation is taking place.

In forward rotation,the Forwardwaveform is high so thattheforward gates U42-U47,which produce an active low outputwhen all inputs are high, are enabled. Thus, an active low is produced in gates U42-U47 during the ON times (highs) ofthe duty cycled waveform, occuring during the highs ofthe respective output waveforms from gates U31-U35 of the Modulo 6 Counter. For example, during forward motor rotation,the gate U42 is active in formation of the AT output switching waveform. The output waveform from the gate U34, which corresponds to the ATwaveform is high when CS4 and CS5 are low.

If the duty cycle setting is zero, and the output from U15 stays low,then the ATwaveform is low for an initial portion of CS4 equal to the duration of Reset 1.

ltthen becomes highfora commutation period.The AT waveform (with U15 held low) goes low after CS5 has gone lowwith a time delay equal to the duration ofthe Reset 1 pulse. lithe duty cycle setting is for 100%,and the outputfrom Ul 5 stays high, then the AT waveform remains high for the duration of CS4 and CS5. If an intermediate setting of duty cycle is involved, then theATwaveform as illustrated in Figure 3, is partially ON and partially OFF. During the CS4 low switching occurs at the 20KHz rate for a period corresponding to the length ofthe Reset 1 pulse.The AT waveform then remains high (without duty cycling) for a commutation period, and then returns to duty cycled 20KHz switching forthe balanceoftheCS5lowinterval. ltshouldbenoted thatthestartofthesecond portion ofthe duty cycled switching begins after a delay equal to Reset 1 from the beginning ofthe CS5 low.

The waveforms to the left of Figure 3 illustrate forward rotation of the motorandthe output switch ing waveforms illustrating duty cycled operation. The left portion of the drawing is affected by start-up conditions during the low portion of the POR wave form. The I start waveform, forthis paragraph's discussion, is assumed to be high at all times. After POR (low) is completed, the waveforms assume with their conventional regularity-- until the middle ofthe page is reached. At the middle ofthe page, a reversal in rotation is indicated, and waveforms correspond ing to a reversal are provided forthe righthand portion ofthefigure.Forforward rotation, assuming that the BB waveform is first, CT follows, then AB, then BT, CB,AT, BB, CT, etc. Two waveforms are always on together, and the duty cycling occurs first (after POR) on the ("B" for bottom) ground connected switch (BB). Duty cycling occurs second on the ("T" fortop) VDD connected switch (CT). Duty cycling occurs next on the ground connected switch (AB), next on the VDD connected switch (BT), etc. Each successive time, the switch connection alternates between a Vdd and a Vss (ground) connection. In addition, at any instant, two highs exist-- but one is duty cycled and one is not duty cycled.While this method of alternation causes a shift in the voltage of the winding neutral, the differential amplifier has very good common mode rejection, and by connecting both ends ofthe winding stage being measured to the differential inputs ofthe amplifier, the error produced is negligible. The duty cycled sequence, in addition, is adjusted so that as a winding is de-energized the next winding to be energized has a sense to absorb the turn-offtransient.The Reset 1 pulse is therefore selected to have a duration approximately equal to the duration ofthis transient orslightly longer. The effect is to produce smooter motor operation.

OUTPUT DRIVERS 146 The control IC has at its output 6 separate output bufferamplifiersTOBA, BOBA,TOBB, BOBB,TOBC, AND BOBC coupled to the output pads P7, P8, PlO, P9, P1 1 and P12 respectively. The letter assignments having a coded meaning. The firsttwo letters designate whether switched connection is to be made between the winding stages and B+ or ground potential; "TO" for top means connection to B+ potential, while "BO" for bottom means connection to ground potential. The third "B" means buffer amplifier. The fourth letter, A, B, or C denotes whether connection is made to the A, B, or Cwinding stage.

The output switching waveforms produced by the buffers (in the order already cited) are respectively at the AT, AB, BT, BB, CT and CB. Here, the initial letter designates the winding stage, and the terminal letter determines whether it is designed for load connection to B+ orto ground potential.The output switching waveforms are those shown as the bottom 6 waveforms illustrated in Figure 3. The waveforms with a final "T" indicatethatthey areto be connected to the base of 082 in switch A or its counterpart in switches B or C for connection to B+ potential. The waveforms with a final "B" indicate that they are to be connected to the gate of Q91 in switch A or its counterpart in switch B orCforconnectionto ground potential.The conduction periods that are produced in the top and bottom switches correspond to the highs in the waveforms, with the vertical lines indicating duty cycled operation, as earlier explained.

The logical design ofthe Output Drivers 146 is illustrated in Figure 9. The "Top" buffers are each two stage amplifiers consisting of two successive inverters designed to drive the Top portion (Q82, etc.) of the switches A, B and C. The "Bottom" buffers, each consist of a two input NAND gate in the first stage followed by an inverter in the second stage designed to drive the Bottom portion (091) ofthe switches A, B and C. The second input of each NAND gate is connected to the POR 150 for application ofthe I start waveform. The effect of an inhibition ofthe bottom buffers isto prevent the application of powerto the motor, since both a top and bottom switch must be conductive for powerto flow to the winding stage.As will be explained in connection with the POR 150, upon starting the motor, power is not applied to the windings until the fifth count(CS5) in operation ofthe Modulo 6 Counter 144.

OSCILLATOR 147 AND PULSE WIDTH MODULATOR 148 The Oscillator 147 is used fortwo purposes on the Control IC. In the operation ofthe Autonull Circuit,the Oscillator output controls the counting rate used to decrement the offset current in nulling the Amplifier 141.The Oscillator 147 and the Pulse Width Modulator 148 together enter into the adjustment ofthe speed ofthe fan motor. The electronically commutated motor is designed to operate at a speed established by the amount of electrical power supplied to the motor. When more electrical power is supplied, the motor rotates at a higher rate and when less electrical power is supplied, the motor rotates at a lower rate. In the present embodiment, the amount of power supplied to the fan motor is subject to control from approximately 100% to lessthan 1% of maximum power. This range of power adjustment produces at least a 200:10 rpm speed range. The AT, AB, BT, BB,CT, CBwaveforms illustrated in Figure3 depictthe mode of application of duty cycled energization to the motor windings. The creation of thesewaveforms based on the supplyof a pulse width modulated waveform from the Pulse Width Modulator 148 has been described in connection with the Control Logic 145 and the Output Drivers 146.The present discussion deals with the Oscillator 147 and the Pulse Width Modulator 148 inthecreation ofthat waveform, a combination which facilitates the wide range of motor speed adjustment sought herein.

The Oscillator 147 is a relaxation oscillator. The circuit elements ofthe Oscillator external to the IC are shown in Figure 2. Those circuit elements on the IC are shown in Figure 10A. It comprises a capacitor C6, a transistor Q42 for recurrently discharging the capacitor and a resistorR24for recurrently charging the capacitor. The Oscillator circuit also includes two comparators(COM4and COM 5)forsetting thelimits ofthe voltage swing of the relaxation oscillator, each comparator being followed by and inverting hysteresis gate, U87, U88, a flip-flop comprised of NAND gates U90, U91,a reference voltage comprising transistors Q47, Q48, 049, resistors R9 and R10, and a protective network including resistor R11 and diodes D2 and D3.

The elements of the Oscillator are interconnected asfollows. The capacitorC6,which is external tothe integrated circuit, has one terminal connected to pad P15 and the otherterminal connected to the system ground. The resistor R24, which is also external to the integrated circuit, is connected between pad P13to which the source of Vdd voltage is applied and the pad P15. The N-channel transistor 042 has its drain connected to pad P15 and its source connected to IC ground. The drain oftransistor 042 is also connected via 250he resistor R1 1 to the positive input ofthe comparator COM 4 and to the negative inputterminal of comparator COM 5.The negative inputterminal of the comparator COM 4 is connected to the voltage reference circuit at a point having a normal potential of 1.8 volts. The positive inputterminal of comparator COM 5 is connected to a voltage reference (Vref5) having a potential of 0.75 volts. The output terminal of the comparator COM 4 is connected via the inverting hysteresis gate U87 to one input terminal (S) ofthe NAND gate U90. The outputterminal ofthe comparator COM 5 is connected via the inverting hysteresis gate U88to one input terminal (woof the NAND gate U91 The other input ofthe NAND gate U90 is connected to the output of the NAND gate U91 , at which the Q output of the Flip-Flop appears.The other input ofthe NAND gate U91 is connected to the output of the NAN D gate U90 at which the Output of the Flip-Flop appears. The 0 output ofthe Flip-Flop (U90, U91) is connected to the gate of 042. The output ofthe oscillator CLK in the form of a rectangular pulse having a short interval duration of approximately 300 nano-seconds and a pulse repetition rate of 20KHz is coupled from the output of U91 to U93 in the Autonull Circuitfortiming the counting rate.

The voltage reference and the remainder of the Oscillator circuit components are interconnected as follows. The P-channel transistor 047, of 4/8 geometry, has its source connected to Vdd, its gate connected to IC ground, and its drain connected via 1.6K resistor R9, and 1.6K resistor Ri Oto the drain ofthe N-channel transistor 049, of 50/4 geometry. The gate and drain of Q49 are connected together, and the source of 049 is connected to IC ground. The 1.8 volt reference coupled to the negative input terminal of COM 4 appears at the drain of 049. Protective diodes D2 and D3 are serially connected between Vdd and IC ground, their interconnection being connected to the positive input terminal of COM 4andthe negative inputterminal of COM 5.

The Oscillator operates as a relaxation oscillator whose amplitude is defined by the limits set by the voltage references atthe comparator inputs. Waveforms useful to understanding oscillator operation are provided in Figure 1 OB. When first energized, capacitor C6 beginsto charge toward Vdd, the voltage on thecapacitor C6 appearing atthe inputsof both comparators. When the voltage exceeds PWM "Ref" (+1.8 volts), COM 4 sets the Flip-Flop, and the Q output goes high, turning on Q42, which discharges the capacitor C6. When the voltage on C6 falls below Vref 5 (+0.75 volts), COM 5 goes high, resetting the Flip-Flop, with 0 low and turning off Q42.Since the discharge of C6 is extremely fast (for the values of R24, C6 shown), and COM 5 has a finite response time, the voltage on C6 tends to fall all the wayto ground. The capacitor C5 then begins to recharge, and the cycle repeats. The output waveform (CLK) appearing atthe outputof U91 is coupled to U93 of the Autonull circuit The waveform appearing at the capacitor C6 is the sawtooth waveform in the upper part of Figure lOB. The CLKwaveform is the rectangular pulse superimposed on the sawtooth waveform. The duty cycle, as earlier noted, forthe clock waveform is < 1 %, using the indicated parameters. The selection of the parameters is designed to create a relatively linear sawtooth waveform on the capacitor C5.

The Pulse Width Modulator 148 utilizesthesawtooth capacitorwaveform and provides an output waveform (i.e., PWM output), which is selectively either always off; on some off some; or always on.

The ratio ofon-to-offtime (i.e. Pulse Width) is controlled by the setting of the external potentiometer R40 or the wall speed control 105. Thesethree possibilities are described in Figure 1 OB.

The PulseWidth Modulator comprises the external potentiometer R40, external transistor 081, external resistances R25, R26, R27, R29, R30 and external capacitor C4 associated with "Regulate" pad P1 4 and the comparator COM 6, and hysteresis gate U89 on the IC. The 100K ohm potentiometer R40 has its end terminals connected between Vdd (pad P13) and the system and IC ground (pad P6). The tap on the potentiometer R40 is connected via the 150K resistor to the pad P14. The 2.2if capacitor C4 and the 39K resistor are connected between the pad P14 and system ground. PNPtransistor Q81 has its collector coupled to pad P14, its base connected to the tap on a voltage division network comprising 430K resistor R26 connected to the 150 volt supply and 36K resistor R27 connected to system ground, and its emitter connected via 36K resistor R25toVdd. The principal collector load is the 39K resistor R30 connected between the collector of Q81 and system ground.

On the IC, the comparator COM 6 has its negative inputterminal coupled to the pad P14, and its positive input terminal coupled via the resistance RI 1 to the capacitor CS. The output ofthe comparator COM 6 is coupled to the inverting hysteresis gate U89 at the outputotwhich the PWM output appea rs.

The limits and an intermediate form ofthe PWM output wave are illustrated in Figure 10B.Theduty cycle is affected by both potentiometer R40 and the wall control 105. When the potentiometer R40 is set very low, the negative input ofthe comparator is always below the voltage on the capacitor C6, and the COM 6 output is high. The PWM output derived from U99 is always low. When R4Oissetveryhigh,the comparator output is always low, and the PWM output is always high. When R40 is set at an intermediate position between the limits ofthe oscillation voltage appearing across the capacitor, the PWM output waveform is high partofthetime and low part ofthe time.Since the capacitor voltage is controlled to rise and fall substantially linearly, the practical linear adjustment range ofthe duty cycle is very close to the Oto 100% absolute limits.

Figure 10C,which also applied the Forward/ Reverse Logic, illustrates howthe duty cycle is affected by the wall control 105. When the wall control is used, the maximum B+ voltage is limited to about 135V. Downward adjustmentofthe motor potentiometer in the wall control reduces the B+ (+135V) applied to the motor. Initial downward adjustment ofthe control brings about a reduction in speed by a reduction on the voltage applied to the motor. Afterthevoltage has been reduced from a nominal value of 150 volts to approximately 100 volts, further downward adjustment ofthe wall potentio meter brings about simultaneous downward adjust mentofthe B+ and the imposition of a pulseformat upon the outputwaveform, whose duty cycle is gradually decreased.This is illustrated in Figure lOC.

The duty cycle is controllable bythis control from 100% to nearly 0% as indicated in relation to the adjustment of R40.

The operation ofthe wall control 105 involves the components earlier named connected to the Regulate pad P1 4. These include the transistor Q81 and resistors R25, R26, R27, R29, R30 and R40. Operation ofthewall control adjusts the average voltage applied to the motor. The maximum voltage (e.g. 135 volts) produces the maximum speed. Decreasing the average voltage by means of the wall control produces a substantially linear reduction in voltage applied to the motor as indicated by the upper solid line. (When this reduction begins, let us assume that R40 issetatthe maximum value).Atthe maximum value, Q81 is biased off by an approximately 1.4 volts difference between its emitter voltage, which is defined by the zener diode CR1 at 9 volts above ground, and the base voltage, which is defined at about 10.4volts bythevoltage dividerformed by R26 and R27 connected between the 135V B+ terminal and ground. As the B+ potential is adjusted down, the voltage on the emitter connected to the zener diode remains constant, while the voltage on the base connected to the voltage dividerfalls in proportion to the reduction in B+ potential. At about 11 OV B+,the reverse bias on Q81 is removed, and adequate forward bias providedto overcomethe junction drop, and initiate conduction.To this point, in the downward adjustment ofthe potential, the voltage on the Regulate pad P14 has been unaffected, and has remained atzero potential. Beyondthispoint,con- duction bytransistor Q81 between Vdd and the Regulate pad causes the voltage on the pad to increase. Any slight increase in voltage raises the threshold of U89, and causes a decrease in the Pulse Width. The joint reduction in absolute B+ voltage and in the duty cycle produces an increased rate of decrease in average voltage. At about 60 volts, a minimum rotation rate (just above the stalling speed ofthe motor) is achieved and the PWM duty cycle is near zero. For a REG voltage equal to about 2.2 volts, the PWM duty cycle and speed are both zero.At this point anyfurther decrease in voltage provides no further decrease in speed ofthe motor, but rather a further elevation ofthe voltage on the Regulate pad.

This last range of adjustment permits the voltage increase on the Regulate pad to signal a reversal in rotation by tripping a comparator set at 2.4 volts, as will be described in connection with the Forward/ Reverse Logic 149.

Control of the rate of rotation of the fan motor is achieved buy a combination of an initial reduction in the B+ voltage supplied to the fan motor followed by the utilization of a pulse width modulated form of energization in which further reduction of the B+ supply is accompanied buy a progressive narrowing of the energizing pulsesoffixed repetition rate. As the voltage is further reduced, a minimum point is reached at which there is essentially no "on" time for the pulses and the energization is essentially cut off.

The practical range of speed adjustment exceeds 200:20 rpms.

Togeta 10:1 speed control range using avariation of B+ supplyvoltage onlywould require a 10:1 range of voltage. This is difficultto do and still use a single zener diode power supply to power the IC from the B+ supply. By proportionately reducing pulse width with B+ voltage reduction, a 10:1 speed range can be obtained with only a 2 to 3:1 variation in B+.TheB+ supply voltage variation is used in orderto control motor speed with the wall control. If a wall control is not used, the full speed range can be obtained using PWM only.

Achieving this range of control requires a system capable of stable operation at both the upper and lower limits of operation. This has been achieved by the avoidance of a pulse by pulse feedback loop for current control, and the use of a higher PWM rate. The present arrangement, which uses an open loop pulse width modulation configuration is particularly advan tageous when it is desired to achieve the present wide range of control. Open loop operation ischaracte- rized in a block diagram in Figure 1 OE. The applicable waveform istheATwaveform of Figure lOF, also illustrated with less detail in Figure3.

In the Figure 10E illustration,the motor speed is set by an energy balance between a mechanical load imposed on the ECM motor206primarily bythefan 207 and the electrical energy supplied to the motor and determined bythe operator. The block diagram illustrates a manually adjusted potentiometer 203 whose end terminals are connected between Vdd and ground and whose tap is connected to the negative inputterminal of comparator 202. The positive input terminal ofthe comparator 202 is coupled to the output of a source of sawtooth waveforms 201. The comparator 202 output is coupled to Electronic Gating 205. Power is supplied to the Electronic Gating 205 from the dc power source 204. Power is derived from Electronic Gating bythree separate connections (A, B, C) to thethree winding stages ofthe ECM 206.

The output of the comparator, depending upon the setting of 203 produces an output waveform which is a sustained logical "one", a pulsed logical "1" having a fixed 20KHz repetition rate whose duration is determined bythe setting of 203 orfinally, a sustained logical "zero".

The intermediate case is illustrated in Figure 10E.

The Electronic Gating 205 is primarily the Control Logic 145 whose function isto providegating in response to the pulse width modulation which appears at U89 and in responsetotheoutputofthe Modulo 6 Counterwhich defines the double commutation periods forenergizing the separate winding stages. The setting of the input of the comparator is determined by the operator when he sets the voltage at 203. This arrangement provides a full range of control and does so with the required stability at both the upper and lower limits. While lacking the drift stability of a closed loop feedback system, the open loop system has the advantage of simplicity, and any slightdriftwhich might occur is not ordinarily objectionable.

The objective of open loop PWM (pulse width modulation} operation isto avoid anomalies due to time delay which occur in closed loop PWM systems.

Specifically, in feedback PWM systems the system is turned on and then turned off at a latertime by some motor related parameter such as current or voltage.

There is a minimum pulse width that can be thus generated which corresponds to the total time delay of the system includingtheturn-offdelayofthe power transistors. If an attempt is made to generate a PWM pulse which is shorterthan the system time delay, the system will eitherjump to zero from some finitevalue or itwill duty cycle back andforth between zero and this minimum finite value, in a bang-bang way, trying to achieve the "Forbidden" setting by averaging over many pulses some ofwhich are too large and the others of which are zero.

The avoidance of these anomalies sets requirements upon the manner of adjusting the variable level and the mode of generation of the periodic waveform, the two being illustrated as the inputs to the comparator 202 of Figure 10E. Requirements are also placed upon the relationship of one to the other.

In the disclosed embodiment, the user of the fan may look at the fan, determine whether it is going at the desired speed and make an upward or downward adjustment. The adjustment, once made is essentially independent of what happens to the motor and the power circuit, and when the user has moved away from the control and is no longer regulated by hand and by eye, this operation is also open loop.

The control 203 need not be manually adjusted in the mannerjust described, however. The adjusted level may be part of a power sensing, current sensing, cooling sensing, etc. feedback system in which average levels of slowly varying parameters such as average currents, average temperatures, etc. may be used. It is thus possible to have an open loop modulator used in a closed loop motor system.

The adjustable level in the PWM input must meet two criteria. It should not be instantaneously responsive to motor circuit parameters nor have any frequency components comparable to that ofthe repetitive wave such as would disturb the distance between intercepts used to define the active state of the comparator output and thus the duty cycle ofthe PWM waveform. Re-phrased, the adjustable wave should not have any components whose rate of change is comparable to the rate of change of the repetitive waveform.

Another requirement is that the repetitive waveform should be independent of the motor in a strict sense in that in both the shortterm and in the long term there is no relationship between them. In the actual embodiment, the oscillator is powered from the same DC supply asthe motor butthe supply is controlled by a Zenervoltage regulatorand DC levels as well as short time current instabilities are precluded from affecting the oscillatorfrequency, amplitude, or waveform. If these conditions are maintained, then the motor speed is adjusted throughout essentially all of its range without any unevenness in the motor speed function.

The present arrangement achieves a large range of speed adjustment with quiet operation. The continuous control range is from approximately 0% to 100% duty cycle adjustment corresponding to a rate of rotation of approximately 10 rpms to approximately 200 rpms maximum. At nearzero duty cycle, the power switches do not fully turn on and operate in an analog fashion down to 0 duty cycle. The pulseto pulse feedback systems on the other hand are usually restricted to 5% to 95% duty cycle adjustment because of limitations in the delaytimes of available low cost semiconductor switches and the delaytimes in the signal logic itself.

Economics normally dictates that the repetition rate ofthe pulses be in excess of the audible limits (20KHz) but not so significantly above audible limits as to require high cost, high frequency transistor switches. An economically practical limit is approximately 30KHz.

In practical circuits using NPN devices, the sawtooth waveform has a very accurate positive peak and a not too accurate lower peak. This is because the positive peak is associated with the turn on of a device while the negative peak is associated with the turn off of the device. Forthis reason the 0% modulation is associated with the positive peak which occurs at approximately 2 volts and the 100% modulation is associated with the negative peak which occurs at ground, since smooth modulation to 0% is more critical. The turn-on time always embraces the positive peak, the turn-offtime the negative.

THE FORWARD/REVERSE LOGIC 149 The Forward/Reverse or direction control Logic is responsive to the setting of the forward/reverse switch S1 coupled to the pad P16Onthe IC, andto a controlled diminution in the B+ supply, effected by the wall motor speed control. An inversion in the logic state ofthe output of 149 causes an inversion in the counting sequence and a reversal in the sense of rotation ofthe motor.

The direction control Logic 149 comprises the transistor 048, the comparator COM 7, hysteresis gate Ul 1 3,the flip4lops D13, D14, D15, exclusive OR gates U107, U110, and NORgates U111 and U112.

External to the IC, the transistor Q81; resistors R25, R26, R27, R29 and R30 (mentioned in connection to PWM 148); and the switch S1 enter into forward/ reverse operation.

ThecomparatorCOM 7, which isthe heartofthe control, has its positive input terminal coupled to the "REG" pad P14and its negative input terminal coupled to an internal reference (Vref 9) at 2.4 volts.

The potential at pad P14,while affected by the setting on potentiometer R40, will not change the state of COM 7. The state of COM 7 may be changed only by adjustment of control 105, which affects the state of conduction of Q81, as earlier described.

The negative inputterminal of COM 7 is connected to a voltage reference to which hysteresis is added at the momentthatswitching takes place. The input connection is made to the drain ofthe P-channel transistor 047, which is never less than 1.8 volts irrespective of reductions in B+. The drain of 047 is connected via serially connected resistances R9, R10 and transistor Q49 (with interconnected gates and drain) to ground. The PWM reference voltage of 1.8V appearing across Q49 is used as the reference to set the maximum amplitude of the sawtooth waveform.

By adding the voltage drops across R9 and RlOto this level (1.8V) and coupling the resulting voltage to the negative inputterminal of COM 7,thetrip pointfor COM 7 is set in a mannerwhich assures that reverse always occurs below zero speed. One ofthe two outputs taken from COM 7 is connected via an inverting hysteresis gate U 113 to the C input ofthe flip-flop D15. The otheroutputof COM 7 is connected to the gate of N-channel transistor 048 of 500/4 geometry, whose drain and source are connected to shunt resistance R9. When 048 becomes conductive as the COM 7 output goes high upon sensing an increase in voltage at P14 in excess ofthe Vref 9, it reduces the voltage on Vref 9 by approximately one quarter volt.This introduces hysteresis which makes the reversal more positive acting, assuring that only a single reversal occurs everytime VREG exceeds Vref 9.

The reduction in B+ is coupled to theforward/ reverse circuit in thefollowing manner. When the B+ voltage is reduced by wall control 105 to a point where Q8f becomes conductive, the voltage on the Regulate pad P14 monotonically increases as shown in Fig. 10C. (It is assumed that R40 is set at a maximum clockwise position when the wall control 105 is used). Adjustment of wall control 105 over the normal range of PWM control leads to a final value of 1.8 volts. Adjustment past 1.8 volts produces a voltage peak in excess of 2.4volts. The comparator COM 7 is set to trip the Forward/Reverse Logic at about 2.4 volts.

The setting of R40 does not interfere with the reversal achieved by control 105 and will not itself produce a reversal in motor rotation. So long as Q81 is nonconductive, the voltage on the Regulate pad P1 4 is determined by the setting of the potentiometer R40 and resistors R29 and R30. With Q81 nonconductive, the configuration sets a maximum voltage on the Regulate pad P14 of approximately 2.2 volts, when the tap on R40 is atVdd (and no reversal will occur). The 2.2 volts is used to assure that minimum speed is reached even underworstcase conditions.

The minimum value of zero volts occurs when the tap on R40 is at ground. When transistor Q81 becomes conductive by a suitable fall in B+ voltage with adjustment of 105,the voltage on the Regulate pad P14 will increase toward Vdd as shown in Figure 1 OC.

The setting of R40, which is isolated by the 150K ohms of R29, has only a slight affect on the Figure 1 OC characteristic.

In normal operation, the operator, when itis decided to reverse the fan motor rotation, reduces the manual control to its lowest speed setting,which first reduces the speed to minimum value (stalling), and then continues past that setting to a value which trips the reversing comparatorCOM 7. Sincethesetting is too low for use, the operator returns the setting forward to the desired speed of rotation. In this manner, the speed characteristic illustrated in Figure 10C is reproduced in the course of either a speed increase or a speed decrease.

The output of Ul 13 is connected to the C input of flip-flop D15. The R input of D15 is connected to the POR 150 (U120). The Q output of D15 is connected to the D input of D15, and the D15 SO output is connected to one input ofthe exclusive OR gate Us 07. The other input ofthe gate 107 is connected to pad Pl 6for application via single pole, double throw switch S1 to eitherVdd or system ground potential. Switch S1 provides the permanent memory for motor direction, and determines the direction of rotation when power is first applied.

The output ofthe exclusive OR gate U107 is connectedtotheDinputofflip-flopD13,which together with flip-flop D14, provides at least one clock pulse of delay before a reversal can occur. The 0 output ofDl3 is connected to the D input offlip-flop D14. The CLK signal is connected to the C inputs of D13, D14. The exclusive OR gate U110 has one input connected to the output of U107 and one input connected to the 0 output of D14,from which is coupled an input of Us 16 (in POR 150). The Q output of D14 is coupledto an inputof U115 (in POR 150).

NOR gate Us 11 has one input connected to the output of exclusive OR gate U110, and one input connected to D14 Q. NOR gate U112has one input connected to the output exclusive OR gate Us 10 and one input coupled to D140.The output of Us 12, atwhich the Forward waveform appears, is coupled to gate Ul 2 in the Modulo 6 Counter and aftertwo successive inversions in U12, U7 is coupled uninverted to the gates of U42-U47 ofthe Control Logic. The output of NOR gate Us 11, atwhich the Reverse waveform appears is coupled to the gates U36-U41 in the Control Logic.

The output state of the Forward/Reverse Logic is defined bythe state of D1 5, wh ich is in turn dependent on the state of COM 7, and on the setting of switch S1 connected to pad P16. When the installation isfirstturned on, D15 is reset (0 low) by the POR. If P16 is connected to ground by S1 (a logical low), then with two lows atthe input of U107, a low is produced atthe U107 output. This produces one low immediately at the input to exclusive OR gate Us 10.

Meanwhile, after a 1 to 2 clock pulse delay, D13 0 and D14 Q have gone low. With two lows atthe input to Ul 10, the Us 10 output goes low. This causes Us 12 (forward) to go low, and U111 (reverse) with inputs which are connected to D13 Q and U 110 (both low), to go high, and reverse operation to occur.

If switch S1 is set high, D1 SO being low, then the exclusive OR gate U107 output goes high, and a high is propagated directly and indirectly via D13 0, D14 Q to exclusive Or gate Us 10. The output of gate Us 10 goes low after a delay of at least one clock pulse, and NOR gate U112, with lows at both inputs, goes high for forward operation.

The delayed operation of at least one pulse is achieved bythe insertion of Dl 3 and Dl 4 in the signal path in parallelwiththe U107 output; and the application of the delayed and undelayed signal to the exclusive OR U110. The exclusive OR produces no high unless both inputs are different. Thus, it actsto defer the transmission of a high to the output gate UllOuntil the delayed and undelayedwaveforms have reached the gate Ul 10 output The logical use of the Qand Q outputs of the flip-flops allows the delay to occurwith both a change to reverse or a change to forward rotation.

The direction control logic 149 produces output signals at Us 11 and U1 12 for control of the direction (clockwise/counter clockwise; or Forward/Reverse) of motor rotation. The absence of an active output signal from Us 11 or Us 12 inhibits any inputto the winding stages. The active outputs (highs) for U111 (Reverse) and U1 12 (Forward) never coexist, and an interruption occurs for long enough to protect the solid state switches 122-4after one active state is terminated, before the other active state starts.

The Forward and Reverse waveforms have been illustrated in the waveforms of Figure 3 and assume a logical high or low. The connections ofthe output of the Forward/Reverse Logic 149 are made to the Commutation Counterfor inverting the count sequence within the counter (U8, U9, U20, U21), as earlier described, and to the Control Logic for selecting the forward (U42-U47) or reverse (U36-U41) "decoders" for achieving the correct switching sequence in the output drivers 146.

POWER ON RESET 150 The Power on Reset or Protection Circuit 150 senses Vdd as it increases after power is first turned on (i.e. "Power On") and holds certain portions of the logic in an initial state (i.e. "Reset") until the appearance of sufficient Vdd voltage gives assurance thatthe logic is valid. It performs a similar function after power is turned off. When power is turned on, it also dictates the initial operation, which is nulling of the Amplifier 141 before it is used for integration timing.

In addition, the POR 150 precludes the application of powerto the motorwindings until other portions of the control IC have been properly initialized and are readyto perform the normal control functions. The present POR circuit performs its function with the addition of an external pad, and does not require the provision of an additional capacitor.

The analog and digital portions ofthe POR Circuit 150 are illustrated in Figure 11 A. The input voltages to the comparator (COM 8 ofthe POR), illustrating the operation of the POR in response to increasing Vdd upon turn on, are illustrated in Figure 11 B. The waveforms derived from the POR 150 are shown in Figures 3, 12Aand 12B.

The Power On Reset 150 maintains an initial reset condition by means of the POR waveform responsive to the instantaneous value ofthe Vdd voltage. The POR waveform becomes inactive when the Vdd voltage exceeds the desired threshold (i.e. 7 volts).

The POR waveform is coupled to the Set inputs of the flip-flops D16, D17 of the Comparator Network 142; to the Reset inputs of the flip-flops Dl, D2 and D3 (assuring a 000 initial state) in the Commutation Counter; and to the Reset input of Dl S ofthe Forward/Reverse Logic 149, assuring a return to the state (Forward or Reverse) established by the position of 81. The D17Q output is coupled via U92 to D7, and D7Q opens gate U85, disconnecting the Amplifier 141 from capacitorC5.When theAmplifier is reconnected after nulling, a significant (6,us) current (IST) is injected into (R4A-D) ofthe Integrating Amplifier in a sense to cause a discharge of capacitor C5, via gate U85, belowthe comparator COM 2 threshold (3 volts). This current, which is interrupted during each of four subsequent nullings, prevents the Amplifier from "hanging up" in a Vdd saturated state upon turn on, but is not so great asto interfere with the reset of the capacitor C5.

TheVdd sensing portion ofthe POR Circuit 150 comprises the transistors Q52-059, the comparator COM 8 and the non-inverting hysteresis gate Us 20.

The positive terminal of the comparator is connected to a first series circuit comprising diode D1 and N-channel transistors 058 and Q59. The negative terminal ofthe comparator COM 8 is connected to a second series circuit comprising the P-channel transistors 052-057.

In the first series circuit, the anode of D1 is connected to the source of Vdd potentials and the cathode is connected to the gate and drain of N-channel transistor 058 of 500/4 geometry. The source and body of Q58 are connected together and to the drain of N-channel transistor 059 of 4/40 geometry. These three connections are interconnected to the positive input terminal of the comparator COM 8. The source of Q59 is connected to the IC ground. The gate of Q59 is connected to the Vdd source. The foregoing connections apply a potential to the positive inputterminal of comparator COM 8 which is equal to the instantaneous Vdd voltage less a constant, which is equal to the voltage drop in diode D1 and drop in 058. This is approximately 1 .4volts.

The negative inputterminal of comparator COM 8 is connected to a second series circuit in which the slope is fixed fraction (K < 1) ofthe Vdd voltage and which is provided with hysteresis to insure positive operation of the POR. In particular, P-channel transistor 052 of 10/6 geometry has it drain connected to the source of transistor 054. P-channel transistor Q54 of 100/4geometry has its drain connected tothe source of Q55. P-channel transistor Q55 of 25/4 geometry has its gate and drain joined, and the two electrodes are connected to the source of Q56. P-channel transistor 056 of 25/4 geometry has its gate and drain joined, and the two electrodes are connected to the source of Q57. Pchannel transistor 057 of 25/4 geometry has its gate and drain connected to IC ground.The P-channel transistor Q53 of 20/6 geometry has its sourceconnectedto Vdd.The gate and drain of 053 are joined and connected to the gate of Q52,to the drain of of Q54 and to the negative inputterminal of COM 8. The outputterminal of COM 8 is connected to the gate of Q54for effecting hysteresis Theoutputterminal of comparatorCOM 8 is connected to the input terminal ofthe non-inverting hysteresis gate U120. The POR outputwaveform is derived from the output of U120.

Upon energization,the output of comparator COM 8 arrives at a logical "low" value once Vdd is in excess of several volts and so remains until the trip point occurs (ata Vdd of about 7 volts).

As shown in Figure 11B,thetrippointofthe comparator COM 8 occurs when the voltages at its positive and negative inputs intersect At this point, the POR waveform goes to an inactive high. The voltage ofthis intersection is designed to be at a level whichallowsthe logic in the digital circuitry ofthe IC to become valid and the analog circuitry, particularly that involved in nulling, to become functional. This voltage is set at approximately7 volts for an upward change in Vdd and 6.5 voltsfora downward change in Vdd as a result of the provision for hysteresis.

The foregoing trip point is determined bytwo independent variables characterizing the series circuits associated with the positive and negative input terminals, respectively, ofthe comparatorCOM 8.

The first is the voltage offset provided bythe diode D1 and Q58 in the first series circuit at the positive input terminal ofthe comparator, it being assumed that the slope ofthe resulting input voltage is unitary as a function of Vdd. The second independent variable is the voltage division ratio ofthe second series circuit, which is coupled to the negative input terminal ofthe comparatorCOM 8 and which is assumed to act ata simple resistive voltage divider. The fraction K has a value of 0.8 for an intercept at about 7 volts. These values are approximate and appreciable latitude isto be expected.

Hysteresis is provided bythe output connection of the COM 8to the gate Q54. If output of COM 8 is low, Q54 is conductive and, similarly, 052 in series with it is conductive. Thus, current is provided to the transistors 055,056 and Q57 via both transistors Q52 and Q54 in one path and Q53 in the other path. When the output of COM 8 goes high, then Q54 and Q52 are disabled to conduct current in parallel with Q53, and the voltage atthe negative inputto COM 8fallsfrom 5.53to 5.41, or 120 millivolts, implying a lower conductance. The change in the Vdd threshold is approximately 1/2 volt and insures a positive switchover.

The output circuitry of the POR circuit 150 responds to both the state oftheVdd as sensed atthe comparator COM 8 and tothe state ofthe other circuits on the IC which are caused to go through a preliminary series of simulated commutations by the POR. The output circuitry of the POR consists ofthe SR flip-flop U118, U119, the NOR gate U86, the three NOR gates U115, U116, U1 17 and the transistors Q69 and S9. Thefive commutation count duration of the ISTand I start POR waveforms is drived from a connection of U115, U116to U25, U29 ofthe Commutation Counter 144.The connection ofU118, Ul 19to U86, and U86to D7QoftheAutonull Circuit 193 causes the Ist waveform to be delayed until after the first nulling, and interruptedforthe nextfour nullings. The circuit is as follows.

The SR flip-flop consists of two, two terminal NAND gates U1 18 and Us 19 with the R input being responsive to the Modulo 6 Counter andto the Forward/Reverse Logic, and the S input being re sponsiveto the state ofthe Vdd (COM 8, U1 20). The outputs of the two NOR gates U1 15 and Us 16 are connected to the input ofthetwo input NOR gate Us 17. One input ofthetwo input NOR gate Us 15 is connected to the CS5 output of the Modulo 6 Counter and the other input of Us 15 is connected to the Do 40 ofthe Forward/Reverse Logic.One input ofthe two inputterminal NOR gate Us 16 is connected to the Modulo 6 Counterfor application ofthe CS1 wave form. The other input of Us 16 is connected to the D14 O output of the Forward/Reverse Logic. The two outputs of NOR gates U115 and U116 are connected to the two respective inputs of NOR gate U1 17. The output of 17 is connected tothe R inputof the flip4lop.Theset(SJinputoftheflip4lopatthe inputof U1 19 is connected to the output of hysteresis gate U120.

0 The NANDgates U118and U119 havecross- coupled outputs, one ( ofwhich is connected to one input of U86, and to the Output Drivers 146. The Q output of the flip-flop appearing at the output of U 19 is coupled to the other input of U118. The Q output of 5 the flip-flop appearing atthe output of Us 18 is connected to the other input of U119. The Q of the flip-flop is then connected to one input of the two input NOR gate U86. The other input of U86 is connectedto D7 Qin theAutonull Circuit 142for ) application of the Null Output waveform.The output of NOR gate U86 is coupled to the gate of N-channel transistor S9 whose source is connected to the resistance R4A-D in the Autonull Circuit. The drain of S9 is connected to the drain of P-channel transistor 5 Q69 whose source is connected to Vdd and whose gate is connected to Vref in the Autonull Circuit.

Conduction of switch S9 allows a 6iA current to flow from current source 069 to R4A-D. Transistor 069 is a P-channel transistor of 45/12 geometry, ) which has its source connected to Vdd and its drain connected to the drain oftransistorswitch S9.

Transistor switch S9, an N-channel device of 45/4 geometry, has its source connected to the upper terminal of R4A-D for return to IC ground. The gate of 5 S9 is connected to the output of U86. The gate of Q69 is connected to the voltage reference Vref 8 in the Autonull Circuit,which is adjusted to supply a 6pA (IST) currentto the resistance R4A-D in the Autonull Circuit. The current (IST) causes a negative output 0 current ofthe same amountto occur in the output of the Integrating Amplifier and insures the discharge of the capacitor C5, should there be a tendency of the Amplifier 141 to hang upata positivesaturation during this start-up period.

The overall Power On Reset process takes place in thefollowing manner. The waveforms of greatest relevance are those provided in Figure 12B.The output ofthe comparator COM 8 is assumed to be low immediately (and active as soon as any other protected circuitry) upon turn-on of the power. The output of U120 whose input is coupled to COM 8, remainslowandthePORwaveform is in its active low state holding the Comparator Network 142, the Modulo 6 Counter 144, and the Forward/Reverse Logic 149 in the appropriate initial states.More particularly, the flip-flops D16 and Dl 7 of the Comparator Network 142 are set (0 high) providing a "false" commutation signal causing the Reset waveform and the Null Clockwaveform to be high. Theflip4lops D1, D2, D3 ofthe Modulo 6 Counter 144 are resettothe 000 state (Qs low) and theflip-flop D15 ofthe Forward/Reverse Logic 149 are returned to a state corresponding to the setting of theforward/reverse switch S1.

Afurther consequence of a valid low at the output of the comparator COM 8 isthatthe Output Drivers 146 are disabled immediately afterturn-on. This condition assumesthattheSinputofUi 19 is low, the flip-flop (U118, Ul 19) is "set" (0 output low). TheO low output oftheflip-flop applies a low to the bottom output drivers BOBA, BOBB and BOBC in 146, precluding energization of the motor winding stages.

These drivers remain disabled so long astheflip-flop (U118,U119)isset.

Afurtherconsequenceofa low at the output of COM 8 is that a negative offset current IST is supplied to R4A-D in the Autonull Circuit, which is intended to facilitate the Integrating Amplifier's discharge of C5 belowthe 3voltthreshold of comparatorCOM 2 when it is connected by U85to reset and charge capacitor C5. The Q low output of the threshold of flip-flop (U118, Us 19) is also coupled to one input of the NOR gate U86, which has a high due to the Null Output waveform on the other input. The output of U86 is therefore low, causing transistor switch S9 to remain off until the initial Autonull (and next four) periods are over.The Autonull period is defined to be the interval between the moment when the Null Clock waveform goes high (at power on) and when the Null Output waveform goes low.

During the continuation ofthe active low of POR waveform, the states indicated above are maintained.

In addition, the capacitor C5, which influences the state ofthe comparators COM 1, COM 2 and COM 3, is normally discharged atthe start of energization, and is not likely to significantly chargeforthe duration of the active low of the POR waveform. During this time the capacitor C5 is disconnected from the amplifier output since U85 is open because the Null Output waveform is high. As soon as Vdd exceeds 4 or S volts and the Amplifier is active, its outputwill swing to the positive saturation limit since the Autonull Circuit is now supplying it maximum positive offset current (IST is off). Thiswill cause Nullsetto go low and remain low until after POR goes high and a null is detected.

When the POR waveform goes to an inactive high, the forced sets and resets are removed and the Modulo 6 Counter and Autonull Circuits are free to function in a more conventional repeating manner for the nextfour periods.

Afterthe initial Autonull period has concluded (Null Out low), S9 turns on supplying current ISTto R4A-D.

In respectto the Modulo 6 Counter, the CS5 waveform is NOR'd (U1 15) with the D14O output from the Forward/Reverse Logic, which is high in the reverse direction, disabling Us 15. TheCS1 waveform is NOR'd (U1 16) with the D14 0 output. If the Forward/ Reverse Logic is operating in a forward sense, then D14 Q is high, disabling U1 16. If the Forward/Reverse Logic is operating in a reverse sense, then Do 40 is high, U115 is disabled and U1 16 is enabled. Initially, CSO is active andCS5goes high. This is true forfive counts, until CS5 goes low.When CS5 goes low, the output of Us 15 goes high,forcing the output of Us 17 low, resetting theflip4lop Ul 18, Ul 19, turning offthe current IST.

The addition of IST assures that the amplifier offset current remains negative during the time before Vdd has stabilized. The similar POR output waveform I start, which lasts for a five commutation count duration, but is not interrupted during nulling, is coupled to prevent the application of power to the motor until five commutations have occurred.

The protection circuit gives the Autonull circuit five counts to stabilize, and insures adequate (negative) integration current to discharge the timing capacitor C5 should theAmplifier drifttoward saturation in this interval.

The protection circuit acts on behalf ofthe control circuit, and the power switches and, as earlier noted, operates both during power up and power down.

Upon turn on (POR active) the Amplifier 141 is disconnected from the integrating capacitor C5, due to the high on D7 O. Nulling of the Amplifier is initiated when the POR goes to an inactive state. After nulling, the Amplifier is connected forthefirsttimeto C5. The circuitthus insures that nulling will occur as the POR goes inactive and thatthe Amplifier will not be allowed to affect the timing until it is nulled.

The invention has been used primarilywith available neutral connections from the winding stages of the motor. The available neutral connection is not mandatory, however, and a synthetic neutral may be used instead. In general,the requirements ofthe synthetic neutral arethatswitching take place in accordance with winding stage energization sequences, and that a resistance or reactance matrix be substituted for the actual windings. The synthetic neutral should not degrade the system and must respond atthesame level of accuracy as other elements of the system.

The motor control circuit herein described in utilizing a periodically balanced transconductance amplifier responding to the back emf of an unenergized winding stage for commutation timing of an ECM need not be restricted to the illustrative example. The invention need not be restricted to variable speed designs nor to the low speed ranges characteristic of ceiling fan operation. The nulling can be accomplished at higher clocking rates within shorter times to fulfill rpm requirements.

The transconductance amplifierwith intensive distributed degeneration and self-balancing, is well suitedtoa maxiamalyintegrated motorcontrol circuit, in that it places a minimum requirement upon external components and upon external precision resistors, and has an extremely low power dissipation. The power dissipation on the IC is typically 18 milliwattsandonthecontrol circuitistypicallyfrom 0.3 to 1 watt. The resulting motorcontrol circuitthus represents a significant improvement in performance over non-integrated prior art electronic commutation circuits and does so with a significant decrease in cost.

Claims (135)

1. An integrated circuitfor use in a control circuit for an electronically commutated motor adapted to be energized from a power source, said motor having a multistage winding assembly with a neutral connection, and a magnetic assembly, the two arranged for mutual relative rotation, said motor in a given state of a multistate energization sequence having an unenergized winding stage and at least one winding stage energized in the appropriatesenseto cause relative rotation, said integrated circuit comprising:: input terminal means for connection to the winding stages and to the neutral motor connection or equivalentfor deriving the back emf induced in successive unenergized winding stages; input switching means connected to said input terminal means for selecting an unenergized winding stagefordifferential derivation of the induced back emf, said input switching means being responsive to an unenergized winding-stage selection signal:: a two input, differential transconductance amplifier means, the selected differentially derived back emf being coupled between thetwo inputsofsaid amplifier means for conversion to a corresponding current; a terminalforconnecting the amplifieroutputto capacitive integration means, the voltage appearing at said terminal being substantially proportional to the integral of said selected, differentially derived back emf; timing comparison means for comparing the voltage of said integration means to a value suitable for commutation, and upon sensing equality generating a timing signal atthe instantforcommutation;; control logic means for generating winding stage selection signals for motor operation in a multistate energization sequence having m motorenergization states, in each state ofwhich a signal is generated for selecting an unenergizedwinding stageforsensing said induced back emf, and a signal isgeneratedfor selecting at leastone winding stage for energization, the motorenergization state changing in response to said timing signal atthe instantfor commutation to the next state in a sequence; and outputterminals meansforcoupling said winding stage energization signals to a plurality of power switching means for appropriate energization of the winding stages in said multistate sequence.

2. The integrated circuitsetforth in claim 1 wherein said control logic means comprises counting means having one count for each ofthe (m) states of the motor energization sequence (e.g., 0-1; 1-2; 2-3; . .

(m-1 )-m; m-O, 0-1, etc.); and at a constant rate of rotation allocates equal time for each count in a repeating sequence; and wherein said winding stage selection signals are derived from said states of said counting means.

3. The integrated circuitsetforth in claim 2 wherein said counting means comprises a minimum number of flip-flops fo r defi ni ng m states of said counting means, said flip-flops being positive (or negative) edge triggered flip-flops; and wherein said flip-flops are clocked simultaneously by a common pulse at each change of motor energization state for timing accuracy.

4. The integrated circuitsetforth in claim 3 wherein said flip-flops are clocked by said timing signal, the duration of said timing signal being long in relation to the propagation delays in said control logic means.

5. The integrated circuitsetforth in claim 3 wherein said control logic means includes a first rank of gates connected to the outputs of said flip-flops for deriving the signals for unenergized winding stage selection.

6. The integrated circuit setforth in claim 5 wherein the signals from said control logic means for unenergized winding stage selection are a first succession of equal duration pulses, having an active period equal to the duration of a state in the motor energization sequence.

7. The integrated circuit set forth in claim 6 wherein said input switching means consists of an m-fold plurality of input gates, andwherein said first rank of gates in said control logic means consistsofm members, atthe outputofwhich a signal for unenergized winding stage selection appears, said first rank gate outputs being separately connected to said input gates for unenergized winding stage selection.

8. The integrated circuitsetforth in claim 3 wherein said control logic means includes a first rank of gates connected to outputs of said flip-flops and a second rank of gates connected to the outputs of said first rank of gates for deriving signalsforenergized winding stage selection.

9. The integrated circuit set forth in claim 8 wherein the motorhasthreewinding stages, and there are six motor energizatiion states (i.e., m=6), and wherein the signalsforenergized winding stage selection are a second succession of equal duration pulses, having an active period equal to the duration of two motor energization states, in said multistate sequence.

10. The integrated circuit set forth in claim 9 wherein said first rank of gates consists of 6 members, the outputs of said first rank of gates being separately connected to the inputs of said second rank of gates for deriving said second succession of double duration pulses, said second succession occurring in an overlapping sequence (e.g., 0+1; 1+2,3+4,4+5; 5+0; etc.).

11. An integrated circuitfor use in a control circuit for an electronically commutated reversible motor adapted to be energized from a power source, said motor having a multistage winding assemblywith a neutral connection, and a magnetic assembly, the two arranged for mutual relative rotation, said motor in a given state of a multistate energization sequence having an unenergized winding stage and at least one winding stage energized in the appropriate sense to cause relative rotation, said integrated circuit comprising:: inputterminal means for connection to thewinding stages and to the neutral motor connection or equivalentfor deriving the back emf induced in successive unenergized winding stages; inputswitching means connected to said input terminal meansforselecting an unenergizedwinding stage for differential derivation of the induced back emf, said input switching means being responsive to an unenergized winding-stage selection signal; a two input, differential transconductance amplifier means, the selected differentially derived back emf being coupled between the two inputs of said amplifier means for conversion to a corresponding current;; aterminalforconnecting the amplifier outputto capacitive integration means, the voltage appearing at said terminal being substantially proportional to the integral of said selected, differentially derived back emf; timing comparison meansfor comparing the voltage of said integration means to a value suitable for communation, and upon sensing equality generating atiming signal at the instant for commutation;; control logic meansfor generating winding stage selection signals in a first multistate energization sequence having m motorenergization states for forward motor rotation, and in a second multistate energization sequence having m motor energization states for reverse motor rotation, in each state of which a signal is generated for selecting an unenergized winding stage for sensing said induced back emf, and a signal is generated for selecting at least one winding stage for energization, the motorenergization state changing in response to said timing signal at the instant for commutation to the next state in the sequence; said control logic means being responsive to a direction control signal for selection of said first or second energization sequence and outputterminals means for coupling said winding stage energization signalsto a plurality of power switching means for appropriate energization of the winding stages in said multistate sequence.

12. The integrated circuit set forth in claim 11 wherein said control logic means comprises bidirectional counting meanshaving onecountforeach ofthe (m) states of the motor energization sequence (e.g., 0-1; 1-2; 2-3;... (m-1 )-m; m-0; 0-1; etc. in the forward count, or 0-m; m-(m-1);... 3-2; 2-1; 1-0; 0-m; etc. in the reverse count) and at a constant rate of rotation allocates equal timeforeach count in a repeating sequence whether counting forward or reverse, as well as during a change from forward to reverse counting, orfrom reverse to forward counting; and wherein said winding stage selection signals are derived from said counter means.

13. The integrated circuit set forth in claim 12 wherein said bidirectional counting means comprises a minimum number offlip-flopsfor defining m states of said counting meansforforward and reverse counting, said flip-flops being positive (or negative edge triggered flip-flops; and wherein said flip-flops are clocked simultaneously by a common pulse at each change in the motor energization statefortiming accuracy.

14. Theintegratedcircuitsetforthinclaim 13 wherein said flip-flops are clocked by said timing signal, the duration of said timing signal being long in relation to the propagation delays in said control logic means.

15. The integrated circuit set forth in claim 14 wherein said control logic means includes a first rank of gates connected to the outputs of said flip-flops for deriving the signals for unenergized winding stage selection.

16. Theintegratedcircuitsetforthinclaim 15 wherein the signals from said control logic means for unenergized winding stage selection are first succession of equal duration pulses, having an active period equal to the duration of a state in the motor energization sequence.

17. The integrated circuitsetforth in claim 16 wherein said input switching means consists of an m-fold plurality of input gates, and wherein saidfirst rank of gates in said control logic means consists of m members, at the output of which a signal for unenergized winding stage selection appears, said first rank gate outputs being separately connected to said input gates for unenergized winding stage selection.

18. The integrated circuit set forth in claim 13 wherein said control logic means includes a first rank of gates connected to outputs of said flip-flops and a second rank of gates connected to outputs of said flip-flops and a second rankofgates connected to the outputs of said first rank of gates for deriving signals for energized winding stage selection.

19. The integrated circuit setforth in claim 18 wherein the motor hasthree winding stages, and there are six motor energization states (i.e., m=6), and wherein the signaisforenergized winding stage selection are a second succession of equal duration pulses, having an active period equal to the duration of two motor energization states, in said multistate sequence.

20. The integrated circuit set forth in claim 19 wherein said first rankofgates consists of 6 members, the outputs of said first rank of gates being separately connected to the inputs of said second rank of gates for deriving said second succession of double duration pulses, said second succession occurring in a first overlapping sequence (e.g., 0+1; 1 +2; 3+4; 4+5; 5+0; etc.) forforward motor rotation or in a second overlapping sequence for reverse motor rotation.

21. The integrated circuit set forth in claim 20 wherein the members of said first rank of gates arethree input gates, and the members of said second rank of gates are two input gates.

22. The integrated circuit set forth in claim 13 wherein said control logic means includes a first rank of gates connected to outputs of said flip-flops and a second rank of gates connected to the outputs of said first rank of gates, the outputs of said first rank of gates providing signalsforunenergizedwinding stage selection, and the outputs of said second rank of gates providing signals for energized winding stage selection.

23. The integrated circuit set forth in claim 22 wherein the motor has three winding stages, and there are six motor energization states (i.e., m=6), and wherein the signals from said control logic means for unenergized winding stage selection are a first succession of equal duration pulses, having an active period equal to the duration of one state in the motor energization sequence and the signals for energized winding stage selection from said control logic means are a second succession of equal duration pulses, having an active period equal to the duration oftwo motorenergization states in said multistate sequence.

24. The integrated circuit set forth in claim 23 wherein said inputswitching means consists of a 6-fold plurality of input gates, and wherein said first rank of gates in said control logic means consists of 6 members, the outputs of said first rank of gates being separately connected to said input gates for unenergized winding stage selection, and the outputs of said first rank of gates being separately connected to the inputs of said second rank of gates for deriving said second succession of double duration pulses, said second succession occurring in first overlapping sequence (e.g. 0+1; +2; 3+4; 4+5; 5+0, etc,) for forward motor rotation, or in a second overlapping sequence for reverse motor rotation.

25. The integrated circuited as setforth in claim 24 wherein said control logic means comprises a 6-fold plurality ofgates, responsive said direction control signal, for providing winding stage energization signals in either said first or said second energization sequence to said outputterminals means.

26. The integrated circuit as set forth in claim 25 wherein said control logic means includes means responsiveto an energy control signal in a form including periodic pulse width modulated (PWMed) pulses, having a repetition rate which is high in relation to the commutation rate, for modificatio ofsaid energiza tionsignalssuppliedtosaidoutputterminal means for control of the energization sequences.

27. An integrated circuit for use in a control circuit for an electronically commutated reversible motor adapted to be energized from a powersource, said motor having a th ree stage winding assembly with a neutral connection, and a magnetic assembly, the two arranged for mutual relative rotation, said motor in a given state of a six state energization sequence causing relative rotation, having one winding stage energized in one sense, a second winding stage energized in an oppositesense and serially con- nectedwiththefirstwinding stage and a third winding stage unenergized, said integrated circuit comprising:: inputterminal means for connection to the winding stages and to the neutral motor connection or equivalentfor deriving the backemf induced in successive unenergized winding stages; input switching means connected to said input terminal meansforselecting an unenergized winding stage for differential derivation ofthe induced back emf, said input switching means being responsive to an unenergized winding-stage selection signals; a two input, differential transconductance amplifier means, the selected differentially derived back emf being coupled between the two inputs of said amplifier means for conversion to a corresponding current;; aterminalforconnectingtheamplifieroutputto capacitive integration means, the voltage appearing at said terminal being substantially proportional to the integral of said selected, differentially derived back emf; timing comparison meansfor comparing the voltage of said integration means to a value suitable for commutation, and upon sensing equality generating a timing signal atthe instantforcommutation;; control logic means for generating winding stage selection signals in a first six state sequence for forward motor rotation, and in a second six state sequence for reverse rotation, in each state of which a signal is generated for selecting one winding stage for energization in one sense, a signal is generated for selecting one winding stageforenergization in the other sense, and a signal is generated for selecting an unenergized winding stage for sensing said induced back emf, the motor energization state changing in response to said timing signal at the instant for commutation to the next state in the sequence;; said control logic means being responsive to a direction control signal for selection of said first or second energization sequence and to an energy control signal in a form including periodic pulse width modulated (PWMed) pulses, having a repetition rate which is high in relation to the commutation rate, winding stage energization occurring only during the active on time of the pulses of said energy control signals, and outputterminal means for coupling said winding stage energization signals to a three-fold plurality of power switching means for appropriately sensed energization of the winding stages in said multistate sequence.

28. An integrated circuitfor use in a control circuit for an electronically commutated motor adapted to be energized from a power source, said motor having a multistage winding assembly with a neutral connection, and a magnetic assembly, the two arranged for mutual relative rotation, said motor in a given state of a multistate energization sequence having an unenergized winding stage and at least one winding stage energized in the appropriate sense to cause relative rotation, said integrated circuit comprising:: inputterminal meansfor connection to the winding stages and to the neutral motor connection or equivalentfor deriving the backemf induced in successive unenergized winding stage; input switching means connected to said input terminal meansforselecting an unenergized winding stage for differential derivation ofthe induced back emf, said input switching means being responsive to an unenergized winding-stage selection signal; a two input, differential transconductance amplifier means, the selected differentially derived back emf being coupled between the two inputs of said amplifier means for conversion to a corresponding current;; a terminal for connecting the amplifier outputto capacitive integration means, the voltage appearing at said terminal being substantially proportional to the integral of said selected differentially derived back emf; timing comparison meansforcomparing the vol tageofsaidintegration means to a value suitable for commutation, and upon sensing equality generating a timing signal at the instantforcommutation; means for periodically resetting said integration means to an initial state suitable for initiating the succeeding integration; and meansfor periodically nulling the output current of said amplifier means, said nulling being timed to occur after said instant for commutation, but prior to resetting said integration means; said nulling means comprising means for incrementing an offset current at the input of said amplifiermeansto avaluewhich corrects imbalance in the output current of said amplifier means, and sustaining said corrective offset current until nulling again occurs, control logic means for generating winding stage selection signals for motor operation in a multistate energization sequence having m motorenergization states, in each state of which a signal is generated for' selecting an unenergizedwinding stageforsensing said induced back emf, and a signal is generated for selecting at least one winding stage for energization, the motorenergization state changing in response to said timing signal at the instant for commutation to the next state in a sequence; and output terminals means for coupling said winding stage energization signalsto a plurality of power switching means for appropriate energization of the winding stages in said multistate sequence.

29. The integrated circuit set forth in claim 28 wherein said control logic means comprises counting means having one countfor each ofthe (m) states of the motor energization sequence (e.g., 0-1; 1-2; 2-3;..

(m-l)-m; m-O, 0-1, etc.); and allocates equal time for each count in a repeating sequence; said counting means comprising a minimum number offlip-flops for defining said m states, said flip-flops being positive (or negative) edge triggered flip-flops; and wherein said flip-flops are clocked simultaneously by said timing signal, the duration of said timing signal being long in relation to the propagation delays in said control logic means, said winding stage selection signals being derived from the states of said counting means.

30. The integrated circuit set forth in claim 29 wherein the duration of said timing signal is long enough to null said amplifier means and reset said integration means.

31. The integrated circuit set forth in claim 30 wherein said input switching means consists of an m-fold plurality of gates, and wherein said control logic means includes a first rank of m gates connected to the outputs of said flip-flops, and a second rank of m gates connected to the outputs of said first rank of m gates for deriving signals for winding stage selection, said first rank of gates producing a first succession of m equal duration pulses having an active period equal to the duration of one motor-energization state, in said multistate sequence, and said second rank of gates producing a second succession of m equal duration pulses, having an active period equal to the duration of two motorenergization states in said multistate sequence, said second succession occurring in an overlapping sequence.

32. An integrated circuit for use in a control circuit for an electronically commutated reversible motor adaptedto beenergizedfrom a powersource,said motor having a three stage winding assemblywith a neutral connection, and a magnetic assembly, the two arranged for mutual relative rotation, said motor in a given state of a six state energization sequence causing relative rotation, having one winding stage energized in one sense, a second winding stage energized in an opposite sense and serially con nected with thefirstwinding stage and a third winding stage unenergized, said integrated circuit comprising: : inputterminal means for connection to the winding stages and to the neutral motor connection or equivalentfor deriving the backemf induced in successive unenergized winding stages; input switching means connected to said input terminal means for selecting an unenergized winding stage for differential derivation of the induced back emf, said input switching means being responsive to an unenergized winding-stage selection signal; a two input, differential transconductance amplifier means, the selected differentially derived back emf being coupled between the two inputs of said amplifier means for conversion to a corresponding current;; a terminal for connecting the amplifier output to capacitive integration means, the voltage appearing at said terminal being substantially proportional to the integral of said selected, differentially derived back emf; timing comparison meansforcomparingthevol- tage of said integration means to a value suitable for commutation, and upon sensing equality generating a timing signal atthe instantforcommutation; means of periodically resetting said integration means to an initial state suitable for initiating the succeeding integration; and means for periodically nulling the output current of said amplifier means, said nulling being timed to occur after said instantfor commutation, but prior to resetting said integration means; said nulling means comprising meansforincrementing an offset current at the input of said amplifier means to a value which corrects imbalance in the output current of said amplifier means, and sustaining said corrective offset current until nulling again occurs, control logic means for generating winding stage selection signals in a first six state sequence for forward motor rotation, and in a second six state sequence for reverse rotation, in each state of which a signal is generated for selecting one winding stage for energization in one sense, a signal is generated for selecting an unenergized winding stage for sensing said induced back emf, the motor energization state changing in response to said timing signal atthe instantfor commutation to the next state in the sequence; said control logic means being responsive to a direction control signal for selection of said first or second energization sequence and to an energy control signal in a form including periodic pulse width modulated (PWMed) pulses, having a repetition rate which is high in relation to the commutation rate, winding stage energization occurring only during the active on time ofthe pulses ofsaid energy control signals, and outputterminal means for coupling said winding stageenergizationsignalstoathree-fold plurality of power switching meansfor appropriately sensed energization ofthewinding stages in said multistate sequence.

33. The integrated circuit set forth in claim 29 or 32 wherein said control logic means includes means responsiveto saidtiming signal to apply said PWMed energy control signal atthebeginning ofthefirsthalfofthe energization period of a winding stage for the duration of said timing signal, and atthe beginning of the second half ofthe energization period of a winding stage, delaying forthe duration of said timing signal, before applying said PWMed energy control signal forthe remainder ofthe energization period.

34. The integrated circuit as set forth in claim 25, 27 or33wherein said control logic means comprises a 6-fold plural ityof gates for response to said direction control signals andto said energycontrol signals, for providing winding stage energization signals in either said first or said second energization sequence, motor energization occurring only during the active on time of said pulse including energy control signals.

35. The integrated circuit set forth in claim 34 wherein said 6-fold plurality of gates responsive to direction and energy control signals consists oftwo ranks of three input gates; one rank ofgatesfortransmission oftheforward multistate sequence; one rank of gates for transmission of the reverse multistate sequence, and athird rank of gates for "or"ing the outputs of said forward and reverse ranks of gates, one input of the forward and reverse ranks of gates being coupled to the outputs of said second ranks of gates, a second input of said forward and reverse ranks of gates being for application of said direction control signal, and the third input of said forward and reverse ranks of gates being for application of said PWMed energy control signal.

36. The integrated circuit set forth in claim 35 wherein said control logic means includes means responsiveto said timing signal to apply said PWMed energy control signal atthe beginning ofthe first half ofthe energization period of a winding stage for the duration of said timing signal, and atthe beginning of the second half of the energization period of a winding stage, delaying for the duration of said timing signal, before applying said PWMed energy control signal for the remainder ofthe energization period.

37. The integrated circuit set forth in claim 36 wherein said output terminal means consists of six output terminals, and wherein six output drivers are provided for coupling the energized winding stage selection signals from said control logic means to said output terminals for application to the power switching means.

38. The integrated circuit set forth in claim 37 wherein three of said output drivers are for control of power switches connecting individual winding stages to the otherterminal ofthe power source.

39. The integrated circuitsetforth in claim 38 wherein a terminal is provided for connection to a low voltage DC supply suitable for operation of said integrated circuit,thevoltage ofsaid supply changing at a finite rate when power to said integrated circuit is turned on or turned off, means are provided for gating the output drivers associated with one power source terminal offto disable the switches connecting the winding stages to that power sourceterminal, and a protection circuit is provided producing an active output responsive to the voltage of said low voltage DC supply for gating off said drivers when said voltage has been below a first value when power is turned on or below a second value when power is turned off, saidvoltagevaluesbeing set such that normal circuit operation is assured at supply voltages exceeding said first and second values.

40. The integrated circuitsetforth in claim 39 wherein said protection circuit gates off said drivers when power is turned on for a period of time required for stabilization ofthe operation of said control circuit

41. The integrated circuit set forth in claim 40 wherein said protecrion circuit generates an artificial timing signal when poweristurned on, signalling an artificial instantforcommunication, nulling said amplifier means and causing generation of at least a partial sequence ofwinding stage selection signals, and nullings before said drivers are gated on.

42. In a control circuitfor an electronically commutated reversible motor adapted to be energized from a power source, said motor having a three stage winding assembly with a neutral connection, and a magnetic assembly, the two arranged for mutual relative rotation, said motor in a given state of a six state energization sequence causing relative rotation, having one winding stage energized in one sense, a secondwinding stage energized in an opposite sense and serially connected with the first winding stage and athird winding stage unenergized, the combination comprising:: input terminal means for connection to the winding stages and to the neutral motor connection or equivalent for deriving the back emf induced in successive unenergized winding stages; input switching means connected to said input terminal means for selecting an unenergized winding stagefordifferential derivation of the induced back emf, said input switching means being responsive to an unenergizedwinding-stage selection signal; a two input, differential transconductance amplifier means, the selected differentially derived back emf being coupled between the two inputs of said amplifier meansforconversion to a corresponding current; capacitive integration means connected to the amplifieroutput,thevoltageappearing at said integration means being substantially proportional to the integral of said selected, differentially derived back emf;; timing comparison means for comparing the voltage of said integration means to a value suitable for commutation, and upon sensing equality generating atiming signal at the instantforcommutation; control logic means for generating winding stage selection signals in a first six state sequence for forward motor rotation, and in a second six state sequence for reverse rotation, in each state of which a signal is generatedfor selecting one winding stage for energization in one sense, a signal is generated for selecting one winding stage for energization in the other sense, and a signal is generated for selecting an unenergized winding stage for sensing said induced back emf, the motor energization state changing in response to said timing signal at the instant for commutation to the next state in the sequence, said control logic means being responsive to a direction control signal for selection of said first or second energization sequence and to an energy control signal in a form including periodic pulse width modulated (PWMed) pulses, having a repetition rate which is high in relation to the commutation rate, winding stage energization occurring only during the active on time of the pulses of said energy control signals, and athree-fold plurality of power switching means responsive to said winding stage energization signals for appropriately sensed energization of said winding stages in said multistate sequences.

43. The combination setforth in claim 42 having in addition thereto means for periodically resetting said integration means to an initial state suitable for initiating the succeeding integration ; and means for periodically nulling the output current of said amplifier means, said nulling being timed to occuraftersaid instantforcommutation, but priorto resetting said integration means; said nulling means comprising meansforincrementing an offset current at the input of said amplifier means to a value which corrects imbalance in the output current of said amplifier means, and sustaining said corrective offset current until nulling again occurs.

44. The combination setforth in claim 43 having in addition thereto a four-partvoltage divider connected between said inputterminal means and said input switching means to scale down the induced back emf induced in successive unenergized winding stages.

45. The combination setforth inclaim44wherein said control logic means comprises counting means having onecountforeach ofthe (6) states of the motor energization sequence (e.g., 0-1; 1-2; 2-3; 3-4; 4-5; 5-0; 0-1; etc.); and at a constant rate of rotation allocates equal time for each count in a repeating sequence; said counting means comprising a minimum number offlip-flops for defining said states, said flip-flops being positive (or negative) edgetriggeredflip-flops; and wherein said flip-flops are clocked simultaneously by said timing signal, the duration of said timing signal being long in relation to the propagation delays in said control logic means, said winding stage selection signals being derived from the states of said counting means.

46. The combination setforth in claims45 wherein the duration of said timing signal is long enough to null said amplifier means and reset said integration means.

47. The combination setforth in claim 46 wherein said input switching means consists of an m-fold plurality of gates, and wherein said control logic means includes a fist rank of m gates connected to the outputs of said flip-flops, and a second rankofm gates connected to the outputs of said first rank of m gates for deriving signals for winding stage selection, said first rank of gates producing a first succession of m equal duration pulses having an active period equaltotheduration of one motorenergization state, in said multistate sequence, and said second rank of gates producing a second succession of m equal duration pulses, having an active period equal to the duration oftwo motorenergization states in said multistate sequence, said second succession occurring in an overlapping sequence.

48. The combination setforth in claim 47 wherein said control logic means comprises a 6-fold plurality of gates for responseto said direction control signals and to said energy control signals, for providing winding stage energization signals in either said first or said second energization sequence, motor energization occurring only during the active on time of said pulse including energy control signals.

49. The combination setforth in claim 48 wherein said 6-fold plurality of gates responsive to direction and energy control signals consists of two ranks of three input gates; one rankofgatesfortransmission oftheforward multistate sequence, one rankof gates fortransmission ofthe reverse multistate sequence, and a third rank of gates for "or" ing the outputs of said forward and reverse ranks of gates, one input ofthe forward and reverse ranks of gates being coupled to the outputs of said second rank of gates, A second input of said forward and reverse ranks of gates being for application of said direction control signal, and the third input of said forward and reverse ranks of gates being for application of said PWMed energy control signal.

50. The combination setforth in claim 49 wherein said control logic means includes means respon sivetosaidtiming signal to apply said PWMed energy control signal atthe beginning ofthefirst half ofthe energization period of a winding stageforthe duration ofsaidtiming signal, and atthe beginning of the second half of the energization period of a winding stage, delaying for the duration of said timing signal, before applying said PWMed energy control signal for the remainder of the energization period.

51. The combination set forth in claim 50 wherein six output drivers are provided for coupling the energized winding stage selection signals from said control logic means to said power switching means.

52. Thecombinationsetforth in claim 51 wherein three of said output drivers are for control of power switches connecting individual winding stages to one terminal of the power source; andthreeofsaid output drivers are for control of power switches connecting individual winding stages to the other terminal ofthe power source.

53. The combination setforth in claim 52 wherein a terminal is provided for connection to a low voltage DC supplysuitable for operation of said control circuit, the voltage of said supply changing at a finite rate when powerto said control circuit is turned on orturned off, Means are provided for gating the output drivers associated with one power source terminal off to disable the switches connecting the winding stages to that powersourceterminal, and a protection circuit is provided producing an active output responsiveto the voltage of said lowvoltage DCsupplyforgating off said drivers when said voltage has been below a first value when power is turned on or below a second value when power is turned off, said voltage values being setsuch that normal circuit operation is assured at supply voltages exceeding said first and second values.

54. The combination set forth in claim 53 wherein said protection circuit gates off said drivers when poweristurnedonfora period of time required for stabilization ofthe operation ofsaid control circuit.

55. Thecombimation setforth in claim 54 wherein said protection circuit generates an artificial timing signal when power is turned on, signalling an artificial instantforcommutation and nulling said amplifier means; and causing the generation of at least a partial sequence of winding stage selection signals and nullings before said drivers are gated on.

56. The method of operating an electronically commutated motorfrom a power source, said motor having a multistage winding assembly with a neutral connection, and a magnetic assembly, thetwo arranged for mutual relative rotation, said motor in a given state of a multistate energization sequence having an unenergized winding stage and at least one winding stage energized in the appropriate sense to cause relative rotation, comprising:: successively selecting an unenergized winding stage and differentially deriving the induced back emf in relation to the neutral connection, Converting the selected, differentially derived back emf into a corresponding current in a transconductance amplifier, integrating in integration means the amplifier output currentto obtain a voltage substantially proportional to the integral of said selected differentially derived back emf, comparing the voltage of said integration means to a stored value suitable for commutation, and upon sensing equality generating a timing signal atthe instantfor commutation; selecting successive unenergized winding stages for sensing said induced back emf and selecting successive winding stages for energization, and changing said selections atthe instantfor commuta tiontothe next state in the sequence;; and operating a plurality of power switches for energization ofthewinding stages in said multistate sequence.

57. The method of operating an electronically commutated reversible motor from a power source, said motor having a three stage winding assembly with a neutral connection, and a magnetic assembly, thetwo arrangedfor mutual relative rotation, said motor in a given state of a six state energization sequence causing relative rotation, having one winding stage energized in one sense, a second winding stage energized in an opposite sense and serially connected with thefirstwinding stage, and a third winding stage unenergized,comprising:: selecting an unenergized winding stage and differentially deriving the induced backemf in relation to said neutral connection, converting the selected, differentially derived back emf into a corresponding current in a transconduct ance amplifier, integrating in integration means the amplifier output current to obtain a voltage substantially proportional to the integral of said selected differentially derived back emf, comparing the voltage of said integration means to a stored value suitable for commutation, and upon sensing equality generating a timing signal atthe instantfor commutation;; choosing by means of a reversable counter respon siveto a direction control signal either a first six state sequence of winding stage selection signals for forward rotation or a second six state sequence of winding state selection signals for reverse rotation, and selecting successive unenergized winding stages for sensing said induced back emf and selecting successive winding stages for energization in accord ancewith the chosen sequenceand changing said selections at the instant for commutation to the next state in the chosen sequence; and controlling a plurality of power switches for energizing the winding stages in the chosen sequence.

58. The method of claim 56 or 57 comprising, after generating atiming signal at the instantfor commutation, nulling the output current of the amplifier means, and resetting the integration means in preparation for the next integration for timing the selection ofthe next motor energization state.

59. The method of operating an electronically commutated motor as set forth in claim 58 comprising generating an artificial timing signal upon turning on powerto the control circuit, immediately nulling the amplifier and disabling the power switches, and continuing at least a portion of the selected winding stage selection sequence, beforethe steps of claims 68 and 69 are undertaken with the power switches enabled.

60. In a control circuit for an electronically commutated motor adapted to be energized from a DC power source, said motor having a multistage winding assembly, and a magnetic assembly, the two arranged for mutual relative rotation, said motor in a given state of a multistate energization sequence, having an unenergized winding stage in which induced back emf appears which when integrated overtime to a predetermined value indicates the instant at which the mutual relative angular position has been attained suitable for commutation to the next state, the combination comprising:: solid state transconductance amplifier means adapted to be coupled to an unenergized winding stage in the motor, for converting the voltage appearing in the winding stage to a corresponding output current, integration means coupled to the output of said amplifier means for integrating said output current to obtain an output voltage substantially proportional to an integral of said voltage appearing in the winding stage; and comparison meansforcomparing the output voltage of said integration means to a value corresponding to the mutual relative angular position suitable for commutation, and upon sensing equality generating atiming signal attheinstantforcommuta- tion.

61. The combination set forth in claim 60 wherein said transconductance amplifier means has current series feedback to stabilize amplifier transconductance.

62. In a control circuitfor an electronically commutated motor adapted to be energized from a DC power source, said motor including a stator having a multistagewinding arrangementwith a neutral connection, and a permanent magnet rotor associated with said stator, said motor in a given stage of a multistate energization sequence, having an unenergized winding stage in which an induced back emf appears which when integrated overtimeto a predetermed value indicates the instant at which the rotor is atthe angular position suitablefor commuta- tion to the next state, the combination comprising:: a two input solid state differential transconductance amplifier means, one input adapted to be coupled to an unenergizedwinding stage, and the other input adapted to be coupled to a voltage equivalent to that at said neutral connection, said amplifier means converting the differential voltage appearing in the unenergized winding stageto a corresponding output current; integration means coupled to the output of said amplifier means for integrating said output current to obtain an outputvoltage substantially proportional to an integral of the differential voltage appearing in the winding stage; and comparison meansforcomparing the output voltage of said integration means to a value corresponding to the angular position of said rotor suitable for commutation, and upon sensing equality generating atiming signal atthe instant for commutation.

63. In a control circuitforan electronically commutated motor adapted to be energized from a DC powersource, said motorincluding a stator having a multistage winding arrangement with a neutral connection, and a permanent magnet rotor associated with said stator, said motor in a given state of a multistate energization sequence, having an unenergized winding stage in which an induced back emf appears which when integrated overtime to a predetermined value indicates the instant at which the rotor is atthe angular position suitable for commutation to the next state, the combination comprising: : a two input solid state differential transconductance amplifier means, one input adapted to be coupled to an unenergized winding stage, and the other inputadapted to be coupled to said neutral connection, said amplifier means converting the differential voltage appearing in the unenergized winding stage to a corresponding output current; integration means coupled to the output of said amplifier means for integrating said output current to obtain an output voltage substantially proportional to an integral of the differential voltage appearing in the winding stage; and comparison meansfor comparing the output voltage of said integration means to a value corres ponding to the angular position of said rotor suitable for commutation, and upon sensing equality generat ing a timing signal atthe instantforcommutation.

64. The combination set forth in claim 62 or 63 wherein said transconductance amplifier means comprises a two transistor differential amplifier stage, the inputs ofwhich are the transistor control electrodes, said stage determining the transconductance of said amplifier means, and wherein current series feedback is provided comprising a pair of resistances, one connected in series with the common electrode of one transistor of said stage and the other connected in series with the common electrode ofthe othertransistor of said stage to stabilize said transconductance.

65. The combination set forth in claim 64 wherein said transconductance amplifier means includes at least two stages, the input stage of which is said differential amplifier, and the stage(s) succeeding said differential amplifier exhibit substantially unit current gain.

66. The combination setforth in claim 65 wherein said transconductance amplifier means further includes a first and a second solid state current mirror, the output current from thefirsttransistor in said input stage being coupled to said first current mirror and the output current from the second transistor in said input stage being coupled to said second current mirror.

67. The combination setforth in claim 66 wherein said transconductance amplifier means further includes a first and a second solid state buffer amplifier and athird, polarity inverting current mirror; said first buffer amplifier comprising a third transistor having the control electrode common and a first principal electrode coupled to the output of said first current mirror, and the second principal electrode coupled to the input of said polarity inverting current mirror;; the second buffer amplifier comprising a fourth transistor having the control electrode common and a first principal electrode coupled to the output of said second current mirror, and wherein said third current mirror comprises a fifth, output transistor having its control electrode coupled to the second principal electrode of said fourth transistor and a first principal electrode thereof connected to the second principal electrode of said third transistor, said fourth and fifth transistors being connected to provide a push-pull output in which output current is either supplied orwithdrawn.

68. The combination set forth in claim 67 wherein each of said current mirrors comprises at least a first and a second solid state device, the second solid state device being a transistor, said first solid state device exhibiting a voltage drop approximating that ofthe input of said second device, and a first and a second resistance, a first reference series circuit, which comprises said first solid state device and said first resistance, being connected in shunt with a second, mirroring series circuit, which comprises the input of said second solid state device connected in series with said second resistance.

69. Thecombinationsetforth in claim 68wherein the first and second resistances of said current mirrors are selected to provide significant degeneration for accuracy in the currenttransferfunction of said mirrors.

70. The combination set forth in claim 69 wherein the transistors of said transconductance amplifier means are field effect transistors to achieve high amplifier input and output impedances.

71. The combination setforth in claim 70 wherein said transconductance amplifier means is a portion of a monolithic integrated circuit, the transistors, the currentseriesfeedback resistances, andthe current mirror resistances being formed as a portion thereof, the values of said resistances exhibiting smaller variations than the values ofthe transconductances of said associated transistors to stabilize the transconductance of said amplifier.

72. The combination set forth in claim 62 wherein means are provided for resetting said integration means to an initial state suitable for initiating the succeeding integration, said resetting occurring after said instantfor commutation, and wherein means are provided for periodically nulling the output current of said transconductance amplifier means, said nulling being timed to occur after said instant for commutation but prior to resetting said integration means.

73. The combination set forth in claim 72 wherein means are provided for sensing a null and initiating resetting of said integration means in preparation for the next commutation period.

74. The combination set forth in claim 73 wherein a low voltage DC supply is provided suitable for operation of said monolithic integrated circuit, the voltage of said supply changing at a finite rate when power to said control circuit is applied or removed; and a protection circuit producing an output responsive to the voltage of said low voltage DC supplyfor holding at least a portion of said control circuit in an inactive state when said voltage is below a firstvalue when poweristurnedonorbelowasecondvalue when power is turned off, and when said voltage has exceeded said first value as power is turned on, releasing said circuit portion at a predetermined initial state, said voltage values being set such that normal circuit operation is assured at supplyvoltages exceeding said values.

75. The combination setforth in claim 74 wherein said protection circuit, upon termination of said output releases said circuit portion in a state to null said amplifier means to insure balance ofthe output current of said amplifier means before integration.

76. In a control circuitforan electronically commutated motor adapted to be energized from a DC powersource, said motor including a stator having a multistage winding arrangement with a neutral connection, and a permanent magnet rotor associated with said stator, said motor in a given state of a multistate energization sequence, having an unenergized winding stage in which an induced back emf appears which when integrated overtime to a predetermined value indicates the instant at which the rotor is at the angular position suitable for commutation to the next state, the combination comprising:: a two input solid state differential transconductance amplifier means, one input adapted to be coupled to an unenergized winding stage, and the other input adapted to be coupled to said neutral connection, said amplifier means converting the differential voltage appearing in the unenergized winding stage to a corresponding output current; said transconductance amplifier means comprising an input stage comprising two transistors, the control electrodes forming the inputs of said transconductance amplifier means, and a second and a third stage, the second stage being a current mirror, the output current of said firsttransistor being coupled to said second stage and the output current from said second transistor being coupled to said third stage;; integration means coupled to the output of said amplifier means for integrating said output current to obtain an output voltage substantially proportional to an integral ofthe differential voltage appearing in the winding stage; comparison means for comparing the output voltage of said integration meansto a value corresponding to the angular position of said rotor suitable for commutation, and upon sensing equality generating a timing signal atthe instantfor commutation; means for periodically resetting said integration meansto an initial state suitable for initiating the succeeding integration; and means for periodically nulling the output current of said transconductance amplifier means, said nulling being timed to occur after said instantforcommutation, but prior to resetting said integration means; said nulling means comprising meansforincrementing the offset current of said current mirrorto a value which corrects imbalance in the output current of said transconductance amplifier means, and sustaining said corrective offset current until nulling again occurs.

77. In a control circuit for an electronically commutated motor adapted to be energized from a DC power source, said motor having a multistage winding assembly with a neutral connection, and a magnetic assembly, the two arranged for mutual relative rotation, said motor in a given state of a multistate energization sequence, having an unenergized winding stage in which an induced back emf appears which indicates the instant at which the mutual relative angular position has been attained suitablefor commutation to the next state, the combination comprising:: a two input solid state differential trans-conductance amplifier means, one input adapted to be coupled to an energized winding stage, and the other input adapted to be coupled to said neutral connection, said amplifier means converting the differential voltage appearing in the unenergized winding stage to a corresponding bidirectional output current in which output current is either supplied or withdrawn; integration means coupled to the output of said amplifier means for integrating said outputcurrentto obtain an output voltage substantially proportional to an integral ofthe differential voltage appearing in the winding stage; and comparison means for comparing the output voltage of said integration means to a value corresponding to the mutual relative angular position suitable for commutation, and upon sensing equality generating atiming signal at the instant for commutation.

78. The combination setforth in claim 77 wherein said transconductance amplifier means comprises an input stage comprising two transistors, the control electrodes forming the inputs of said transconductance amplifier means, and a second and a third stage, the second stage being a current mirror, the output current of said first transistor being coupled to said second stage and the output current from said second transistor being coupled to said third stage; and wherein means are provided for periodically resetting said integration meanstoandinitialstatesuitablefor initiating the succeeding integration; and means are provided for periodically nulling the output current of said transconductance amplifier means, said nulling being timed to occur aftersaid instantforcommutation, but prior to resetting said integration means; said nulling means comprising means for incrementing the offset current of said current mirrorto a value which corrects imbalance in the output current of said transconductance amplifier means, and sustaining said corrective offset current until nulling again occurs.

79. The combination setforth in claim 76 or 78 wherein said nulling means comprises: meansfor zeroing the differential inputvoltage applied between said inputs of said transconductance amplifier means and for establishing a desired output current level in said first and second transistors of said input stage, amplifier output switching means for disconnecting the output of said transconductance amplifier means from said integration means during said nulling interval, and a nulling comparator coupled to the output of said transconductance amplifierfor detecting a change in sense of the output current, as the amplifier go6s through balance to terminate the incrementing process and initiate resetting of said integration means.

80. The combination setforth in claim 79 wherein said offset current incrementing means comprises: means for supplying a clocking signal having a period which is short in relation to the commutation period, and a nulling counter counting atthe rate of said clocking signal, the state of said nulling counter controlling the sum of the increments of offset current, said nulling counter being preset in response to said timing signal, subsequent counting during nulling adjusting said current offset toward balance until a null is detected by said nulling comparator.

81. The combination set forth in claim 80 wherein a low voltage DC supply is provided suitable for operation of said control circuit, the voltage of said supply changing ata finite rate when power to said control circuit is turned on orturned off, and a protection circuit is provided for producing an active output responsive to the voltage of said low voltage DC supply for holding at least a portion of said control circuit in an inactive state when said voltage is below a first value when power is turned on or below a second value when power is turned off, and when said voltage has exceeded said first value as power is turned on releasing said circuit portion at a predetermined initial state, said voltage values being set such that normal circuit operation is assured at supply voltages exceeding saidfirst and second values.

82. The combination set forth in claim 81 wherein said protection circuit, upon termination of said active output as power isturned on, releases said circuit portion in a state to null said amplifier means to ins re insure balanceoftheoutputcurrentofsaid amplifier means before integration of its output current.

83. The combination set forth in claim 82 wherein said protection circuit during said active output, presets said nulling counter, and upon termination of said active output, as power is turned on releases said circuit portion in a state for nulling said amplifier means, said statefornulling comprising: activation of said zeroing means at the input of said transconductance amplifier means, activation of said amplifier output switching means for disconnection, and releasing ofsaid nulling counter.

84. The combination setforth in claim 83 wherein said protection circuit comprises: means to cause a starting offset in the output current of said amplifier means to insure integration of said output current to a voltage sufficient for generation of said commutation timing signal, said starting offsetcurrent, except during said nulling interval(s), extending over a sufficient period after power is applied to allow control circuit stabilization.

85. Thecombinationsetforth in claim 84wherein said starting offset continues after power is turned on forat least one commutation period.

86. The method oftiming the commutation of an electronically commutated motor energized from a DC power source, said motor having a multistage winding assembly, and a magnetic assembly,thetwo arranged for mutual relative rotation, said motor in a given state of a multistate energization sequence, having an unenergized winding stage in which induced back emf appears which when integrated overtime to a predetermined value indicates the instant at which the mutual relative angular position has been attained suitable for commutation to the next state, comprising:: converting the voltage appearing atthe winding stage to a corresponding output current by means of a solid statetransconductance amplifier means coupled to an unenergizedwinding stage in the motor, integrating said output currentto obtain an output voltage substantially proportional to an integral of said voltage appearing in the winding stage by means of integration means coupled to the output of said amplifier means; and comparing the output voltage of said integration meanstoavaluecorrespondingtothe mutual relative angular position suitable for commutation, and upon sensing equality generating a timing signal atthe instant for commutation.

87. The method oftiming the commutation of an electronically commutated motor energized from a DCpowersource,said motorhavingamultistage winding assembly with a neutral connection, and a magnetic assembly, thetwo arranged for mutual relative rotation, said motor in a given state of a multistate energization sequence, having an unenergized winding stage in which an induced back emf appears which when intergrated overtime to a predetermined value indicates the instant at which the mutual relative angular position has been attained suitable for commutation to the next state, comprising:: converting the differential voltage appearing in the unenergized winding stage to a corresponding bidirectional output current by means of a two input solid state differential transconductance amplifier means having one input coupled to an unenergized winding stage, and the other input coupled to said neutral connection; integrating said output current to obtain an output voltage substantially proportional to an integral of the differential voltage appearing in the winding stage by means of an integration means coupled to the output of said amplifier means; and comparing the output voltage of said integration means to a value corresponding to the angular position of said rotor suitable for commutation, and upon sensing equality generating a timing signal at the instantforcommutation.

88. The method oftiming the commutation of an electronically commutated motor energized from a DC power source, said motor having a multistage winding assembly with a neutral connection, and a magnetic assembly, the two arranged for mutual relative rotation, said motor in a given state of a multistate energization sequence, having an unenergized winding stage in which an induced back emf appears which when integrated overtime to a predetermined value indicates the instant at which the mutual relative angular position has been attained suitable for commutation to the next state, comprising:: converting the differential voltage appearing in the unenergized windingstageto a corresponding bidirectional output current by means of a two input solid state differentiaitransconductance amplifier means havingone input coupled to an unenergized windingstage,andthe other input coupled to said neutral connection, integrating said output current to obtain an output voltage substantially proportional to an integral of the differential voltage appearing inthewirxling stage by means of integration means coupted tothe output of said amplifier means;; comparing the outputvoltage of said integration means to a value corresponding to the angular position of said rotorsuitableforcommutation, and upon sensing equality generating a timing signal at the instantforcommutation; resetting said integration means to an initial state suitable for initiating the succeeding integration subsequenttoeachtimingsignal; and periodically nulling the output current of said transconductance amplifier means, said nulling being timed to occur after said instantfor commuta tion, but prior to resetting said integration means.

89. The method of operating an electronically commutated motor energized from a DC power source, said motor having a multistage winding assemblywith a neutral connection, and a magnetic assembly,thetwo arranged for mutual relative rotation, said motor in a given state of a multistate energization sequence, having an unenergized winding stage in which an induced back emf appears, which when integrated over time to a predetermined value, indicates the instant at which the mutual relative angular position has been attained suitable for commutation to the next state, and having a differential transconductance amplifier means in the control circuitforsaid motor, said method comprising; nulling said amplifier means upon turning on powerforsaidcontrol circuit priorto turning power on forsaid motor;; converting the differential voltage appearing in the unenergized winding stage to a corrseponding bidirectional output current by means of a two input solid state differential transconductance amplifier means having one input coupled to an unenergized winding stage, and the other input coupled to said neutral connection, integrating said outputcurrentto obtain an output voltage substantially proportional to an integral of the differential voltage appearing in the winding state by means of integration means coupled to the output of said amplifier means; comparing the output voltage of said integration meansto a value correspondingtothe angular position of said suitableforcommutation, and upon sensing equality generating a timing signal atthe instant suitable for commutation;; applying power to said motor after a delay, in responseto the next or a subsequenttiming signal, selected to allow adequatetimeforsaid control circuitto stabilize; resetting said integration means to an initial state suitable for initiating the succeeding integration subsequent to each timing signal; and periodically nulling the output current of said transconductance amplifier means, said nulling being timed to occur after said timing signal, but prior to resetting said integration means.

90. In a motor speed control circuit for an electronically commutated motor adapted to be energized from a DC power source, said motor having a multistage winding assembly and a magnetic assembly, the two arranged for mutual relative rotation upon application of a multi-state energization sequence, the combination comprising:: power inputterminalsfor connection to supply suitable for motor operation; a waveform generator for supplying a repetitive low voltage waveform of substantially constant repetition rate, amplitude and configuration, said characteristics being substantially free of dependence on said motor, said waveform having a first slope of a first duration and a second slope of a second duration and of opposite sense to said first slope, and a repetition rate which is high in relation to the commutation rate; means for producing a substantially smooth adjustable control voltage;; a modulating comparator having a first inputto which said repetitive voltage waveform is supplied and a second input to which said adjustable control voltage is supplied, to produce output pulses when intersections occur between said inputs, said output pulses having an "active" on time equal to the interval between alternate pairs of intersections and occurring at said constant repetition rate; and control logic means responsive to the "active" on time of said modulator pulses for providing pulse width modulated signals for control ofthe energization ofthewinding stages in said multistate energization sequence whereby adjustment of said control voltage, adjuststhe active on time of each pulse andtherebythe rate at which electrical energy is supplied to the motorfordetermination of the motor speed or torque.

91. Ina motorspeedcontrolcircuitforan electronically commutated motor adapted to be energized from a DC power source, said motor having a multistage winding assembly, and a magnetic assembly, the two arranged for mutual relative rotation, said motor in a given state of a multistate energization sequence having an unenergized winding stage in which an induced back emf is integrated overtime to determine the instant at which the mutual relative angular position has been attained suitable for commutation to the next state, and wherein in said given state, a second winding stage is energized in a first sense, and a third winding stage is energized in a second sense inverse to said first sense for serial energization of said second and third winding stages, the combination comprising:: power inputterminalsforconnection to a supply suitable for motor operation; a waveform generator for supplying a repetitive low voltage waveform of substantially constant repetition rate, amplitude and configuration, said characteristics being substantially free of dependence on said motor, said waveform having a first slope of a first duration and a second slope of a second duration and of oppositesensetosaidfirst slope, and a repetition rate which is high in relation to the commutation rate; means for producing a substantially smooth adjustable control voltage; ; a modulating comparator having a first input to which said repetitive voltage waveform is supplied and a second inputto which said adjustable control voltage is supplied, to produce output pulses when intersections occur between said inputs said output pulses having an "active" on time equal to the interval between alternate pairs of intersections and occurring at said constant repetition rate; and control logic means responsive to the "active" on time of said modulator pulses for providing pulse width modulated signals for control ofthe energiza tion ofthe winding stages in said multistate energiza tion sequence whereby adjustment of said control voltage, ad justs the active on time of each pulse and therebythe rate atwhich electrical energy is supplied to the motorfordetermination ofthe motor speed or torque.

92. The combination set forth in claim 91 wherein the slope of any variation in said adjustable voltage is small in relation to the variations of said repetitive wave.

93. The combination setforth in claim 91 wherein the slope ofany variations in said adjustable voltage is small is in relation to the rate of motor commutation.

94. The combination setforth in claim 92 or 93 wherein said paired intersections embrace positive peaks of the repetitive voltage waveform and the modulator output pulses are essentially rectangular waves.

95. The combination setforth in claim 91 wherein the range of adjustment of said adjustable control voltage is comparabletothe amplitude of said repetitive voltage waveform to facilitate a large range of speed ortorque adjustment.

96. Thecombinationsetforthinclaim91wherein said adjustable control voltage has an adjustment range which, at one limit of adjustment, avoids intersection with said repetitive wave to cause said modulating comparatorto produce an output which is substantially always on or always off.

97. The combination setforth in claim 91 wherein said adjustable control voltage has an adjustment range which, atthe limits of adjustment avoids intersection with said repetitive wave to cause said modulating comparatorto produce an output which at one limit of adjustment is substantially always on and at the other limit of adjustment is substantially always off.

98. The combination set forth in claim 91 wherein said first adjustable control voltage has a range of adjustment overlapping the range of values of said repetitive wave to cause said modulating comparator to produce an outputwave which at one limit of adjustment is substantially always on, at the other limit is substantially always off, and at intermediate adjustments is pulsed.

99. The combination setforth in claim 91 wherein: the repitition rate of said repetitive wave is above audibility and belowthe value atwhich lowfrequency solid state switches exhibitsignificant switching losses.

100. The combination setforth in claim 91 wherein: the frequency of said repetitive wave is in excess of 20Khz.

101. The combination setforth in claim 100 wherein: said repetitive wave is a sawtooth wave whose first slope is of long duration and whose second slope is of short duration.

102. In a motor speed ortorque control circuitfor an electronically commutated motor adapted to be energized from a power source, said motor having a multistage winding assembly and a magnetic assem bly, the two arranged for mutual relative rotation upon application of a multi-state energization sequ ence, the combination comprising:: power input terminals for connection to a power supply suitable for motor operation; first adjustable voltage reduction means for serially connecting a load via said inputterminalsto the powersupply to provide a variable output voltage suitableforvariable torque orvariable speed motor operation; a low voltage supply suitable for energization of said speed control circuit, said low voltage de su pply comprising a second voltage reduction means for serially connecting said speed control circuitvia said first voltage reduction means and said power input terminals to the power supply; the speed or torque control circuit comprising:: a modulating comparator having afirstinputto which a repetitive low voltage waveform is supplied and a second input to which an adjustable control voltage is supplied, said control voltage changing as said variable outputvoltage decreases to produce output pulses having an active ontimewhich decreases as said adjustable control voltage de creases, said output pulses appearing when said repetitive voltage waveform and said adjustable voltage intersect, said output pulses occurring at said constant repetition rate and having an "active" on time equal to the interval between alternate pairs of intersections; control logic means responsive to the "active" on time of said modulator pulses for providing pulse width modulated signals for control of the energiza tion ofthe winding stages in said multistate energiza tion sequence;; load outputterminalsfor connection to the winding stages of said motor, and power switches responsive to said pulse width modulated signalsforconnecting the winding stages of the motor via said first adjustable voltage reduc tion means and via said power input terminals to the powersupplyforwinding energization in said multi state energization sequence, whereby upon operation of said first adjustable voltage reduction means, both the magnitude ofthe applied voltage and the active on time of the output pulsesofthepulsewidth modulatorarnsimul- taneously reduced.

103. In a motor speed ortorque control circuit for an electronically commutated motor adapted to be energizecifroma powersource,said motorhavinga multistage winding assembly and a magnetic assem bly, the two arranged for mutual relative rotation upon application of a multi-state energization sequ ence,the combination comprising:: power input terminals for connection to a power supply suitable for motor operation; first adjustable voltage reduction means for serially connecting a load via said inputterminals to the power supply to provide a variable output voltage suitableforvariabletorque orvariablespeed motor operation; a low voltage dc supply suitable for energization of said speed control circuit, said low voltage dc supply comprising a second voltage reduction means for serially connecting said speed control circuitvia said first voltage reduction means and said power input terminals to the power supply; the speed control circuit comprising:: a modulating comparator having a first input to which a repetitive lowvoltagewaveform is supplied and a second inputto which an adjustable control voltage is supplied, said control voltage, after an initial reduction in motor operating voltage which occasions no change, changing as said variable output voltage decreases to produce output pulses having an active on time which decreases as said adjustable control voltage decreases, said output pulses appearing when said repetitive voltage waveform and said adjustable voltage intersect, said output pulses occurring at said constant repetition rate and having an "active" on time equal to the interval between alternate pairs of intersections, control logic means responsive to the active on time of said modulator pulses four providing pulse width modulated signals for control of the energization ofthewinding stages in said multi-state energization sequence;; load outputterminals for connection to the winding stages of said motor, and power switches responsive to said pulse width modulated signals for connecting the winding stages of the motor via said first adjustable voltage reduction means and via first power inputterminals to the power supply for winding energization in said multistate energization sequence, whereby after said initial reduction by operation of said first adjustable voltage reduction means, both the magnitude of the applied voltage and the active on time of the pulse width modulator are simultaneously reduced.

106. In a motor speed ortorque control circuitfor an electronically commutated motor adapted to be energized from a power source, said motor having a multistage winding assembly, and a magnetic assembly,thetwo arranged for mutual relative rotation, said motor in a given state of a multistate energization sequence having an unenergized winding stage in which an induced back emf is intergrated over time to determine the instant at which the mutual relative angular position has been attained suitableforcommutation to the next state, and wherein in said given state at least one otherwinding stage is energized in the appropriate sense to cause relative rotation, the combination comprising:: power inputterminals for connection to a power supply suitablefor motor operation; first adjustable voltage reduction meansfor serially connecting a load via said inputterminalsto the power supply to provide a variable output voltage suitableforvariabletorque orvariablespeed motor operation; a low voltage dc supply suitable for energization of said speed control circuit, said lowvoltagedosupply comprising a second voltage reduction means for serially connecting said speed control circuit via said firstvoltage reduction means and said power input terminalstothe power supply; the speed control circuit, comprising:: a waveform generatorfor supplying a repetitive low voltage waveform of substantially constant repetition rate, amplitude and configuration, said characteristics being substantially free of dependence on said motor, said waveform having a first slope of a first duration and a second slope of a second duration and of opposite sense to said first slope, and a repetition rate which is high in relation to the commutation rate, means for producing an adjustable, substantially smooth control voltage, a modulating comparator having afirstinputto which said repetitive lowvoltagewaveform is supplied and a second input to which said adjustable voltage is supplied, to produce output pulses when intersections occur between said repetitive low voltage waveform and said adjustable voltage, said output pulses occurring at said constant repetition rate and having an "active" on time equal to the interval between alternate pairs of intersections; control logic means responsive to the "active" on time of said modulator pulses for providing pulse width modulated signalsforthewinding stages in said multistate energization sequence; load outputterminals for connection to the winding stages of said motor, and power switches responsive to said pulses width modulatedsignalsforconnectingthewinding stages of the motorvia said first adjustable voltage reduction means and said power input terminals to the power supply for winding energization in said multistate energization sequence.

105. The combination setforth in claim 104, whereinthe meansforproducing said adjustable control voltage comprises a voltage divider with a movable tap, the divider being connected across said low voltage dc supply, and the movable tap being connected to the second input of said modulating comparator whereby said first adjustable voltage reduction means or said adjustable tap provides adjustment of motortorque or speed.

106. The combination setforth in claim 104 wherein voltage stabilizing means is provided for said lowvoltagedcsupply,and the means for producing said adjustable control voltage comprises means for deriving a voltage dependent on said variable output voltage sensed to decrease the active on time of said PWM pulses as said variable output voltage is reduced.

107. The combination setforth in claim 104 wherein voltage stabilizing means are provided for said low voltage dc supply, and the means for producing said adjustable control voltage comprises solid state means for deriving a voltage which after an initial reduction in said variable outputvoltage, which occasions no change in said controlvoltage, changeswith additional decreases in said variable output voltage in a sense to reducethe active on time of said pulse width modulated pulses.

108. The combination setforth in claim 106 or 107 wherein the means for producing said adjustable control voltage comprises a voltage divider with a movaable tap, the voltage divider being connected across said lowvoltage desupply, and the tap being connected to the second input of said modulating comparator, the setting of said movable tap setting the maximum motortorque or speed, and the setting of said first adjustable voltage reduction means reducing the speed ortorque below the maximum setting.

109. The combination setforth in claim 107 wherein said solid state means comprises, a voltage dividerwith an outputtap across which said variable output voltage is applied, and a transistor having the emitter connected to one terminal of said low voltage dc supply, the base connected to the output tap of sa id voltage divider, and the collector coupled to the second input of said modulating comparator.

110. The method of controlling the speed or torqueofan electronicallycommutated motorensr- gizedfrom a powersource,saidmotorhaving a multistage winding assembly, and a magnetic assembly,thetwo arranged for mutual relative rotation, said motor in a given state of a multistate energization sequence having an unenergizedwind- ing stage in which an induced back emf is integrated overtime to determine the instant at which the mutual relative angular position has been attained suitableforcommutationtothe next state, and wherein in said given state, at least one otherwinding stage is energized in the appropriate sense to cause relative rotation,comprising generating a repetitive low voltage waveform of substantially constant repetition rate, amplitude and configuration, said characteristics being substantially free of dependence on said motor, said waveform having a first slope of a first duration and a second slope of a second duration and of opposite sense to said first slop, and a repetition rate which is high in relation to the commutation rate;; adjusting a substantially smooth control voltage for speed ortorque control comparing said repetitive voltage waveform to said adjustable control voltage in a modulatorto produce output pulses when intersections occur between said inputs, said output pulses occurring at said constant repetition rate and having an "active" on time equal to the interval between alternate pairs of intersections; and providing pulse width modulated signals during the active on time of said modulator pulses for control of the electrical energy supplied in the energization of the winding stages in said multistate energization sequence.

111. The method of controlling the speed or torque of an electronically commutated motorenergizedfrom a powersource,said motor having a multistage winding assembly, and magnetic assembly, the two arranged for mutual relative rotation, said motor in a given state of multistate energization sequence having an unenergized winding stage in which an induced back emf is integrated overtimeto determine the instant at which the mutual relative angular position has been attained suitable for commutation to the next state, and wherein in said given state at least one other winding stage is energized in the appropriate sense to cause relative rotation, comprising providing a variable output voltage suitableforvariable speed or variable torque motor operation by means of an adjustable voltage and reduction means serially connecting said motor to said power source; generating a repetitive lowvoltagewaveform of substantially constant repetition rate, amplitude and configuration, said characteristics being substantially free of dependence on said motor, said waveform having a first slope of a first duration and a second slope of a second duration and of opposite sense to said firstslope, and a repetition rate which is high in relation to the commutation rate;; providing an adjustable substantially smooth con trolvoltageformotorspeed ortorque control and comparing said repetitive voltage waveform to said adjustable control voltage in a modulatorto produce output pulses when intersections occur between said inputs, said output pulses occurring at said constant repetition rate and having an "active" on time equal to the interval between alternate pairs of intersections; applying energy from said power source to said motor during the active on time of said modulator pulses; and selectively adjusting said variable output voltage or said adjustable control voltage for motor speed ortorque control.

112. The method of controlling the speed or torque of an electronically commutated motorener gizedfrom a powersource,said motor having a multistage winding assembly, and a magnetic assembly, the two arranged for mutual relative rotation, said motor in a given state of a multistate energization sequence having an unenergized winding stage in which an induced back emf is integrated overtime to determine the instant at which the mutual relative angular position has been attained suitable for commutation to the next state, and wherein in said given state at least one other winding stage is energized in the appropriate sense to cause relative rotation, comprising providing a variable output voltage suitable for variable speed or variable torque motor operation by means of an adjustable voltage reduction means serially connecting said motor to said power source generating a repetitive lowvoltagewaveform of substantially constant repetition rate, amplitude and configuration, said characteristics being substantially free of dependence on said motor, said waveform having a first slope of a first duration and a second slope of a second duration and of opposite sense to said first slope, and a repetition rate which is high in relation to the commutation rate;; providing an adjustable substantially smooth control voltage for motor speed ortorque control and comparing said repetitive voltage waveform to said adjustable control voltage in a modulatorto produce output pulses when intersections occur between said inputs, said output pulses occurring at said constant repetition rate and having an "active" on time equal to the interval between alternate pairs of intersections; applying energy from said power source to said motor during the active on time of said modulator pulses; and simultaneously adjusting said variable output voltage and said adjustable control voltage for motor speed or torque control.

113. The method of controlling the speed or torque of an electronically commutated motor energized from a power source, said motor having a multistage winding assembly, and a magnetic assembly, the two arranged for mutual relative rotation, said motor in a given state of a multistate energization sequence having an unenergized winding stage in which an induced back emf is integrated overtime to determine the instant at which the mutual relative angular position has been attained suitable for commutation to the next state, and wherein in said given state at least one other winding stage is energized in the appropriate sense to cause relative rotation, comprising providing a variable output voltage suitable for variable speed orvariabletorque motor operation by means of an adjustable voltage reduction means serially connecting said motor to said power source;; generating a repetitive lowvoltagewaveform of substantially constant repetition rate, amplitude and configuration, said characteristics being substantially free of dependence of said motor, said waveform having a first slope of a first duration and a second slope of a second duration and of opposite sense to said first slope, and a reputation rate which is high in relation to the commutation rate; providing an adjustable substantially smooth control voltage for motor speed ortorque control and comparing said repetitive voltage waveform to said adjustable control voltage in a modulatorto produce output pulses when intersections occur between said inputs, said output pulses occurring at said constant repetition rate and having an "active" on time equal to the interval between alternate pairs of intersections;; applying energyfrom said powersourceto said motor during the active on time of said modulator pulses; and adjusting only said variable output voltage for a small reduction in motor speed ortorque, and for a further reduction simultaneously adjusting said variable output voltage and said control voltage for motor speed or torque control.

114. In a motor control circuitfor an electronically commutated reversible motor adapted to be energized from a power source, said motor having a multistage winding assembly, and a magnetic assembly, the two arranged for mutual relative rotation, said motor in a given state of a multistate energization sequence having an unenergized wind ingstageinwhichaninduced backemfisintegrated overtime to determine the instant at which the mutual relative angular position has been attained suitable for commutation to the next state of sequence, and wherein in said given state at least one other winding stage is energized in the appropriate sense to cause relative rotation, the combination comprising power inputterminals for connection to a power supply suitablefor motor operation;; first adjustable voltage reduction means for serially connecting a motorvia said inputterminals to the power supply to provide a variable output voltage suitable for variable speed ortorque operation; means for producing a substantially smooth control voltage dependent on said variable output voltage, said control voltage, upon passing through an intermediate value corresponding to a useful limit of said adjustable means, continuing monotonically toward afinal value, and means responsive to a value of said control voltage between said intermediate and final values for generating a signal for changing the direction of motor rotation.

115. The combination set forth in claim 114 wherein said intermediate value of control voltage corres pondstothe desired minimum motor speed or rque, said change in direction occurring toward minimum output voltage.

116. The combination setforth in claim 114 wherein said intermediate value of control boltage corres pondsapproximatelyto motorstalling,saidchange in direction occurring toward minimum output voltage.

117. Thecombinationsetforthinclaim 116 wherein means are provided to interrupt energization of said motorforashorttimewhen the direction of rotation is changed.

118. In a motor control circuitforan electronically commutated reversible motor adapted to be energized from a power source, said motor having a multistage winding assembly, and a magnetic assembly, the two arranged for mutual relative rotation, said motor in a given state of a multistate energization sequence having an unenergized winding stage in which an induced back emf is integrated overtime to determine the instant at which the mutual relative angular position has been attained suitable for commutation to the next state of the sequence, and wherein in said given state at least one other winding stage is energized in the appropriate sense to cause relative rotation, the combination comprising power inputterminalsfor connection to a power supplysuitablefor motor operation; ; first adjustable voltage reduction means for serially connecting a motorvia said inputterminalsto the power supply to provide a variable output voltage suitableforvariable speed or torque operation; means for producing a substantially smooth control voltage dependent on said variable output voltage, said control voltage, upon passing through an intermediate value corresponding to a minimum useful setting of said adjustable means, continuing monotonicallytoward a finial value, and control logic means comprising energy control means responsive to said control voltage for adjustment of the rate at which electrical energy is supplied form the supplyto the motorfor determining motor speed or torque, and motor direction control means responsive to a value of said control voltage between said intermediate andfinal values to generate a signal forchanging motor direction.

119. In a motor control circuitforan electronically commutated reversible motor adapted to be energized from a powersource, said motor having a multistage winding assembly, and a magnetic assembly, the two arranged for mutual relative rotation, said motor in a given state of a multistate energization sequence having an unenergized winding state in which a induced back emf is integrated overtime to determine the instant at which the mutual relative angular position has been attained suitable for commutation to the next state of the sequence, and wherein in said given state at least one otherwinding stage is energized in the appropriate sense to cause relative rotation, the combination comprising power input terminals for connection to a power supply suitable for motor operation;; first adjustable voltage reduction means for serially connecting a motor via said input terminals to the powersupplyto provide a variable outputvoltage suitable forvariable speed ortorque operation; means for producing a substantially smooth control voltage dependent on said variable output voltage, said control voltage, upon passing through an intermediate value, continuing toward a final value, and control logic means comprising a pulse width modulator responsive to said control voltage for adjustment ofthe rate at which electrical energy is supplied from the supply to the motorfor determining motor speed or torque, and motordirection control means responsive to a value ofsaid control voltage between said intermedi ate and final valuesto generate a control signal for changing motor direction.

120. The combination setforth in claim 119 wherein said pulse width modulator produces output pulses ofconstant repetition rate, said repetition rate being high in relation to the commutation rate, said electrical energy being supplied to the motorduring the active on time of said pulses.

121. The combinationsetforthin claim 120 wherein a portion of said control circuit is energized by said output voltage and requires a predetermined value for proper operation, and wherein said pulse width modulator produces a reduction in active on time of said pulses adequate to produce a minimum desired motor speed ortorque before said output voltage falls below said predetermined value.

122. The combination setforth in claim 120 wherein a portion of said control circuit is energized by said output voltage and requires a predetermined value for proper operation, and wherein said pulse width modulator produces a reduction in active on time of said pulses substantially adequate to produce motor stalling before said output voltage falls below said predetermined value.

123. In a motor control circuitforan electronically commutated reversible motor adapted to be energizedfrom a power source, said motor having a multistage winding assembly, and a magnetic assembly, the two arranged for mutual relative rotation, said motor in a given state of multistate energization sequence having an unenergized winding stage in which an induced back emf is integrated overtime to determine the instant at which the mutual relative angular position has been attained suitable for commutation to the next state of the sequence, and wherein in said given state at least one other winding stage is energized in the appropriate sense to cause relative rotation, the combination comprising power inputterminals for connection to a power supply suitable for motor operation;; first adjustable voltage reduction means for serially connecting a motor, and a portion of said control circuit connected in parallel with said motor, via said input terminals to the power supply to provide a variable output voltage suitable for variable speed or torque operation ofthe motor, the minimum output voltage being adequate for control circuit energization, means for producing a substantially smooth control voltage dependent on said variable output voltage, said control voltage, upon passing through an intermediate value corresponding to a minimum useful setting of said adjustable means, continuing monotonicallytoward a final value, and control logic means comprising energy control means, including a pulse width modulator responsive to said control voltage for producing output pulses of constant repetition rate, said repetition rate being high in relation to the commutation rate, the energy being supplied to the motor during the active on time of said pulses, being reduced at said intermediate value of said control voltage too produce the minimum desired motor speed and torque, and motor direction control means responsive to a value of said control voltage between said intermediate and final values to generate a control signal for changing motor direction.

124. The combination set forth in claim 123 wherein said pulse width modulator comprises a waveform generatorforsupplying a repetitive low voltage waveform of substantially constant repetition rate, amplitude and configuration, said characteristics being substantially free of dependence on said motor, said waveform having a first slopeofafirstduration and a second slope of a second duration and of opposite sense to said first slope, and a repetition rate which is high in relation to the commutation rate; and a modulating comparator having a first inputto which said repetitive voltage waveform is supplied and a second input to which said adjustable control voltage is supplied, to produce output pulses when intersections occur between said inputs, said output pulses occurring at said constant repetition rate, and having an "active" on time equal to the interval between alternate pairs of intersections.

125. The combination setforth in claim 124 wherein said motor direction control means comprises a reversing comparator having a first input to which said adjustable control voltage is supplied, and a second input to which a voltage reference is supplied having a value between said intermediate and final values, said reversing comparator in responseto equality between inputs, generating a signal for a change in the direction of motor rotation.

126. In a motor control circuitfor an electronically commutated reversible motor adapted to be energized form a power source, said motor having a multistage winding assembly, and a magnetic assembly, the two arranged for mutual relative rotation, said motor in a given state of a multistate energization sequence having an unenergized winding stage in which an induced back emf is integrated overtime to determine the instantatwhich the mutual relative angular position has been attained suitable for commutation to the next state ofthe sequence, and wherein in said given state at least one other winding stage is energized in the appropriate sense to cause relative rotation, the combination comprising:: power inputterminalsforconnection to a power supply suitable for motor operation; first adjustable voltage reduction means for serially connecting a motor, and a portion of said control circuit connected in parallel with said motor, via said inputterminalstothe powersupplyto provide a variable output voltage suitable for variable speed or torque operation ofthe motor, the minimum output voltage being adequate for control circuit energization;; means for producing a substantially smooth control voltage dependent on said variable output voltage, said control voltage, upon passing through an intermediate value, continuing toward a final value, and control logic means comprising energy control means, including a pulse width modulator responsive to said control voltage for producing output pulses of constant repetition rate, said repetition rate being high in relation to the commutation rate, the energy being supplied to the motor during the active on time of said pulses, being reduced at said intermediate value of said control voltage to produce the minimum desired motor speed and torque, and motor direction control means having a first input coupled to a reversing comparatorfor response to a value of said control voltage between said intermediate and final valuesfor generating a signal for changing the direction of motor rotation, and a second input coupled to a switch for generating a signal for controlling the direction of motor rotation.

127. The combination setforth in claim 1 18or 126 wherein means are provided to interruptenergization of said motorfor a shorttime when the direction of rotation is changed.

128. The combination setforth in claim 125 or 126 wherein solid state switching means are provided for serially connecting said winding stages via said input terminalstothe power supply, said switching means conducting to energize said winding stages in one energization sequence, and wherein means are provided to interrupt conduction of said switches for a short period adequate to turn off said switch(es), when the direction of motor rotation is changed, before energization of said winding stages in another energization sequence.

129. The combination setforth in claim 128 wherein said conduction interruption period is derived from said waveform generator, and exceeds one period of said repetitive low voltage waveform.

130. The combination setforth in claim 128 wherein said motor direction control means has a dual output one output having an active stateforfacilitating clockwise motor rotation, and a second output having an active stateforfacilitating counterclockwise motor rotation, the two active outputs states never occurring simultanelously and wherein said means for interrupting conduction of said switch, produces said interruption by maintaining both output states inactive forthe interruption period.

131. Thecombinationsetforthinclaim 130 wherein second voltage reduction means is provided, coupling the portion of said control circuit in parallel with said motorvia said inputterminalstothesupply, and establishing lowvoltage de supplyfor said control circuitportion,the voltage of said low voltage dc supply changing at a finite rate when power is applied or removed; and a protection circuit producing an output responsive to the voltage of said lowvoltage dc supply and when saidvoltage has exceeded afirstvalue as power is turned on, releasing said motor direction control means in an output state determined by setting of said switch, said first value being set such that normal circuit operation is assured at low voltage supply voltages exceeding said value.

132. The method of controlling an electronically commutated reversible motor energized from a power source, said motor having a multistage winding assembly, and a magnetic assembly, the two arranged for mutual relative rotation, said motor in a given state of a multistate energization sequence having an unenergized winding stage in which an induced back emf is integrated over time to determine the instant at which the mutual relative angular position has been attained suitable for commutation to the next state ofthe sequence, and wherein in said given state at least one otherwinding stage is energized in the appropriate sense to cause relative rotation, comprising reducing the output voltage supplied to the motor through a range of values suitable for variable speed ortorque operation, producing a substantially smooth control voltage dependent on said variable output voltage, said control voltage, upon passing through an intermedi atevalue corresponding to a minimum useful reduction, continuing monotonicallytoward a final value, and generating a signal for changing the direction of motor rotation art a value of the control voltage between said intermediate and final values.

133. The method ofcontrolling an electronically commutated reversible motor energized from a powersource,said motor having a multistage winding assembly, and a magnetic assembly, the two arranged for mutual relative rotation, said motor in a given state of a multistate energization sequence having an unenergized winding stage in which an induced back emf is integrated over time to determine the instant at which the mutual relative angular position has been attained suitableforcommutation to the next state ofthe sequence, and wherein in said given state at least one otherwinding stage is energized in the appropriate sense to cause relative rotation, comprising reducing the output voltage supplied to the motor through a range of values suitable for variable speed ortorque operation, by means of a first adjustable voltage reduction means serially connecting the motorto a power supply producing a substantially smooth control voltage dependent on said variable output voltage, said control voltage, upon passing th rough an intermediate value corresponding to a minimum useful setting of said adjustable means, continuing monotonically toward a final value, and generating a signal for changing the direction of motor rotation at a value of the control voltage between said intermediate and final values.

134. The method of controlling an electronically commutated reversible motor energized from a power source, said motor having a multistage winding assembly, and a magnetic assembly, the two arranged for mutual relative rotation, said motor in a given state of a multistate energization sequence having an unenergized winding stage in which an induced back emf is integrated overtimeto determine the instant at which the mutual relative angular position has been attained suitable for commutation to the next state ofthe sequence, and wherein in said given state at least one other winding stage is energized in the appropriate sense to cause relative rotation, comprising reducing the output voltage supplied to the motor through a range of values suitable for variable speed or torque operation by means of a first adjustable voltage reduction means serially connecting the motor to a power supply producing a substantially smooth control voltage dependent on said variable output voltage, said control voltage, upon passing through an intermediate value, continuing monotonically toward a final value, enhancing the rate of downward adjustment in energy per unit change in output voltage supplied to the motor and thereby reducing said range of values by means of a pulse width modulatorforproducing output pulses of high repetition rate in relation to the commutation rate whose on time, during which energy is supplied to said motor, is responsive to said control voltage, said intermediate values correspond ing to a minimum useful setting of said adjustable means, and generating a signal for changing the direction of motor rotation at a value ofthe control voltage between said intermediate and final values.

135. The method of controlling an electronically commutated reversible motor energized from a power source, said motor having a multistage winding assembly, and a magnetic assembly, the two arranged for mutual relative rotation, said motor in a given state of a multistateenergization sequence having an unenergized winding stage in which an induced back emf is integrated overtime to determine the instant at which the mutual relative angular position has been attained suitableforcommutation to the next state ofthe sequence, and wherein in said given state at least one otherwinding stage is energized in the appropriate sense to cause relative rotation, comprising reducing the output voltage supplied to the motor through a range of values suitable forvariable speed ortorque operation by means of a first adjustable voltage reduction means serially connecting the motorto a power supply producing a substantially smooth control voltage dependent on said variable output voltage, said control voltage, upon passing through an intermedi atevalue,continuing monotonicallytoward afinal value, enhancing the rate of downward adjustment in energy per unitvoltage supplied to the motor and thereby reducing said range of values by means of a pulse width modulatorfor producing output pulses at high repetition rate in relation to the commutation rate whose on time, during which energy is supplied to said motor, is responsive to said control voltage, said intermediate values corresponding to a minimum useful setting of said adjustable means, generating a signal forsuspendingthe energization for motor rotation in one sense at a value of the control voltage between said intermediate and final values, and after a short interruption for protection of motor switches, generating a signal for motor rotation in an opposite sense.