GB2177272A

GB2177272A - Reversing electric motors

Info

Publication number: GB2177272A
Application number: GB08619590A
Authority: GB
Inventors: William Kenneth Guzek; Ricky Francis Bitting; William Peil; Thomas Alfred Brown
Original assignee: General Electric Co
Current assignee: General Electric Co
Priority date: 1983-06-09
Filing date: 1986-08-12
Publication date: 1987-01-14
Also published as: IT8421302A1; FR2547962B1; GB2177559B; GB2177272B; GB2141888A; GB2141888B; FR2547962A1; IT1176288B; GB8619590D0; GB2177559A; GB8411736D0; IT8421302A0; GB8619589D0

Abstract

The forward/reverse logic responds to a controlled reduction of the supply due to a speed control so that upon reduction to a set value, below a threshold corresponding to the stalled motor condition, the logic causes the direction of rotation to reverse. For an electronically commutated motor, when the speed control input (P 14) falls below a threshold (VREF9), a bistable arrangement (D13, D14) changes state so as to invert the counting sequence of the control circuit and reverse the motor which will recommence rotation in that direction upon increase of the speed control beyond the stall position. The device may be used in a control for a ceiling fan. <IMAGE>

Description

1 GB2177272A 1

SPECIFICATION

Electronically commutated motors This invention relates in general to domestic appliances powered by an electronically com mutated motor (ECIVI), a method of operating an ECK and more particularly to a control circuit for an ECIVI. The invention further re lates to control circuits for ECMs suited to fabrication in solid state electronic form to a large degree utilizing monolithic integrated cir cuitry, to integrated circuits having application to such control circuits for ECIVI motor pow ered appliances, and to an ECIVI powered vari able speed fan incorporating such control cir cuitry.

Control circuits for electronically commu tated motors have hitherto been fabricated us ing discrete electronic components, and yet the desirability of fabricating such control cir cuits in solid state electronic form, to a large degree utilizing monolithic integrated circuitry, is widely honored in discussions among elec trical industry spokesmen if not by an equally wide presence of products incorporating such monolithic integrated circuitry in the actual market place.

The electronically commutated motors for which such control circuitry would have appli- 95 cation is exemplified by those ECIVIs disclosed in U.S. Patent Nos. 4,005,347 and 4,169,990 to David M. Erdman, and U.S. Patent No.

4,162,435 to Floyd H. Wright. These motors are characterized by having a multistage wind- 100 ing assembly, and a magnetic assembly, the two arranged for mutual relative rotation, the motor in a given state of a multistate energi zation sequence, having an unenergized wind ing stage in which an induced back emf ap- 105 pears, which when integrated over time to a predetermined value indicates the instant at which the mutual relative angular position has been attained suitable for commutation to the next state. In the most common examples, the multistage winding assembly is stationary, with the magnetic assembly arranged within the winding assembly, and arranged to rotate with respect to the immediate environment by means of bearings attached to a frame, me- 115 chanically common with the winding assembly. The mechanically opposite arrangement in which the winding asembly rotates within the magnetic assembly is less common, but makes many of the same requirements of the 120 control circuitry, and in general the control circuitry has equal application to such motors. In addition, the more common, magnetic assembly in such motors is a permanent mag- netic assembly. However, an arrangement in 125 which the magnetic assembly is electromag netic makes many of the same requirements of the control circuitry, and in general, the control circuitry has equal application to such motors.

The common requirements of the control circuitry for electronically commutated motors, may be divided into four ca, tegories, which in a sense, place differing requirements upon their fabrication. The appliance is installed in the house, and controls located when practical in the appliance, and when not practical, located at wall locations convenient to the user. In the practical case of a combined ceiling fan, lighting fixture, which is the practical product exemplified herein, the "fan" includes a motor, a light and user operated controls for the same. The controls are both integral with the lighting fixture and remote. The remote control may be located upon a convenient wall location and it may embody largely duplicate user operated controls. The usual functions of the user operated controls include turning on or turning off the fan or light, regulating the in- tensity of the light, regulating the speed of rotation, or direction of rotation of the fan.

The user operated controls, particularly those on the wall controls, are themselves constructed similarly to other wiring devices used in the home, and they are interconnected by electrical cable typical of the customary 110 AC house wiring. In general, the requirement placed upon such "control systems" is that the interconnections by minimal, and if possible not require additional special wiring. Ideally, the wiring installation would permit complete communication within the "control systems" by the minimum two wire cable. Ideally, the user operated control circuitry exemplified herein should require no more than two wires between the wall control, the fixture, and the house wiring for minimum installation expense. In this category, the control circuit is fabricated in the form typical of house wiring systems.

A second category of electrical control circuit fabrication is utilized within the enclosure of the ceiling fixture or of the wall control. This usually is "point to point" wiring, and the electrical connections are made with mechanical bonds, including solder, rivets, or electrical terminals. Here, the stress is often upon compactness, and ease of on-site assembly.

A third category of electrical control circuit fabrication, which is often practiced in the fixture itself or in the wall control, is that which is usually performed in the factory, and which is called "printed circuit board" (PCB) wiring. This wiring is of moderate density, and allows for ampere level currents, voltages in excess of the customary house level voltages (120-240, etc.), and heat dissipation levels comparable to the needs of the customary home appliances. This wiring is used to interconnect-by a factory process, discrete electronic components, such as resistors, capacitors, inductors, discrete solid state devices, such as transistors, diodes, diacs, triacs, SCRs, etc. on the printed circuit board.

2 GB2177272A 2 When the control application of the control circuitry is as complicated as the provision of electronic commutation of an ECM motor and,the imposition of user operated controls, and automatic protection functions incidental to user operated controls, then the complexity of the control function required of the control circuitry tends to transcend the practical limits of fabrication by the assembly of discrete electri- cal components upon a printed circuit board. In the printed circuit mode of fabrication for such control circuitry,the volume weight, and costs of printed circuit fabrication are greater by a factor of at least a hundred, and often by a factor of a thousand times the comparable measure of a circuit of monolithic integrated circuit fabrication of like complexity.

The thrust of these practical considerations upon control circuit fabrication is to perform all of the control functions that can be performed, taking into account the limitations on allowable current levels, voltage levels and power dissipations, with monolithic integrated circuitry.

Present day limitations upon the application 90 of integrated circuitry are less restrictive than some time ago, and more restrictive than one would expect some time in the future. In gen eral, circuitry complexity required for the con- trol function herein contemplated can be 95 handled with MSI (Medium Scale Integration) or LSI (Large Scale Integration). In the usual case, the component count of the motor con trol system is on the order of 102 to 103.

The current, voltage and power dissipations ordinarily dictate special interfacing circuits between the monolithic integrated circuit and the user operated controls, the motor, the light and the power mains. In general, this dictates that voltages applied to the IC not exceed the voltage rating of the integrated circuit process, typically from 5 to 40 volts, that currents should not exceed tens of milliamperes and that power dissipation not exceed 100s of milliwatts. Because of voltage limitations, it is 110 necessary to use voltage dividers coupled to the winding stages of the motors to reduce the back emf sensed on the winding stages to several volts (e.g. about 3 volts) before appli- cation to the integrated circuit. Similarly, the control of power to the winding stages of the motor requires current and power dissipation levels that can only be performed by discrete solid state switches. The integrated circuit, accordingly, has terminal pads supplied by internal drivers, with the power to control either directly or through additional buffers, the solid state power switches energizing the winding stages of the motor. A similar practical prob- lem relates to the non-integrable components, which are primarily large capacitors, inductors, and the user operated controls. These may usually be coupled to the pads of the monolithic -integrated circuit with no other transition than the terminal pads of the integrated circuit and a demountable 16 pin connection on the printed circuit board.

There is a need to use a standard package with ICs in order to keep the cost minimum.

This is typically 16 pins. There is also a need to keep outboard of the IC, components which control parameters which may change from product to product such as the inertia of the fan blades. In other words, the IC must be able to adapt to expected changes and must use a standard low cost package. Some components which could be integrated are sometimes not put in the IC for these good engineering reasons.

To date, "maximally" monolithically integrated control circuits for electronically commutated motors are not in common use in the market place.

Summary of the Invention

Accordingly, it is an object of the present invention to provide a maximally monolithically integrated control circuit for an electronically commutated motor.

It is another object of the invention to provide an improved control circuit for an electronically commutated motor.

It is still another object of the invention to provide a control circuit for an electronically commutated motor with improved commutation.

It is an additional object of the invention to provide a control circuit for an electronically commutated motor with improved speed or torque control.

It is a further object of the invention to provide a control circuit for an electronically commutated motor with improved reversing.

It is another object of the invention to pro- vide a control circuit for an electronically commutated motor with improved starting performance.

It is an additional object of the invention to provide a control circuit for an electronically commutated motor in which the commutation timing circuitry is improved.

It is a further object of the invention to provide a control circuit for an electronically commutated motor in which starting performance is improved.

It is another object of the invention to provide in a control circuit for an electronically commutated motor, a commutation timing circult that is self balancing.

It is an additional object of the invention to provide an improved control circuit for an electronically commutated motor combining reversal of the motor with speed/torque control.

It is another object of the invention to pro- vide a circuit for reversing an electronically commutated motor providing means for protecting the power switches during reversal.

It is another object of the invention to provide an improved integrated control circuit for an electronically commutated motor.

3 GB2177272A 3 It is still another object of the invention to provide an integrated control circuit for an electronically commutated motor with im proved commutation.

It is an additional object of the invention to 70 provide an integrated control circuit for an electronically commutated motor with im proved speed or torque control.

It is a further object of the invention to pro- vide an integrated control circuit for an elec- 75 tronically commutated motor with improved reversing.

It is another object of the invention to pro vide an integrated control circuit for an elec tronically commutated motor with improved starting performance.

It is an additional object of the present in vention to provide a maximally integrated con trol circuit for an electronically commutated motor, providing economical remote control.

It is a further object of the invention to pro vide an improved method of operating an electronically commutated motor.

It is an additional object of the invention to provide an improved method of timing the commutation of an electronically commutated motor.

It is another object of the invention to pro vide a method of improving the starting oper ation of an electronically commutated motor.

It is a further object of the invention to pro vide an improved method of controlling the speed or torque of an electronically commu tated motor.

It is another object of the invention to pro- 100 vide an improved method of remotely control ling the speed or torque of an electronically commutated motor.

It is a further object of the invention to pro- vide an improved method of reversing an elec- 105 tronicaily commutated motor.

It is another object of the invention to provide an improved method of control of an electronically commutaed motor combining reversing with speed/torque control.

These as well as other objects of the invention will be dealt with in the description which follows. They are achieved in a control circuit for an electronically commutated motor adapted to be energized from a DC power source, the motor having a three stage winding assembly, and a magnetic assembly, the two arranged for mutual relative rotation. In a given state of a six state energization se- quence causing relative rotation, the motor has one winding stage energized in one sense, a second winding stage energized in an opposite sense and serially connected with the first winding stage, and a third winding stage un- energized.

The inventive combination comprises input terminal means for connection to the winding stages and to the neutral motor connection or equivalent for deriving the back emf induced in successive unenergized winding stages, input switching means for selecting an unenergized winding stage responsive to an unenergized winding-stage selection signal; a two input, differential transconductance amplifier means for conversion of the voltage supplied to a corresponding current; capacitive integration means for providing a voltage substantially proportional to the integral of the back emf; and timing comparison means for comparing the voltage at the integration means to a value suitable for commutation, and upon sensing equality generating a timing signal at the instant for commutation.

Continuing, the inventive combination in- cludes control logic means for generating winding stage selection signals in a first six state sequence for forward motor rotation, and in a second six state sequence for reverse rotation, in each state of which a signal is generated for selecting one winding stage for energization in one sense, a signal is generated for selecting one winding stage for energization in the other sense, and a signal is generated for selecting an unenergized winding stage for selecting an unenergized winding stage for sensing the induced back emf, the motor energization state changing in response to the timing signal at the instant for commutation to the next state in the sequence. The control logic means is responsive to a direction control signal for selection of the first or second energization sequence and to an energy control signal in a form including periodic pulse width modulated (PWMed) pulses, having a repetition rate which is high in relation to the commutation rate, winding stage energization occurring only during the active on time of the pulse of the energy control signals.

The inventive combination also includes a three-fold plurality of power switching means responsive to the winding stage energization signals for appropriately sensed energization of the winding stages in the multistate se- quences.

In accordance with another facet of the invention means are provided for periodically resetting the integration means to an initial state suitable for initiating the succeeding integra- tion; and for periodically nulling the output current of the amplifier means, the nulling being timed to occur after the instant for commutation, but prior to reset. The nulling means comprising means for incrementing an offset current at the input of the amplifier means to a value which corrects imbalance in the output current, and means for sustaining the corrective offset current until nulling again occurs. Typically the nulling occurs once per commu- tation.

The input to the differential amplifier is coupled from the individual winding stages and the neutral connection by means of a four part voltage divider for scaling down the in- duced back emf to a value that the control 4 GB2177272A 4 circuitry can accommodate.

In accordance with a facet of the invention, control logic means comprises counting means having one count for each of the (6) states of 5 the motor energization sequence (e.g., 0-1; 1-2; 2-3; 3-4; 4-5; 5-0; 0-1; etc.) and at a constant rate of rotation allocates equal time for each count in a repeating sequence. The counting means comprises a minimum number of flip-flops for defining the states, the flipflops being positive (or negative) edge triggered flip-flops; which are clocked simultaneously by the timing signal.

The duration of the timing signal is long in relation to the propagation delays in the control logic means, and is long enough to null the amplifier means and reset the integration means.

The winding stage selection signals are de- rived from the states of the counting means. The input switching means to which the unenergized winding selection signals are applied, consists of a six-fold plurality of gates. Accordingly, the control logic means includes a first rank of six gates connected to the outputs of the (three) flip-flops, and a second rank of six gates connected to the outputs of said first rank of gates.

The first rank of gates produces a first suc- cession of six equal duration pulses having an active period equal to the duration of one motor energization state, and are used for operation of the input switching means.

The second rank of gates produces a sec- ond succession of six equal duration pulses having an active period equal to the duration of two motor energization states, the second succession occurring in an overlapping sequence. The double duration signals are used for operation of the power switching means.

As earlier noted, the control logic is responsive to direction control signals and to energy control signals, having three ranks of gates for that purpose. The 6-fold plurality of gates, re- sponsive to direction and energy control signals, consists of two ranks of three input gates, one rank of gates for transmission of the forward multistate sequence, one rank of gates for transmission of the reverse multis- tate sequence, and a third rank of two input gates for "oring" the outputs of said forward and reverse ranks of gates. One input of each of the forward and reverse ranks of gates is coupled to an output of the second rank of gates, a second input of each of the forward and reverse ranks of gates is for application of the PWMed energy control signal.

In accordance with another facet of the invention, the control logic means includes means responsive to the timing signal to apply 125 the PWMed energy control signal at the be ginning of the first half of the energization period of a winding stage for the duration of said timing signal, and at the beginning of the second half of the energization period of a 130 winding stage, delaying for the duration of said timing signal, before applying said PWIVIed energy control signal, for the remainder of the energization period.

At the output of the control logic means, six output drivers are provided for coupling the energized winding stage selection signals to the power switching means. Three of the output drivers are for control of power swit- ches connecting individual winding stages to one terminal (e.g. positive) of the power source; and three of said output drivers are for control of power switches connecting individual winding stages to the other terminal (e.g. negative) of the power source.

In accordance with a further facet of the invention, the control circuit is provided with a power on reset circuit for producing an active output responsive to the voltage of the low voltage DC supply of the control circuit for gating off the drivers when the voltage has been below a first value when power is turned on or below a second value when power is turned off. The voltage values being set such that normal circuit operation is assured at supply voltages exceeding the first and second values.

In operation, the protective circuit gates off the drivers when power is turned on for a period of time required for stabilization of the operation of the control circuit. It is accomplished by generating an artificial timing signal when power is turned on, signalling an artificial instant for commutation, nulling the ampli- fier means and causing the generation of at least a partial sequence of winding stage selection signals and nulling before the drivers are gated on.

According to another aspect of the inven- tion, the above objects are achieved in a control circuit for an electronically commutated motor adapted to be energized from a DC power source, the motor having a multistage winding assembly, and a magnetic assembly, the two arranged for mutual relative rotation. In a given state of a multistate energization sequence, the motor has an unenergized winding stage in which induced back emf appears which when integrated over time to a predet- ermined value indicates the instant at which the mutual relative angular position has been attained suitable for commutation to the next state. An inventive combination in the control circuit comprises a solid state transconductance amplifier means adapted to be coupled to an unenergized winding stage in the motor for converting the voltage appearing in the winding stage to a corresponding output current, integration means coupled to the output of the amplifier means for integrating the output current to obtain an output voltage substantially proportional to an integral of the voltage appearing in the winding stage, and comparison means for comparing the output voltage of the integration means to a value corre- GB2177272A 5 1 sponding to the mutual relative angular posi tion suitable for commutation, and upon sens ing equality generating a timing signal at the instant for commutation.

In accordance with one facet of the inven- 70 tion the transconcluctance amplifier means has current series feedback to stabilize amplifier transconductance.

In the principal embodiment, the motor has a multistage winding arrangement with a neutral connection. The transconductance amplifier means is, accordingly, a two input differential amplifier means, with one input adapted to be coupled to an unenergized winding stage and the other input adapted to be coupled to the neutral connection or the equivalent. The input stage of the amplifier means, is a differential input stage, which determines the transconductance of the amplifier means, with significant current series feedback being provided for stabilizing this parameter in that stage.

The subsequent stages of the transconductance amplifier means are arranged to exhibit unity current gain and a first and a second solid state current mirror are included. The output current from one transistor in the input stage is coupled to one current mirror and the output current from the other transistor in the input stage is coupled to the second current mirror. The transconductance amplifier means is completed with a first and a second solid state buffer amplifier, and a third, polarity inverting, current mirror.

More particularly, the first buffer amplifier comprises a third transistor having the control electrode common and a first principal electrode coupled to the output of the first current mirror, and the second principal electrode coupled to the input of the polarity inverting current mirror. The second buffer amplifier comprises a fourth transistor having the control electrode common and a first principal electrode coupled to the output of the second current mirror. The third current mirror comprises a fifth, output transistor having its control electrode coupled to the second principal electrode of the third transistor and a first principal electrode thereof connected to the second principal electrode of the fourth transistor, the fourth and fifth transistors being connected to provide a push-pull output in which output current is either supplied or withdrawn.

In accordance with a further aspect of the invention, means are provided for periodically resetting the integration means to an initial state suitable for initiating the succeeding integration. In addition, means are provided for periodically nulling the output current of the transconcluctance amplifier means, the nulling being timed to occur after the instant for commutation, but prior to resetting the integration means. The nulling means comprises means for incrementing the offset current of the cur- rent mirror to a value which corrects imbalance and sustains the corrective offset current until nulling again occurs.

More particularly, the nulling means comprises means for zeroing the differential input voltage applied between the inputs of the transconductance amplifier means and for establishing a desired output current level in the first and second transistors of the input stage amplifier, output switching means for disconnecting the output of the transconductance amplifier means from the integration means during the nulling interval, and a nulling comparator coupled to the output of the tran- sconcluctance amplifier means for detecting a change in sense of the output current, as the amplifier goes through balance to terminate the incrementing process and initiate resetting the integration means.

More particularly, the offset current incrementing means comprises means for supplying a clocking single (e.g. 20Khz) having a period which is short in relation to the commutation period and a nulling counter counting at the rate of the clocking signal. The state of the nulling counter controls the sum of the increments of offset current, and is preset in response to the timing signal. Subsequent counting during nulling adjusts the current off- set toward balance until a null is detected by the nulling comparator.

In accordance with a further aspect of the invention, a low voltage DC supply is provided suitable for operation of the control circuit, the voltage of the supply changing at a finite rate when power is turned on or turned off. A protection circuit is provided for producing an active output responsive to the voltage of the low voltage DC supply for holding at least a portion of the control circuit in an inactive state when the voltage is below a first value when power is turned on or below a second value when power is turned off, When the voltage has exceeded the first value as power is turned on, the circuit portion is released at a predetermined initial state. The voltage values are set such that normal circuit operation is assured at supply voltages exceeding the first and second values.

Preferably, the protection circuit, upon termi- nation of the active output as power is turned on, releases the circuit "portion" in a state to null the amplifier means to insure balance of the output current of the amplifier means be- fore integration of its output current. The protection circuit during said active output, presets the nulling counter, and upon termination of the active output, as power is turned on, releases the circuit portion in a state for null- ing the amplifier means, The state for nulling comprises activation of the zeroing means at the input of the transconductance amplifier means, activation of the amplifier output switching means for disconnection, and the release of the nulling counter.

6 GB2177272A 6 The protection circuit further comprises means to cause a starting offset in the output current of the amplifier means to insure integration of the output current to a voltage su- fficient for generatingthe commutation timing signal, the starting offset current, except during said nulling interval(s) extending over a sufficient period after power is applied to allow for control circuit stabilization. This period is typically five commutation periods.

In accordance with a further aspect of the invention a novel method of timing the commutation of an electronically commutated motor is disclosed, the principal steps of which comprise converting the differential voltage appearing in the unenergized winding stage to a corresponding bidirectional output current by means of a two input solid state differential transconductance amplifier means, integrating the output current to obtain an output voltage substantially proportional to an integral of the differential voltage; and comparing the output voltage of the integration means to a value corresponding to the angular position of the rotor suitable for commutation, and upon sensing equality, generating a timing signal at the instant for commutation.

Subsequent steps of the timing method comprise resetting the integration means to an initial state suitable for initiating the succeeding integration subsequent of each timing signal, and periodically nulling the output current of the transconductance amplifier means.

In a preferred method of operating an elec- tronically commutated motor, in which a differential transconductance amplifier is used for timing the instant for commutation, the steps comprise nulling the amplifier means upon turning on power for the control circuit prior to turning power on for the motor. Then the differential voltage appearing in the unenergized winding stage is converted to a corresponding bi-directional output current, integrated to obtain an output voltage, and com- pared to a stored value for generating a timing signal at the instant suitable for commutation. After a delay, power is applied to the motor in response to the next or a subsequent timing signal, selected to allow adequate time for the control circuit to stabilize. Next the integration means are reset to an initial state suitable for initiating the spcceeding integration, which occurs subsequent to each timing signal. Thereafter the output current of the tran- sconductance amplifier. means is periodically nulled.

According to a further aspect of the invention, the above objects are achieved in a motor speed or torque control circuit for an electronically commutated motor adapted to be energized from a power source, the motor having a multistage winding assembly, and a magnetic assembly, the two arranged for mutual relative rotation, the motor in a given state of a multistate energization sequence having an unenergized winding stage in which an induced back emf is integrated over time to determine the instant at which the mutual relative angular position has been attained suitable for commutation to the next state, and wherein in said given state, at least one other winding stage is energized in the appropriate sense to cause relative rotation.

An inventive combination in the control cir- cuit comprised power input terminals for connection to a supply suitable for motor operation; a waveform generator for supplying a repetitive low voltage waveform of substantiaily constant repetition rate, amplitude and configuration, the characteristics being substantially free of dependence on said motor, the waveform having a first slope of a first duration and a second slope of a second duration and of opposite sense to said first slope, and a repetition rate which is high in relation to the commutation rate; means for producing a substantially smooth adjustable control voltage; a modulating comparator having a first input to which said repetitive voltage waveform is supplied and a second input to which said adjustable control voltage is supplied, to produce output pulses when intersections occur between said' inputs said output pulses occurring at said constant repeti- tion rate, having an -active- on time equal to the interval between alternate pairs of intersections; and control logic means responsive to the---active-on time of said modulator pulses for providing pulse width modulated signals for control of the energization of the winding stages in the multistate energization sequence. In operation, adjustment of the control voltage, adjusts the active on time of each pulse and thereby the rate at which elec- trical energy is supplied to the motor for determination of the motor speed or torque.

The repetitive voltage waveform is preferably a saw tooth waveform, having a repetition rate above 20Khz. The adjustable voltage is smooth in relation to the motor commutation rate and in relation to the repetition rate of the repetitive voltage waveform. The inputs supplied to the modulating comparator are selected in the preferred case to produce an output waveform which at one limit of adjustment is substantially always on, at the other limit is substantially always off, and at intermediate adjustments is pulsed rectangular waveform of variable width.

A second means of variable speed or torque control is provided by an adjustable voltage reduction means serially connecting the motor to the power supply. This voltage reduction means in the power circuit is prefera- bly used in concert with the adjustable control voltage affecting the active on time of the pulse width modulation pulses used to control the application of power to the motor.

In a preferred embodiment, the adjustable voltage reduction means, is independent of 1 7 GB2177272A 7 the adjustable control voltage to produce a first reduction in motor speed or torque, but for further reductions, means are provided to make the adjustable control voltage applicable to the pulse modulator dependent upon its reduced voltage for powering the motor. This brings about a joint reduction in both the voltage and duty cycle of the PWMed energy supplied to the motor. This permits a full range of speed or torque control down to stalling speed, with a smaller reduction in motor voltage, and permits the reduced voltage to remain large enough at all times to sufficiently power the control circuit.

In accordance with a further aspect of the invention, a novel method of controlling the speed or torque of an electronically commu tated motor is disclosed. The steps entail pro viding a variable output voltage suitable for variable speed or variable torque motor oper ation by means of an adjustable voltage re duction means serially connecting the motor to the power source, generating a repetitive low voltage sawtooth waveform of substan tially constant parameters; providing an adjust able substantially smooth control voltage for motor speed or torque controls comparing the repetitive voltage waveform to said adjustable control voltage in a modulator to produce out put pulses when intersections occur between said inputs, the output pulses occurring at the repetition rate of the sawtooth waveform and having an -active- on time equal to the inter val between alternate pairs of intersections; applying energy from the power source to the motor during the active on time of the modu lator pulses, and adjusting only the variable output voltage for a small reduction in motor speed or torque, and for a further reduction simultaneously adjusting the variable output voltage and the control voltage for motor speed or torque control.

According to still another aspect of the in vention the above objects are achieved in a motor control circuit for an electronically com- 110 mutated motor adapted to be energized from a power source, said Motor having a multis tage winding assembly and a magentic as sembly, the two arranged for mutual relative rotation. In a given state of a multistate energization sequence, the motor has an unener gized winding stage in which an induced back emf is integrated over time to determine the instant at which the mutual relative angular position has been attained suitable for com120 mutation to the next state of the sequence. In each state of the sequence at least one other winding stage is energized in the appropriate sense to cause relative rotation. In the practi cal example herein treated, one sequence is 125 designed for clockwise operation and a sec ond sequence for counter clockwise operation.

The control circuit combines a first adjust able voltage reduction means for serially con necting the motor to the power supply to pro- vide a variable output voltage suitable for variable speed or torque operation; with means for producing a substantially smooth control voltage, dependent on the variable output vol- tage. The control voltage, upon passing through an intermediate value corresponding to a useful limit of the adjustable means, continues monotonically toward a final value. Means are provided responsive to a value of said control voltage between the intermediate and final values for generating a signal for control of the direction of motor rotation.

Preferably, the intermediate value of control voltage corresponds to the desired minimum motor speed or torque, typically when the motor stalls in a ceiling fan application, and the change in direction occurs past stalling toward the minimum output voltage.

In accordance with a further facet of the invention, the rate of downward adjustment of energy per unit change in output voltage is enhanced by means of a pulse width modulator also responsive to the control voltage. The pulse width modulator produces output pulses of constant rep-tition rate, the repetition rate being high in relation to the commutation rate, but with variable on times under the control of the control voltage. The energy, which is supplied to the motor during the active on times of the pulses, is thus reduced when a reduction in output voltage occurs, both by virtue of the voltage reduction, and by virtue of a reduction in the average time that the voltage is applied (i.e., the width of the PWMed pulses controlling energy supplied to the motor are concurrently reduced).

In effecting the desired range of speed or torque control, with a higher voltage at the minimum desired setting (i.e., the motor stall setting) it becomes possible to energize the control circuit through a voltage dropping network connected in parallel with the motor circuit. This then facilitates remote control operation, in that a simple wall control can achieve full range control of the motor speed or torque, and at the minimum setting effect a reversal also remote.

In the preferred embodiment, the motor direction control logic has two outputs, one for facilitating forward operation (clockwise rotation) by means of an active high in the output state, and the other facilitating reverse operation (counter clockwise rotation) by means of an active high in the output state. The internal logic precludes the output states from being active simultaneously, and when a state is changed, delaying the appearance of the new active state, after discontinuance of the prior active state, by a time long enough to protect the power switches, This period is typically in excess of the period of one pulse of the modulator.

The motor direction may be controlled by a switch coupled to the direction control logic, and normally on the fixture incorporating the 8 GB2177272A 8 fan. This switch, in accordance with a further facet of the invention functions with a protective circuit active during power up and power down to determine the motor direction when 5 power comes back on after an interruption.

In accordance with a further aspect of the invention, a novel mothod of controlling an electronically commutated motor is disclosed. The steps entail reducing the output voltage supplied to the motor through a range of values suitable for variable speed or torque operation, producing a substantially smooth control voltage, dependent on the variable output voltage, the control voltage, upon passing through an intermediate value corresponding to a minimum useful reduction, continuing monotonically toward a final value, and generating a signal for changing the direction of motor rotation at a value of the control voltage between said intermediate and final values.

In accordance with a further aspect of the inventive method the rate of downward adjustment of energy per unit change in output voltage supplied to the motor is enhanced and the range of voltage reduction required for the desired minimum setting (e.g., motor stalling) reduced by means of a pulse width modulator. The pulse modulator, produces output pulses whose "on" time also controls the rate at which energy is supplied to the motor.

As a further variation of the inventive method, the generation of a signal for motor reversal entails first generating a signal for suspending the energization for motor rotation in one sense, and after a short interruption for protection of the motor switches, generating a signal for motor rotation in an opposite sense.

Brief Description of the Drawings

The novel and distinctive features of the invention are set forth in the claims appended to the present application. The invention, itself, together with further objects and advan- tages thereof, may best be understood by ref- 110 erence to the following description and accompanying drawings described below.

Figure 1 is an illustration of the installation of a ceiling fixture combining a fan and a light, and including manual controls, the ceiling fan 115 being designed to be driven by an electronically commutated dc motor.

Figure 2 is a wiring diagram of the electronic circuitry providing electronic commuta- tion of the fan motor and giving effect to the manual controls. More specifically, Fig. 2 is a wiring diagram of a printed circuit board, including the interconnections with the fan motor, the ceiling light, the manual controls and a custom integrated circuit for motor control.

Figure 3 illustrates the control and commutation waveforms of the motor control integrated circuit.

Figure 4 is a block diagram of the principal functional subdivisions or blocks of the motor 130 control integrated circuit and the functional interconnections between said functional blocks. Figs. 5A, 6, 7, 9, 1 OA and 11 A are logic diagrams and/or circuit diagrams of the func- tional blocks for the motor control integrated circuit.

Figure 5A is a logic diagram of the Input Gating and a circuit diagram including device parameters of the Integrating Transconduc- tance Amplifier blocks of Fig. 4. Figures 5B, 5C and 5D are simplified electrical circuit descriptions of the Integrating Transconductance Amplifier.

Figure 5B illustrates a slightly extended and slightly simplified circuit of the Integrating Transconductance Amplifier including the input connections to an exemplary winding stage and the nulling resistances also treatable as a part of the Autonull circuit; Figure 5C illustrates an equivalent circuit representation of the Integrating Transconductance Amplifier (without feedback); and Figure 5D illustrates the equivalent circuit representation of the Amplifier employing series current feedback for stabilizing the amplifier transconductance, a mode of feedback comparable to that herein employed.

Figure 6 is a logic diagram of the Comparator Network and of the Modulo 6 Counter blocks of Fig. 4.

Figure 7 is a circuit diagram including device parameters in part and a logic diagram in part of the Autonull Circuit block of Fig. 7.

Figure 8 is the output waveform of the Inte100 grating Transconductance Amplifier for a single commutation period. The waveform illustrates the time allocated between integration and reset of a capacitor used to time the commutation instant and the nulling of the 105 Amplifier.

Figure 9 is a logic diagram of the Control Logic and Output Drivers blocks of Fig. 4.

Figure 10A is a combined circuit and logic diagram of the oscillator, Pulse Width Modulator and the Forward/Reverse Logic blocks of Fig. 4. Fig. 10B are waveforms explanatory of operation of the Pulse Width Modulator block; Figure 10C is a plot of the effect of manual operation of the wall control upon motor speed and direction of rotation; and Figure 10D is a simplified showing of a switchable wall control for motor speed and direction.

Figure 10E is a block diagram illustrating an open loop pulse width modulationmotor con120 trol arrangement according to the invention.

Figure 10F is a detailed representation of one of the motor control waveforms in Fig. 3.

Figure 1 1A is a circuit diagram including device parameters in part and a logic diagram in 125 part for the Power On Reset block of Fig. 4; Figure 1 1B is a graph illustrating the setting of the release voltage of the Power On Reset block.

Figures 12A and 12B contain the principal internal waveforms incident to operation of 9 GB2177272A 9 the motor control integrating circuit. Fig. 12A deals with commutation and balancing of the integrating Amplifier for an exemplary corn muttion period; and Fig. 12B deals with over all operation during the power on sequence.

DESCRIPTION OF THE PREFERRED EMBODIMENT

COMBINED LAMP AND CEILING FAN FIXTURE 75 USING ELECTRONICALLY COMMUTATED DC MOTOR Referring now to Fig. 1, an installation of a combined lamp 100 and ceiling fan 101 fix ture is shown, together with the appropriate manual controls. The fan motor, which is housed in housing 102, is, in this embodi ment, an electronically commutated dc motor (ECM) driving the 4-bladed fan. A stationary assembly of the motor comprises a ferromagnetic stator having a multi-stage winding ar rangement associated therewith which includes a plurality of stages, each in turn formed of a plurality of coils inserted into a plurality of slots spaced about a core of the stator. A rotatable assembly of the motor is arranged in selective magnetic coupling relation with the winding stages of the stator and comprises a rotor having a plurality of permanent magnet elements disposed thereon.

Although a specific ECM is illustrated herein for purposes of disclosure, it is contemplated that other types of ECMs having various other constructions and electrical characteristics may be utilized within the scope of the invention.

For example, some of the ECMs which may be utilized are disclosed in U. S. Patent Nos.

4,005,347 and 4,169,990 to David M. Erd man, and U. S. Patent No. 4,162,435 to Floyd H. Wright.

The connections to the motor traverse a hollow shaft in the motor permitting a station ary tube to carry wires between a conduit pipe 103, mounted on the upper surface of the motor housing 102 and a control box 104 supported upon the under surface of the hous ing. The conduit pipe 103 may be used to carry wires to a connection box (not shown) mounted on the ceiling. The conduit pipe 103 may also support the fixture. The control box 104 contains the control circuitry for the oper ation of the motor, including three manually operated controls. The lamp assembly 100 is supported on the under surface of the control box 104. The control circuitry is supported upon a circular printed circuit wiring board, fitted within the control box. The controls for the fixture include a three-way switch S2, op erated by a pull chain, for mode selection, a forward-reverse slide switch S1, and a speed adjusting potentiometer R40. The mode selec tion switch permits four modes: fan on; lamp on; fan and lamp on; and fan and lamp off.

The ceiling fixture is energized from a 115V ac main, connected in series with a wall 130 mounted control 105 which also contains manual controls.

In the example, the wall control includes manual controls for both fan and motor.

These also include an on and off switch for the fixture, a motor speed, forward/reverse control, and a lamp dimmer.

The control circuitry for operation of the ceiling fixture is illustrated in Fig. 2, which is a wiring diagram of the Fig. 1 installation. Fig. 2 contains as its principal features, the lamp 100, the three winding stage motor 120, the wall control 105, the wiring mounted on the printed circuit board, which includes as five major features, a motor control integrated circuit 121, three principal solid state switches 122, 123, 124 and a four section, precision resistance voltage divider 125. In addition to these five principal features, the printed circuit board includes the circuit elements for supplying power to the lamp, the motor, the motor control IC, and the timing and the manual controls coupled to the integrated circuit.

Operation of the fixture takes place in the following manner. The lamp receives power during "positive" half cycles of the ac main. Lamp (only) operation takes place when the three-way mode selection switch S2 is rotated to the lamp only position. Let it be further assumed that the wall control is "on" providing a low resistance bi- directional current path between its two external terminals. Assuming that the 115V ac main is energized, ac current follows a path from the first ac terminal 126, via the wall control 105, the demountable connector E4, the lamp 100, the demountable connector E2, the anode first and the cathode second of diode CR4, the demountable connector El, the switch S2, and finally the sec- ond ac terminal 127.

The motor and the IC receive power during 11 negative" half cycles of the ac main. Assuming that switch S2 is rotated to the motor only, or motor and fan on position, current from terminal 127 progresses via the switch S2, the connector E5, to a 150V dc power supply, consisting of a fuse F1, a current limiting resistance R22, a diode CR5, and a filter capacitor C1 connected between the cathode of the diode CR5, and the common ground connection of the supply. The transistor switches 122, 123, 124 each have a power input terminal connected via a protective network (1-1, CR12, CR13) to the 150+ volt bus of the dc supply originating at the cathode of diode CR5, and a load terminal connected respectively via the connectors E6, E7 and E8 to one end of the motor winding stages A, B and C respectively. The other ends of the mo- tor winding stages are connected to a neutral node 128, which is not an external connection point for motor energization. The switches A, B and C, which are identical, operate with one switch (for instance A) conductive high, another (for instance B) conductive low, and 1 G82177272A 10 the third switch (C) in a high impedance (nonconductive) state. In this instance, current flows from the 150V B+ bus via switch 122, connector E6 into the winding A, via the winding node 128 into winding B, into the connector E7, via switch 123 to the common ground. The common ground, also the negative terminal of filter capacitor Cl is returned via connector E4, and the wall control 105 to the other terminal 126 of the ac main. As has been indicated, power is supplied to the motor 120 and the motor control [C 121 only during the negative half cycle of the ac main because of unidirectional conduction by the di- ode CR5. Power is supplied to the lamp only during the positive half cycles of the ac main because of the unidirectional conduction of the diode CR4.

The motor control IC 121 receives its power (Vdd) at the output of the protective network (L1, CR12, CR13) via a voltage dropping resistor R23, a filter capacitor C2, and a voltage limiting zener diode CR1, which is coupled to the pad P13. The IC ground (Vss) is returned via the pad P6 to the system ground, to which the capacitor C2, and the zener CR1 are also returned. The arrangement provides an approximately +9.0 volts Vdd potential for operating the IC. The IC is manu- factured of silicon using a complementary (C) metal oxide semiconductor (MOS) process. The CMOS process readily produces P-channel field effect transistors (FETs), N-channel field effect transistors, single diodes, and resis- tances.

The control]C provides the appropriate output signals to commutate the three winding stage motor 120, and effectuates control over the motor giving effect to the manual controls in the motor mounted control box 104 and in the wall control 105. The IC derives the timing information used for commutation from the individual winding stages of the motor, the non-energized winding being sensed for back emf, to define the instant for commutation. The ends of the winding stages A, B and C, including the winding node 128, are connected respectively via the connectors E6, E7, E8 and E3, to one end terminal of each of four separate, precision, two resistor voltage dividers. The other end terminal of each divider is interconnected at node 129 and returned via two series connected, forward sensed diodes CR2 ano CR3 to ground. The diodes are shunted by a filter capacitor C3. A resistance R28 connects the node 129 to the B+ output at CR5, Cl, The taps on the four voltage dividers, which are set at a division ratio of 1 to 41, are coupled respectively to the input pads of the motor control IC labeled P5 (VA); P4 (VB); P3 (VQ; and P2 (VN). The voltage division ratio is designed so that the voltage swing about neutral (VN) at the IC inputs does not exceed the input capabilities of the motor control IC. The foregoing confi- guration, which is used for sensing the back emf in the momentarily non- energized winding stage, allows the voltage on the neutral winding node 128, which ideally equals half the apparent B+ supply, and which is also divided down to 1 part of 41 to form a reference voltage (VN). The voltages VA, V13 or VC referenced to the voltage (VN) form a suitable signal for application to the differential input of the IC.

For assured starting in the face of error in the Single In-line Plastic (SIP) resistance matrix 125, a discharge mechanism (Q92, R41) at P1 for capacitor C5 is provided, which still main- tains an essential minimum time constant of 0.20 sec. The collector of Q92 is connected to Pl, the emitter via R41 (240 K) to system ground, and the base to node 129 so as to provide a 21pa current drain at Pl. The selec- tion provides a starting period of 0.25 seconds and a margin for a 2pa system error. The offset error in timing becomes negligible at medium and high rpms.

The switches 122, 123 and 124 are de- signed to respond to control signals supplied by the IC at the pads P7 (AT); P8 (AB); P9 (1313); P 10 (BT); P 11 (CT); and P 12 (C13). The initial letters, A, B and C designate the winding stage of the motor 120. The second letter ---T- denotes that---on-signals from the pads so designated on the IC will produce switch conduction to the + 150 volt bus (T for Top) in relation to system ground potential or to a point +75 volts in relation to the voltage on the neutral winding node 128.The second letter -B- denotes that---on--signals from the pads so designated on the IC will produce switch conduction to system ground (B for Bottom) or to a point -75 volts in relation to the voltage on the neutral node.

The circuit of the switch 122, which controls the A winding of the motor, is shown in Fig. 2. It comprises three bipolar transistors Q82, Q88, Q85, which function to couple the non-neutral terminal of winding A terminal to B+ when AT at P7 is high and a single FET Q91, which functions to couple that winding terminal to system ground when AB at P8 is high. The switches represent a low cost de- sign, with the base of the input NPN transistor Q82 being coupled to the pad P7, and the emitter connected via R37 to ground. The signal appearing at the collector of Q82 is developed in the load resistor R31, serially coupled via the protective diode CR6 cathode first, anode second to the 150V B+ bus. A PNP transistor Q88, connected in the emitter common configuration, has its base connected to the collector of Q82, its emitter coupled to the cathode of diode CR6. The collector of Q88 is connected to the base of the NPN output transistor Q85, and via a collector load resistance R34 to the emitter of Q85. The collector of Q85 is connected via diode CR6 to the + 150 volt bus. The emitter of Q85 is 11 GB2177272A 11 coupled via connector E6 to the A winding stage. Transistor G88 serves to shift the level and provide the correct sense for driving the output transistor Q85. The diode C139, which has its anode coupled to the emitter of 0.85, and its cathode coupled to the B+ output at CR5, Cl,is a flyback diode, reducing the inverse switching transients. The Q82, Q88, Q85 combination provides a low resistance, high current capacity connection of winding stage A to the + 150V bus when the voltage AT at pad P7 goes to an active high.

The field effect transistor G91 is an N-channel device, which couples winding stage A to system ground. The gate of Q91 is coupled to pad P8, the source is connected to system ground, and the drain is connected to the emitter of Q85, and via connector E6 to the non-neutral terminal of winding stage A. Tran- sistor Q91 provides a low resistance, high current capacity connection of winding stage A to the system ground when the voltage AB at pad P8 goes to an---active-high. The high currents under discussion are those appropri- ate for a 50 watt fan motor.

The inductor Ll, as a part of the protective network (L1, CR12, CR13), prevents the extremely high switching current peaks which would stress the solid state power switches.

In this application, the problem is more acute in the bottom rank FETs (Q91 in switch A, or the counterparts of Q91 in switches B and Q. These peak currents would ordinarily occur when selected upper rank bipolar transistor switches (Q85 in switch A, or the counterparts of Q85 in switches B and C) are turned on, while the current from the motor is flowing in the diode portion of the FET (drainsource connection). The recovery of this---di- ode- (structurally the base-collector junction of a bipolar transistor inherent in the FET) determines this current and the ---safe-recovery of the device.

The two serially connected diodes CR12 and CR13 shunt Ll, so that the voltage transients appearing on the 150V bus will be clamped to the main filter capacitor Cl. Therefore, the B+ connection to these switches will not fly back significantly above the B+ voltage established by the filter capacitor. For the circuit to be effective, one of the diodes (e.g. CR12) should be a fast recovery diode. The protective circuit protects against the -shoot thru- current mentioned above, during PWM switching, which could otherwise J result in dangerously high peak currents in both ranks of the transistor switches.

An alternative protective scheme for the lower rank FETs is to use two diodes, one connected between the drain and the system ground in shunt with the lower rank FET (e.g. G91), the diode being poled to conduct when the FET is back-biased, and a second diode inserted in the drain poled to conduct when the FET is forward biased.

As the drawing of the switch implies, if both pads P8 and P7 are low, the switch A is in a high impedance state, or non-conductive state, with the non-neutral lead at the winding stage A, now unenergized, free to reach whatever value is produced by the back emf as the winding stage A is subjected to the field produced by the rotating permanent magnet rotor.

The sequence in which switching occurs is shown in the commutation waveforms of Fig. 3. The waveforms available at the pads P7-P12 on the]C for control of the switches 122, 123, 124 are the six lowermost waveforms (AT, AB, BT, etc.), with those to the left representing FORWARD motor rotation and those to the right representing REVERSE motor rotation. The two waveforms denoted the---FOR-for forward or---REV-for reverse waveforms are internally generated on the IC, and are affected by the setting of SPDT S1, connected to the FOR/REV pad P16, and the wall control. With the IC in a Forward state, (FOR active high), the switching waveforms al- low a first sequence from the left margin to the center of the drawing. Should the forward signal go low and the reverse signal go high, the switching signals will resume a second se quence.

The Commutation Output Waveforms or en ergized winding selection signals, occur in a sequence of 6 waveforms (AT, AB, BT, BB, CT, C13) for energization of the winding stages A, B or C. The---highs-of each waveform (for purposes of initial discussion, the vertical markings under highs on the waveform, which denote duty cycled operation, are ignored.) have a duration of two counts of the least significant bit (B0) of a three-bit (B0, Bl, B2) Modulo 6 Counter. The motor, taken as a whole, has 6 distinctive energizaiOn states, in each of which one winding (A, B or C, e.g. A) is connected to B+, one remaining winding (B or C, e.g. B) is connected to ground, and the remaining winding (e.g. C) is not energized. Each motor energization state lasts for one count of the least significant bit (B0) of the Modulo 6 Counter, and each motor energization state ends-by definition-at the corn- mutation instant.

The commutation output waveforms, as will be described, are logically derived from the counts (B0, Bl, B2) of three flip-flops in the Modulo 6 Counter which lead to six counter output states CSO, USP, URS2-, S3, CS4, CS5, (the overlining denoting that the low is active). The counter output waveforms (CSO, etc.) are used to derive the commutation output waveforms and are unenergized winding selection signals used for selecting the unenergized winding at the input of the control IC for commutation sensing.

The order of active lows of the CSO-CS5 waveforms to the left of the margin ascend to the right (from E-SO to U-S5 before reversal, 12 GB2177272A 12 and descend to the right (from ES---5 to JES0) after reversal. The BB and CT waveforms are undefined until the POR (power on reset) goes to an inactive high, releasing the counter from the CSO staiLe (130=0; B1 =0; B2=0). At the next count, CSO goes high and CS1 goes low, AB goes on, BB and BT are off, and CT continues on. At the next count, CS2 goes low, AB stays on, BT goes on and CT and CB are off. The described sequence of winding energizations continue to the center of the figure until FOR goes low, at which the sequence reverses as illustrated.

The production of the correct sequence of switching waveforms to produce forward rotation, reverse rotation, or faster or slower motor rotation, and to commutate the stator assembly at the correct angular position of the rotor is the function of the motor control IC 121, whose internal design will now be described.

MOTOR CONTROL IC 121 FOR ELECTRONICALLY COMMUTATED DC MOTOR The principal functional subdivisions of the motor control IC 121 are shown in Fig. 4. The detailed logical and/or circuit designs of the functional blocks are shown in Figs. 5A, 6, 7, 9, 1 OA and 11 A.

The control IC consists of 11 interconnected blocks 140 to 150 interconnected to the circuitry on the printed circuit board by the 16 pads P1 to P16 as already noted. The rotational position of the rotor is--iclentified- by the Modulo 6 or CornTutation Counter 144, which has six states (CSO-CS5). The permanent magnet rotor, due to magnetic coupling rotates in synchronism with the rotation of the magnetic field produced by the stator as- sembly. Depending on the number of---polesof the motor, the count may repeat once, twice, three times, four times, etc. per revolution. The actual embodiment herein described employs a 6 pole permanent magnet rotor with an 18 coil, 3 winding stage, 36---toothstator assembly. The P count is repeated three times per revolution.

The Modulo 6 Counter 144 controls the sequential switching of the Output Drivers 146 for sequential energization of the winding 115 stages, and for the sequential enabling of the Input Gate 140 for selecting the appropriate unenergized winding for commutation timing.

The Counter is subject to control for a for ward or a reverse count by means of the Forward waveform (FOR) derived from the Forward/Reversed Logic 149. When power is first applied, the CotInter is held in a preset state means of the Power On Reset wave form (POR) derived from the Power On Reset 125 Waveform 150. The commutation instant for the electronically commutated motor is defined by means of the positive going edge Reset 1 waveform supplied by the Comparator Net- work 142 to the Counter 144. The Reset 1 waveform -clocks- the Counter 144, thus defining the instant that the energization stage of the rotor changes and the instant that the winding stage being sensed for commutation timing is changed.

The Moduto 6 Counter 144 controls the energization sequence of the winding stages A, B and C by means of the Control Logic 145, the Output Drivers 146, and the switches 122, 123 and 124. The output from the Counter 144 in the form of six NANDed combinations of adiacent counter states (CSO, ES-1; ES-1, US0; etc. ) and the least significant bit (B0) of the counter memory is coupled to the Control Logic 145. The Control Logic 145, decoding the outputs from Counter 144, derives high or low control signals for application to the six individual drivers, which make up the Output Drivers 146.

The Control Logic 145 is subject to control for a forward or a reverse count by means of the FORWARD Waveform (FOR) and the REVERSE Waveform (REV) derived from the FORWARD/REVERSE Logic 149. It is also subject to a control which inverts the sense of the driver output on alternate counts. This inversion is achieved by means of the BO waveform derived from the least significant bit of the Counter memory, and NORed with the RE- SET 1 waveform derived from the Comparator Network 142. The Control Logic, by means of the PWM Output Waveform derived from the Pulse Width Modulator 148, effects a pulse width modulation of a 20KHz oscillation from Oscillator 147, which affects'the conduction duty cycle of the output drivers in the manner indicated in the vertically lined areas of the driver waveforms (AT, AB, etc.) of Fig. 3.

The Output Drivers 146 to which the wave- forms (AT, AB, etc.) are applied provide signal gain at the pads P7-P12 of the Motor Control]C adequate to drive the separate switching transistors in the solid state switches 122, 123, 124 on the printed circuit board. The output drivers 146 by means of the 1 start waveform derived from POR 150, defer the actual application of power to the motor windings until 5 commutation intervals have taken place after power is initially turned on. This allows the commutation timing circuitry to stabilize before the actual application of power to the windings.

The Modulo 6 Counter 144 sequentially enables the Input Gating 140 for selecting the appropriate unenergized winding stage for connection to the Integrating Transconductance Amplifier 141 and Comparator Network 142 for commutation timing. In timing the commutation, the back emf developed in the unenergized winding stage (as a result of rotation of the permanent magnets on the rotor past the stationary, un-energized winding stage) once selected by the Input Gating 140, is amplified in the Amplifier 141, and inte- grated and measured in the Comparator Net- I; 13 GB2177272A 13 work 142 to determine the correct commuta tion angle. The selection of the appropriate unenergized winding stage by the Input Gating is synchronized with the selection of the other two of the three winding stages by the 70 Control Logic 145 for energization.

The Input Gating 140 is coupled via pads P2-175 to the voltage divider matrix in the printed circuit board connected to the non neutral terminals of each of the three motor stator winding stages (A, B, Q and to the neutral terminal for selection of the appropri ate timing information. The Modulo 6 Counter controls the Input Gating 140 in identifying and selecting the stator winding stages which are unenergized, by_2roviding the six counter output waveforms (CSO, CS1, etc.) to the en abling inputs of the Gating, which have an active low when the Gating should be ena bled. The output of the Input Gating is con nected to the input of the Integrating Tran sconductance Amplifier 141, which has two differentially connected inputs. The Input Gat ing selects a single identified unenergized winding stage taking one input (e.g. VA) from the non-neutral terminal of the winding stage, and one input (e.g. VN) from the neutral wind ing node 126. The counter stages (_SO, _S_1, etc.) are assigned to cause alternation of the sense of the connections between the non neutral terminals of the winding stages and the Amplifier inputs on successive counts. The alternation of the connection sense between the common neutral terminal and the Amplifier inputs is achieved by means of the least signi100 ficant bit (130) derived from the Counter mem ory.

This alternation by the Input Gating 140 of the sense of the connection between the winding stages and the Integrating Amplifier 141 is necessary to insure that the polarity of the Amplifier output is always the same. The waveform of the back EMF appearing on one winding stage has a first slope (e.g. positive) while the waveform of the next winding stage for the next period of integration has an oppo site slope. The inversions produced by the In put Gating thus keep the sense of the Ampli fier output the same for successive integration periods.

The Input Gating 140 is thus the input switching means of the IC which couples the back EMF waveform via the matrix 125 from the winding stage. This waveform, which indi cates the instantaneous angular velocity of the rotor is next coupled to the blocks 141, 142, 143 for integration to obtain the angular tran slation of the rotor. These blocks, and more particularly the Comparator Network 142 (in cluding C5), produce an output pulse, i.e. the Reset 1 pulse, at the instant the correct rotor angle for commutation has been reached. The Reset 1 pulse is used to clock the Modulo 6 Counter 144. The Reset 1 waveform is also coupled to disable the Input Gating during the nulling of the Amplifier 141 and during resetting of the integrating capacitor (C5), connected to the Comparator Network 142.

The Integrating Transconcluctance Amplifier 141 is a difference amplifier to the two inputs of which the signal from the selected winding stage in the form of a voltage are differentially applied. The Integrating Transconductance Amplifier 141 converts the differentially ap- plied input voltage to an output current which is integrated in the Comparator Network 142 in determining the correct commutation angle. The output current from the Amplifier is coupled to an integrating capacitor C5 coupled to pad P1. Capacitor C5, in storing the Amplifier output current, develops a voltage derived from the selected unenergized winding stage, which is an appropriate means of determining the instantaneous rotor angle. The voltage in- tegral is a measure of the angular position of the rotor which is substantially independent of the rate of rotation of the rotor over a 10/1 range of rotational rates. The voltage appearing on the capacitor C5 as a result of integrat- ing the Amplifier output current provides an accurate duplication of the voltage integral to the extent that the Amplifier output current is proportional to the differential input voltage and to the extent that a time integral of the Amplifier output current is equal to the time integral of the input voltage. The voltage integrated by the capacitor C5 is then compared with a standard voltage (Vref 3) corresponding to a known optimum rotor commutation angle to determine the instant that commutation should take place.

The accuracy of this method of rotor angle determination depends on the stability of the transconductance of the Integrating Transcon- ductance Amplifier, and, since the Amplifier is a direct coupled difference amplifier susceptible to imbalance, it also depends on the accuracy with which any imbalance may be compensated.

The output of the Amplifier 141 is coupled to a Comparator Network 142, which detects when the voltage stored in the capacitor C5 as a result of current integration has equaled the standard voltage corresponding to the cor- rect angular position of the rotor for commutation. When equality is sensed, the Comparator Network signals (RESET 1), the commutation instant to the Modulo 6 Counter 144. Upon this signal, the Counter advances to the next count, and the Input Gating 140 and Output Drivers 146 are advanced to implement the commutation and commence the energization, cleenergization and voltage sensing for the three winding stages appropriate to the next count.

The third block active in commutation timing is the Autonull Circuit 143, which provides an offset to correct any imbalance in output current of the Integrating Amplifier. "Nulling" of the Integrating Amplifier occurs on each com- 14 GB2177272A 14 mutation. As illustrated in Fig. 8, nulling takes place after the capacitor integration period has ended, signaled by the RESET 1 pulse, but before the timing capacitor (C5) is reset (dur ing RESET 2) preparatory to the next capacitor 70 integration period. The Amplifier 141 is placed in a condition to be nulled, and then causes reset of the integrating capacitor by the appli cation of the RESET 1 and RESET 2 wave forms, respeGtively.The RESET 1 waveform shorts the differential input of the Amplifier, and thus provides a zero differential input sig nal essential to nulling. The Reset 2 waveform is active after nulling, and sets the amplifier output into a state in which the integrating capacitor (C5) is rapidly recharged toward Vdd. In addition, during nulling, certain con trols are applied to the resistances R3A-D and R4A-D, which for certain purposes, form a portion of the Amplifier. These will be dis- 85 cussed in connection with the Autonull Circuit.

The nulling of the Amplifier 141 produces a periodically verified current offset which is ap plied to one amplifier channel to null the am plifier output current for a zero input signal.

The Autonull Circuit 143 produces this offset current in small (3/4,uA) increments which are applied to a current offset one channel of the amplifier. The increments are designed to raise or lower the current transfer ratio of a mirror in one channel of the Amplifier to bring the output current of that channel into balance with the output current of the other channel.

The nulling takes a small time, typically less than a millisecond, but not exceeding a maxi- 100 mum of 1.4 milliseconds. After nulling, the timing capacitor C5 is reset (during RESET 2), which takes 3-5 milliseconds, to prepare for the next capacitor integration period to time the next commutation. It is also necessary to 105 provide this time delay after commutation has taken place to assure that all of the stored energy in the now unenergized winding (which was energized prior to commutation) has time to dissipate. This is necessary to assure that 110 stored energy is not incorrectly interpreted as back-emf causing a large error in the commu tation instant. The Autonull Circuit 143 and its relationship to the other functional blocks will be described in detail below.

The remaining blocks in the control IC deal primarily with implementing the manual control functions. When the ceiling fixture is turned on, and power is to be applied to the fan motor, the "Power On Reset" (POR) is active. 120 The POR 150 is a protection circuit for other portions of the ECM control circuit which becomes active when power is turned on or turned off. It insures that the protected circuitry is held in a desired safe inactive state 125 when the supply voltage on the protected cir cuit is below a first value when power is turned on, or below a second value (usually slightly lower) when power is turned off.

When power is turned on, it releases the pro- 130 tected circuit in a desired initial state. The interaction of the POR with other functional divisions of the Motor Control]C is in part illustrated in the waveforms of Fig. 3 and Fig. 1213.

In consequence of the appearance of the active output of the POR when power is turned on, the Amplifier 141 is disconnected from capacitor C5, and the Comparator Net- work 142 and the Autonull Circuit 143 are preset. This produces an initial state, akin to the occurrence of a commutation instant in preparation for nulling the amplifier. The POR presets the 3 bit memory of the Commutation Counter 144 in an initial (000) state. It presets the Forward/Reverse Logic to the state set in by the switch S1 on the printed circuit board. The presetting occurs immediately after power has been applied to the POR and lasts until Vdd is high enough (e.g. 7.0 volts) to insure that the analog and logic circuitry is valid.

When the active POR output terminates, the autonull circuit is released for nulling, insuring that the Amplifier is nulled before it is used for integration timing. After this, the POR 150, now acting by means of the IST waveform coupled to the Autonull Circuit, influences starting for five artifical counts of the Commutation Counter 144 by introducing an offset current in the resistance network of the Amplifier 141, which facilitates discharge of the integrating capacitor C5 to the voltage set to mark the commutation instant and nulling. For the same 5 count period, the POR, acting by means of the 1 start waveform, turns off the ---bottornswitches of the output drivers, precluding the coupling of energy to the winding stages of the motor until the Amplifier 141, Comparator Network 142 and the Autonull Circuit 143 have stabilized.

The Forward/Reverse Logic 149 is responsive to the setting of the switch S1 coupled to the pad P 16 on the IC. It is also responsive to a controlled diminution in the B+ supply effected by the operation of the wall control to reduce the B+ voltage below the desired threshold. In addition, when power is reapplied, after having been turned off, the POR 150 circuit presets the Forward/Reverse Logic to the state that corresponds to the setting of switch S1. A change in the output from 149 which causes the Forward waveform to go to an active High from a prior Low, and the Reverse waveform to go to an inactive Low from a prior High, or vice versa, produces a reversal in the direction of rotation of the motor. These waveforms, which are illustrated in Figure 3, are the means by which a reversal in motor rotation is achieved. The Forward waveform is coupled to the Commutation Counter 144 to effect both a forward and a reverse count. The Forward and Reverse waveforms are coupled to the control logic for enabling the Forward gates (U42-U47) or the Reverse gates (U36-U41).

GB2177272A 15 The Forward or Reverse waveform is also coupled to the POR for decoding the five count interval for simulated commutation.

When the Forward/Reverse Logic is in a For ward state, the POR is enabled to count for ward to the CS5 state, and when the Forwar d/Reverse Logic is in a Reverse state, the POR is enabled to count -backwards- to the CSO state, both of which provide the required delay.

Control of the Forward or Reverse state of the Logic 149 is achieved through operation of the wall control 105. If reversal is desired, the motor speed control is moved in the di rection of reducing speed past the point at which the motor will stall. The effect of so moving this control is to reduce the B+ be low a threshold. This in turn is sensed on the regulate pad (p 14) via the action of transistor 0,81, thus raising the regulate voltage above the peak sawtooth voltage. This is sensed in the Logic and used to cause a reversal in the state of the Forward/Reverse setting. The sensing is achieved by comparing the B+ us ing circuitry on the printed circuit board includ- 90 ing Q81, R25, R26, R27, R29 and R30, with a Zener stabilized voltage reference, also on the printed circuit board, but divided down on the Motor Control IC 121. The Logic includes a comparator which compares a voltage pro- 95 portional to the B+ voltage with a voltage proportional to the Zener voltage, and includes a circuit on the IC for introducing hysteresis in the threshold to make the switching action positive.

Finally, the Forward/Reverse Logic is pro vided with a delay based on the use of a 20KHz pulse for the Oscillator 147 in the ac tual changeover from forward to reverse oper ation. The Clock waveform CLK is coupled to the Forward/Reverse Logic to effect this de lay.

The Oscillator 147 and the Pulse Width Mo dulator 148 enter into the regulation of the speed. The motor is designed to run at a speed established by the amount of electrical power supplied to the motor and the amount of mechanical power required to rotate the fan and drive the air impinging on its blades.

When greater power is supplied, the rate of 115 rotation increases, and when lesser power is supplied, the rate of rotation decreases. The speed is thus controlled by the amount of power supplied, and that power is subject to a continuous control. The commutation is designed to be at the correct angle irrespective of the speed of rotation and is not intentionally varied with adjustment of the speed.

The Oscillator 147 and Pulse Width Modula- tor 148 provide the means for adjusting the power supplied to the motor over a range of substantially all off to all on. In practice, the arrangement permits the motor to operate over a 20 to 1 range of speeds. As earlier explained, the motor is energized by simulta- neous energization of two serially connected winding stages. Should only one winding stage be energized as when the 1 start waveform is applied, the motor receives no electri- cal energy.

The control of the motor speed is exerted by pulse width modulating one of the two switches which are enabled at each count of the counter. This is best seen from an examination of Fig. 3. The waveforms derived by the output drivers (AT, AB, etc.) and coupled to the output of pads P7-P12 illustrate these properties. Each waveform (AT, AB, etc.) has an active high of two counts duration with the same two highs being on simultaneously for only a single count. In addition to the two highs that are on, one is always shown with the vertical lines indicative of pulse width modulation. Thus, by pulse width modulating one of the two active switches, pulse width modulation occurs at all times. In addition, due to the classic nature of the pulse width modulation, the on time of the pulse width modulated waveform may vary from 0 to 100% which thus provides a full range of power control.

The Oscillator 147 is a relaxation oscillator whose principal circuitry is on the IC but which has an external capacitor C6 and a resistance R24 mounted on the printed circuit board and connected to the IC at pad 15. The internal oscillator waveform is a unidirectional pulse having an approximately 20KHz repetition rate with an on time of 300 nanoseconds for the narrower portion of the pulse. The CLK output of the oscillator derived from a flip-flop (L194-U91 is coupled to the Forward/Reverse Logic 149, as earlier noted, for effecting a delay when the direction of motor rotation is changed equal to at least one pulse width interval. The inverse of the oscillator waveform ERK is coupled to the Autonmil Circuit 143 where it controls the incrementing rate in the nulling process.

The output of the Oscillator 147 is modulated by the Pulse Width Modulator 148. The components of the Pulse Width Modulator are in part on the integrated circuit and in part on the printed circuit board being interconnected by means of the pad P14 (REG). The external components are largely shared with the Forward/Reverse Logic. They include the potentiometer R40, the resistances R25, R26, R27, R29, R30, and capacitor C4.

The Pulse Width Modulator is a classical modulator which provides an output which in the limiting cases is on all of the time or off all of the time, and in intermediate cases is on part of the time and off part of the time, as illustrated in Fig. 1013. The output of the Pulse Width Modulator (PWM out) is coupled to the Control Logic 145 by means of which it introduces a pulse width modulation into the switching waveforms in either of the forward bank (U42-U47) or the reverse bank 16 GB2177272A 16 (U36-U41) of gates.

The Autonull Circuit 143 nulls the Integrating Transconductance Amplifier to remove any error in timing of the commutation instant attributable to Amplifier input offset and to improve motor starting performance. The Autonull Circuit is located entirely on the Integrated Circuit and requires no pads for external connection.

The Autonull Circuit includes two digitally subdivided resistive elements R3A-D and R4AD, which are the resistive elements in a current mirror inone of the two channels of the Amplifier 141 following the differential input stage. The current mirror is modified by the inclusion of means for introducing an offset current which may be digitally stepped in 3/4MA increments on either the input or output side of the current mirror, and which in effect brings one channel of the Amplifier into balance with the other. The incrementing occurs under the control of a 5 bit counter, which counts at the 20KHz rate of the Oscillator 147 (CLK). In the nulling process, the 5 bit counter is preset to a maximum offset current condition and is then decremented at the clock rate until a balance is detected. When the balance is detected, the counter stops and the offset current is maintained until nulling is again instituted.

The Autonuiling Circuit functions once for each commutation. The waveforms that are involved in nulling for normal operation are illustrated in Fig. 12A. The nulling period starts after the Comparator Network 142 (COM 2, U80, D16 Q) has signalled the commutation instant (see Fig. 9), causing the RESET 1 wa veform to go high (D 16 Q). When the RESET 1 waveform goes high, the input to the Inte grating Amplifier 140 is referenced to a vol105 tage reference (Vref 1) suitable for nulling and the differential amplifier inputs are shorted to gether. At the same time the Null Clock wave form is generated by the Comparator Network 142 (D 17 % This waveform is coupled to a 110 bit counter in the Autonull Circuit (D8, D12) which forces the Autonull Circuit into a PRE SET condition in which the maximum offset current, earlier mentioned, is injected into the Amplifier 141. At substantially the same time, 115 the Autonull Circuit generates the Null Output waveform (D7, d) which is coupled to a transmission gate U85) at the input to the Comparator Network 142. This disconnects the Amplifier from the external integrating capacitor (C5), leaving the Amplifier output connected only to third comparator (COM 3) in the Comparator Network. The input conditions cause the Amplifier output voltage to climb past the threshold Vref 2 of the third comparator (COM 3) causing the Null Set waveform originating at COM 3 U81 to go low. This waveform, when coupled back to the Autonull Circuit, releases the PRESETS on the counter, and allows the counter to decrement 130 at the clock rate. Decrementing is accompanied by a stepped reduction in the offset current applied to the Integrating Amplifier. When the comparator COM 3 senses that the vol- tage at the output of the Amplifier, which had been near Vdd changes in direction, signalling the null, the Null Set waveform goes high. On the following clock pulse the Null Output (D7 (1) waveform goes low. The Null Output wa- veform (D7 (1) is coupled to the Comparator Network which generates the RESET 2 waveform, which converts the Amplifier 141 into a maximum current supply state. At the same time the Null Output waveform operates the transmission gate U85 to reconnect the Integrating Amplifier to the integrating capacitor C5, When the upper voltage reference (Vref 4) is crossed, both RESET 1 and RESET 2 terminate and the next capacitor integration period commences.

During start conditions the Autonull sequence is affected by the Power On Reset 150. The Power On sequence is illustrated in the waveforms of Fig. 1213. When power is first applied, the POR waveform is in an active low which causes the Null Clock waveform (D 17 Q) to go high. This causes the Autonull counter to be preset in a high offset current condition. When the POR waveform goes to an inactive high subsequently, the Null Clock waveform fails, allowing the counter in the Autonull Circuit to decrement. The autonulling is further affected by the application of an offset current IST which is interrupted during nulling, but active during capacitor resetting and integration. The offset current IST adds to the discharge current of the Integrating Amplifier and causes the integrating capacitor to discharge more rapidly and more positively toward the threshold of comparator COM 2. Under the influence of the logic contained in the POR block, the IST current continues until 5 autonull sequences are completed. During the same 5 count sequence, the lower drivers BOBA-C are also disabled so that no power is applied to the motor windings. On the sixth count, the IST and 1 Start highs are terminated, the motor windings are energized and autonulling continues in the normal manner.

THE INPUT GATING 140 The Input Gating 140 is the input switching means of the Control IC 121 which selects the correct unenergized motor winding stage for determination of the next commutation instant. The Input Gating 140 is coupled to the pads P5, P4, P3 and P2, respectively designed for connection via the four section voltage divider 125 to the VA, VB, VC and VN motor winding terminals earlier identified. The voltage divider 125 is the means immediately connected to the winding stages for deriving voltages proportional (1/41) to the voltages induced in the winding stages reduced to values suitable for application of the IC.

17 GB2177272A 17 The Input Gating 140 couples the output voltage from the selected winding stage to the input terminals 150, 151 of the Integrating Transconductance Amplifier 141 in the correct sense to keep the correct Amplifier output po- 70 larity over successive commutation periods. The Input Gating consists of eight bidirectional transmission gates U58, U60, U62, U64, U66, U68, U70 and U72, each associated with an inverter U57, U59, U61, U63, U65, U67, U69 and U71, respectively, three gates U54, U55 and U56 used to control the sense of the selection of the nautral (N), and six gates U73-U78 used to control the sense of selection of the three non-neutral winding stage terminals (A, B, Q. The output voltage from the selected winding is coupled between the input terminals 150, 151 of the Integrating Transconductance Amplifier 141. The control signals for operating the input gates are derived from the Comparator Network (RESET 1) and the Modulo 6 Counter 144 (130, CSO-5).

The Input Gating 140 is connected as follows. The transmission gates are bidirectional conductive devices, each consisting of two complementary field effect transistors connected in parallel between the signal input terminal and the signal output terminal. Each transmission gate has two control terminals requiring oppositely sensed control voltages. In the illustrated configurations, a signal is coupled directly to one control terminal, and through an inverter to the other control terminal, so that there is in fact only a single control connection assigned to each gate. The transmission gates are enabled with a high control signal, and not enabled with a low control signal. The signal input terminals to the gates U58 and U60 are coupled to the pad P2 for application of the VN voltage. The output terminal of the gate U60 is connected to the input terminal 150 of the Integrating Transconductance Amplifier, while the signal output terminal of the gate U58 is connected to the input terminal 151 of the Integrating Transconductance Amplifier. Similarly, the signal input terminals of of the gates U62 and U64 are connected to pad P5 for application of the VA voltage. The signal output terminal of the gate U64 is connected to the amplifier input terminal 150, while the signal output of the gate U62 is connected to the amplifier input terminal 151. The signal input terminals of the gates U66 and U68 are connected to the pad P4 for application of the VB voltage. The signal output terminal of the gate U68 is connected to the amplifier input terminal 150. The signal output terminal of the gate U66 is connected to the amplifier input terminal 151.

The signal input terminals of the gates U70 and U72 are connected to the pad P3 for application of the VC voltage. The signal output terminal of the gate U72 is connected to the amplifier input terminal 150. The signal output terminal of the gate U70 is connected to the amplifier input terminal 151.

As already indicated, each transmission gate has an associated inverter, which inverts the applicable control signal. The uninverted control signal for each transmission gate is directly coupled via the associated inverter to the other control input of that transmission gate. The inverter U54 and two input NOR gates U55 and U56 are connected to the con- trol inputs of transmission gates U60 and U58. The control signals for these gates are the RESET 1 waveform derived from D 16 Q of the Comparator Network 142, and the least significant bit (B0), from the flip- flop D1 Q of the Modulo 6 Counter 144. The RESET 1 pulse is coupled to one input of NOR gate U55 and to one input of NOR gate U56. The least significant bit (B0) from the Modulo 6 Counter is directly coupled to one input of the NOR gate U56, and indirectly coupled via the inverter U54 (whose input is connected to D1 Q) to the other input of NOR gate U55. The two input NOR gates U73 to U78 each have one input coupled to D16 Q for application of the RESET 1 pulse, and one input coupled respectLvely jo the Counter 144 for application of the CS5-CSO waveforms.'The outputs of the NOR gates U55, U56 and U78 to U73 are connected to the control inputs of the transmission gates U58, U60, U62, U64, U66, U68, U70 and U72, rehpectively.

The Input gating 140 is designed to sense the voltage of the selected winding during the capacitor integration period, when the RESET 1 waveform is low (see Fig. 8). Thus, each NOR gate (U55, U56, U73-U78), which has one input coupled to D16 Q for application of the RESET 1 waveform, inhibits all eight transmission gates (U58, U60, U62, U64, U66, U68, U70, U72) when the RESET 1 waveform is high. When the RESET 1 waveform is low, however, corresponding to the capacitor integration period, the NOR gates may be selectively energized in accordance with the state of the Modulo 6 Counter.

The transmission gates of the Input Gating are arranged to successively invert the polarity of the signal coupled from the motor winding stage to the input terminals 150, 151 of the Integrating Amplifier 141. Assuming that the counter is in the CSO state (and that the RESET 1 waveform is low), CSO is low, the output of gate U78 is high, enabling transmission gate U62, which co2les VA at pad P5 to terminal 151. At the CSO state, the least significant bit is also low. NOR gate U56, with two lows at the input, has a high at the output, enabling transmission gate U60 to coupled VN at Rad P2 to terminal 150. At the next count, the CS 'I state, the output of U75 is high, enabling U68, and coupling V13 at pad P4 to terminal 150. The least significant bit is now high, and NOR gate U55, with two lows at the input, has a high at the output, enabling transmission gate U58 to couple VN at pad 18 GB2177272A 18 P2 to terminal 151. Similarly, at the next count, the CS2 state, the output of U74 is high, enabling U70, and coupling VC at pad P3 to terminal 151. The least significant bit is now low, and the output of U56 is high, enabling U60, and coupling VN at pad P2 to terminal 150, Each succeeding count for the states (CS3, CS4, CS5, CSO, etc.) which follows, connects an unenergized winding to the input of the Integrated Amplifier, and does so in a polarity which is opposite to that of the preceding connection (i.e., with neutral connection to terminal 150 on even counts, and to terminal 151 on odd counts).

Fig. 3 illustrates the winding stage selection which is made by the input gating as a function of the counter states. During CSO, both winding stages B and C are energized; therefore winding stage A, which is unenergized is sensed via gate U62. During CS1, both winding states A and C are energized; therefore winqijnq_ stage B is sensed via gate U68. During CS2, both winding stages A and B are energized; therefore winding stage C is sensed via gate U70. During CS3, winding states B and C are energized; therefore winding stage A is sensed via transmission gate U64. During CS5, winding stages A and B are energized; therefore winding stage C is sensed via gate U72.

INTEGRATING TRANSCONDUCTANCE AMPLIFIER 14 1 The Integrating Transconductance Amplifier is illustrated in Figs. 5A, 513, 5C and 5D. Fig. 5A illustrates all the active circuit elements of the amplifier less the resistances in the amplifier current sink into which offset currents are introduced to null the amplifier. Figs. 513, 5C and 5D are provided to explain the operation of the Transconductance Amplifier, emphasizing those measures for stabilizing the amplifier transconductance. The current sink resistances (133, 134) are made a part of the Fig. 5B illus- tration without the offsetting means used for nulling the amplifier. In addition, to complete the Transconductance Amplifier, the connections VA and VN to a representative motor field winding stage (A), are shown coupled via two appropriate pairs of voltage dividing resistors, and via two transmission gates to the inputs 150, 151 of the Transconductance Amplifier. The grounding circuit to the divider network including diodes CR2, CR3 and capa- citor C3 are also shown in Fig. 5B.

As shown primarily in Fig. 5A, the Integrating Transconductance Amplifier consists of the transistors Q1 to Q1 1; Q16, Q17; Q18 and Q23 to Q29 and the resistances R1 to R8. The Amplifier consists essentially of a differential input stage (Q1, Q2, Q3, Q4, Q5, Q6) a first current mirror (Q10, 011) coupled to one output (Q5) of the differential input stage; a second current mirror (Q16, Q17) ential input stage; a common gate buffer Q24 coupling the output of the first current mirror to a high output impedance inverting current mirror Q26-Q29; and a commo.i gate buffer Q25 coupled to the output of the second current mirror. The input signal is coupled to the positive (150) and negative (151) input terminals of the differential input stage (Q5, Q6), where the positive input is defined to be the one which drives the upper output device (Q27) and the negative input drives the lower output device (025). The output of the inverting current mirror (026-Q29) appears at the drain of the transistor Q27 and the output of the buffer G25 appears at the drain of Q25. The drains of push-pull connected transistors Q27, Q25 form the output terminal 152 of the Integrating Transconductance Amplifier.

The five transistors Q7, Q8, Q9, Q18 and 023 control the Integrating Amplifier during nulling and capacitor reset. The transistors Q7 and Q8 provide a means for shorting out the differential input to the Integrating Amplifier during nulling and reset of the capacitor C5.

They become operative during the Reset 1 pulse. The transistors Q9, Q18 and Q23 are the means for causing rapid reset of the capacitor C5 after nulling is complete. During the Reset 2 pulse, transistor Q9'disables the cur- rent sink Q10, Q1 1; Q18 disables the current sink Q16, Q17; while Q23 enables the upper current mirror Q26-Q29 to supply the desired charging current via Q27. 1; The input differential amplifier stage of the Transconductance Amplifier consists of the differentially connected Pchannel transistors Q5 and Q6. The input signal at the positive terminal 150 is coupled to the gate of Q5, and at the negative input terminal 151 is coupled to the gate of Q6. The source of Q5 is connected via a degenerating 200092 resistance R1 to the drain of P-channel transistor Q4 for the supply of current to Q5. The source of Q6 is connected via a degenerating 2000EI resistance R2 to the drain of Q4 for the supply of current to Q6. The resistances R1 and R2 provide current series feedback as symbolized in Fig. 5D for stabilizing the Amplifier Transconductance.

The transistors Q1, Q2, Q3, Q4 supply a fixed current (typically 250,uA) to the sources of transistors Q5 and Q6. Serially connected N-channel transistor Q1 and P-channel transistor Q2 are current references establishing the output current of the current source. The tran- sistor Q2 has its source connected to Vdd, and its drain connected to the drain of transis tor Q1. The drain and gate of Q2 are con nected together. The source of Q1 is con nected to the IC ground and the gate of Q1 is connected to Vdd to establish conduction in the series connected Q1, Q2 transistor pair.

The geometry selection 200/4 gate (gate width to gate length) for Q2 and 4/4 for Q1 coupled to the other oLjtput (Q6) of the differestablishes a current of typically 250,uA in Q1 19 GB2177272A 19 and Q2. The output P-channel transistor Q3 of the current mirror, which has its source con nected to Vdd, has its gate connected to the gate of Q2.

Transistor Q3, which has similar geometry (200/4) to Q2, is held at a gate to source voltage equal to that of Q2, and tends to 11 mirror" an output current equal to the cur rent in the reference at its drain. The drain of Q3 is coupled to the source of current source 75 buffer P-channel transistor Q4. Transistor Q4 is of large design (500/4) to obtain a low drain to source saturation voltage, and has its gate coupled to a 5.8V reference (formed of a plurality of series connected transistors) set to 80 establish conduction in Q4. The current output of the current source (Ql-Q4) appears at the drain of buffer transistor Q4, which is coup led, as already noted, to supply current (250,uA) to the transistors Q5 and Q6 of the differential input stage.

The signal voltage coupled between the gates of Q5 and Q6 produces two output signal currents at the drains of Q5 and Q6, re- spectively. As earlier defined, the gate of Q5 may be regarded as the input to the positive 1. channel" of the Transconductance Amplifier since it controls the conduction of output transistor Q27. Conduction of Q27, which is the upper member of the push-pull output pair, "supplies" current from the positive (Vdd) supply to the load. For similar reasons the gate of Q6 may be regarded as the input to the negative channel of the amplifier, since it controls the conduction of Q25, which "with- draws" current from the load toward (Vss) at IC ground.

The signal current appearing at the drain of Q5 is coupled to the drain of N-channel tran sistor Q10, the input current reference of the 105 first current mirror (Q10, Q1 1) in the positive channel. The source of Q10 is connected through a tapped 2000 ohm resistance R3 (best shown in Fig. 7) to the IC ground. The gate of Q10 is coupled to the drain of transistor Q10. The configuration tends to establish a series current bias of approximately 125,uA in Q10 (half of the Q output current) and in Q5. The gate of Q10 is coupled to the gate of the mirror output N-channel transistor Q1 1, whose source is connected through a tapped 2000 ohm resistance R4 (best shown in Fig. 7) to the IC ground. The appearance of a signal current in Q10 produces a nearly equal mirrored signal output current in the mirror output transistor Q1 1. The current transfer accuracy of the mirror is in part due to the magnitude of the degenerating resistances R3 and R4.

The signal current appearing at the drain of Q6 is coupled to the drain of the N-channel transistor Q16, the input current reference of the second current mirror in the negative channel. The source of Q16 is connected through a 200092 resistance R5 to the IC ground. The gate of Q16 is connected to the drain of Q16. The configuration tends to establish a series current bias of approximately 125/tA in Q16 (half of the Q4 current) and in Q6. The gate of Q16 is coupled to the gate of the mirror output N- channel transistor Q17, whose source is connected through a 2000 ohm resistance R5 to the IC ground. The appearance of a signal current in Q16 produces a nearly equal mirrored signal output current in the mirror output transistor Q17. The current transfer accuracy of the mirror is in part due to the magnitude of the degenerating resistances R5 and R6.

The output current appearing at the drain of transistor Q1 1 in the first current mirror in the positive channel is connected to the source of the large geometry (500/4) N-channel buffer transistor Q24. The gate of Q24 is returned to a 3.2 volt reference voltage supply. The output current of buffer transistor Q24 is coupled from the drain of 024 to the input of the polarity inverting current mirror 026-Q29 from which a part of the amplifier output is derived. The common gate configuration of Q24 accurately preserves a unity current transfer ratio between the source of Q24, which is held to equality with the output current of the first current mirror Q1 1 and the current at the drain of Q24 into which the current from the polarity inverting current mirror is drawn.

The output current appearing at the drain of the transistor Q17 in the second current mir- ror in the negative channel is connected to the source of the large geometry (500/4) N-channel buffer and output transistor Q25. The gate of Q25 is returned to the 3.2 volt reference voltage supply shared with the gate of Q24. The output current of buffer transistor Q25 enters the drain of Q25 from the Integrating Amplifier output terminal 152.The common gate configuration of Q25 accurately preserves a unity current transfer ratio between the source of Q25, which is held to equality with the output current of the second current mirror Q17, and the current at the drain of Q25, connected to the output terminal 152 of the Integrating Amplifier.

The output current appearing at the drain of the buffer transistor Q24 in the positive channel is coupled to the input of the modified Wilson current mirror employing transistors Q26 to Q29. These transistors are all P-chan- nel devices of 200/4 geometry. The mirror, which has a current transfer ratio very closely approximating unity, inverts the signal current direction, and exhibits a high output impedance. The drain of Q24 is connected to the gate of the P-channel transistor Q27 whose drain is connected to the amplifier output terminal 152. The drain of Q24 is also connected to the gate of the P-channel transistor Q26, whose gate and drain are joined. The transistor Q27 is serially connected with the GB2177272A 20 P-channel transistor Q29. The source of Q27 is connected to the drain of Q29, with the source of Q29 being connected via the 300092 resistance R8 to the Vdd supply, and the gate and drain of Q29 being joined. By these connections the current in Q29 is forced into equality with the current in Q27. Continuing, P-channel transistor Q28 has its gate connected to the gate of Q29, and its source connected via the 300OLI resistance R7 to the Vdd supply. By these connections Q28 tends to mirror the current in Q29. The mirror is completed by the connection of the drain of Q28 to the source of Q26. The serial connec- tion of Q24, Q26, and Q28 forces the current in all three transistors into equality with the positive channel signal current in Q24. The result of the foregoing four transistor configuration is to transfer the positive channel signal current from the drain of Q24 in inverse polar- 85 ity to transistor Q27, where it is of a polarity to supply current from Vdd to the output terminal 152.

The Transconductance Amplifier output stage may also be regarded as two current sources (026-Q29; and Q16, Q17, Q25) in push-pull with output transistor Q27 tending to supply current to the output terminal from a source at Vdd potential, and the output transistor Q25 tending to withdraw current from the output terminal of the IC ground. The consequence of the serial connection of two current sources is that the output voltage is not defined until a current exchanging load has been connected to the Amplifier output termi- 100 nal. In the event that the circuit load is the gate of an FET, which draws negligible current, any slight asymmetry in current gain or dc imbalance between positive and negative channels will force the output potential toward either the Vdd or Vss determined limits. If the load is of relatively low impedance in relation to the output impedance of the Amplifier, such as a relatively "large" capacitor operating with a relatively "short" time constant, and further assuming that the input impedance of the Amplifier is large relative to the source impedance (which is true for FETs), then the Transconductance Amplifier is operated in the natural mode, and the output current closely equals the input voltage times the design transconductance of the Amplifier. Further, we may assume that the differential input stage, and the three current mirrors have a high de- pendency on processed resistances rather than on Gm dependent parameters alone for defining the Gm of the initial stage and for maintaining equality in the current ratios of the subsequent current mirrors. The uncertainty in amplifier Gm may be reduced by a factor greater than two using the indicated parameters. These measures on the IC have provided an accurate amplifier Gm, avoiding the need for compensation external to the inte- grated circuit.

Matched pairs of resistors used in the Amplifier mirrors are implemented using interdigitated polysilicon tunnels which are readily available on the conventional gate array.

These tunnels are located in a column between the input/output cells and the body of the array. In a custom IC design, these resistances would be produced using polysilicon in an interdigitated configuration This process im- proves the ratio matching of the individual resistances and improves the accuracy of the current mirror.

Means are also provided on the IC for offsetting any imbalance between the positive and negative channels of the Transconductance Amplifier (i.e. the Autonull Circuit 143).

The five transistors Q7, Q8, Q9, Q18 and Q23 earlier mentioned control the Integrating Amplifier during nulling and reset of the capacitor C5. The transistors Q7 and Q8 are two N-channel devices of 100/4 geometry having their drains connected, respectively, to the amplifier input terminals 151 and 150, and their sources connected together to a 3 volt voltage reference (Vref 1). The gates of Q7 and G8 are connected together for application of the Reset 1 waveform available from the Comparator Network (D16 Q). They short out the differential input, and maintain both channels at a normal level of conduction when the Reset 1 pulse is high for nulling the Amplifier, and for facilitating reset of the capacitor C5.

The transistors Q9, Q18 and Q23 are designed to create a high output current during reset of the capacitor C5, under the control of the Reset 2 waveform. The transistors Q9 and Q18 are two N-channel devices of 200/4 geometry. Transistor Q9 has its drain connected to the gates of the transistors Q10, Q1 1 in the first current mirror and its source connected to the IC ground. Transistor Q18 has its drain connected to the gates of the transistors Q16 and Q17 in the second current mirror and its source connected to the IC ground. The transistor Q23 is an N-channel device of 4/10 geometry having its drain connected to the gates of the transistors Q26 and Q27 of the inverting current mirror, and its source connected to the IC ground. The gates of transistors Q9, Q18 and Q23 are connected together for application of the Reset 2 waveform available from the Comparator Network. When transistors Q9 and Q18 are conductive as by application of the Reset 2 waveform, the gates of the current mirrors Q10, Q11 and Q16, Q17 arQheld at nearIC ground potential, and the output sinking currents are turned off. When transistor Q23 is conductive, as by application of the Reset 2 waveform, the upper current mirror is turned on, and a large current becomes available via transistor Q27 for resetting capacitor C5.

COMPARATOR NETWORK 142 The Comparator Network 142 accepts the 21 GB2177272A 21 output current from the Integrating Transconductance Amplifier 141, "integrates" that current in the integrating capacitor C5, and by measuring the change in voltage on the capa- citor by comparisons to internal voltage references determines the commutation instant. As earlier noted, the amplifier output current is proportional to the reverse electromotive force (or voltage) induced in the unenergized wind- ing. If that voltage is integrated from the reference rotor position, where the voltage reverses in direction, or zero, an accurate measure of the actual rotor position may be obtained with respect to reference position. Since the amplifier produces an output current proportional to input

voltage, an integration of the amplifier output current equals an integration of the voltage (assuming appropriate limits of integration). The Comparator Network 142 produces an output pulse (Reset 1) when the measured voltage change has reached the correct value, and causes commutation. In addition, the Comparator Network, in cooperation with the Autonull Circuit 143, is used to sense the correction of imbalance in the Integrating Amplifier. In nulling the Integrating Amplifier, which occurs once for each commutation in the present arrangement, an offset current is incremented until the output current of the Transconductance Amplifier reverses in direction (passes through zero). When that occurs, the Comparator Network produces an output pulse (Reset 2) terminating the nulling process, causing "reset" of the integrating capacitor C5 and re-instituting timing for the next commutation event.

The Comparator Network 142, which performs the foregoing functions in timing the commutation and amplifier nulling, consists of a transmission gate U85 and accompanying inverter U84, three comparators (COM 1-3), each followed by a hysteresis gate U79-U81, respectively, two flip-flops D16, D17; and a NOR gate U83.

The Comparator Network 142 is connected as follows. The output terminal 152 of the Integrating Amplifier is coupled to the signal input terminal of the transmission gate U85, and to the negative input of the comparator COM 3. The transmission gate is a bidirectional device consisting of two complementary field effect transistors connected in parallel, and requiring oppositely sensed control voltages at the control terminals. The control vol- tage for UK85 is derived from the Autonull Circuit (D7 (1) and is coupled to one control terminal uninverted and to the other control terminal inverted by means of the inverter U84. The signal output of the transmission gate U85 is connected to the pad P1 for connection to the integrating capacitor C5, to the positive input terminal of the comparator COM 1, and to the negative input terminal of com parator COM 2.

The individual comparators, which monitor the voltage on the capacitor C5 and/or Amplifier output, are respectively COM 1, the reset comparator, which terminates capacitor reset; COM 2, the comparison means for timing the commutation instant; and COM 3, the nulling comparator.

The inputs of the three comparators COM 1-3 are connected as follows. The positive input of COM 1 is connected to the signal output of the transmission gate U85 and via the pad P1 to the integrating capacitor C5. The negative input of COM 2 is also connected to the signal output of the transmission gate U85 and the integrating capacitor C5. The negative input of COM 1 is connected to the high (e.g. 6.5 volts) voltage reference Vref 4. The positive input of COM 2 is connected to the low (e.g. 3.0 volts) voltage reference Vref 3. These voltage references (Vref 4 and Vref 3) set the difference in voltage through which the capacitor C5 is discharged to time the commutation degrees from zero winding voltage. The amplifier output 152 is connected to the negative input to comparator COM 3. The positive input of COM 3 is coupled to an intermediate (e.g. 5.5 volts) voltage reference Vref 2. Comparator COM 3 senses the output voltage of the Integrating Amplifier during nulling (when the Inte- grating Amplifier is disconnected from the integrating capacitor), and detects when the output voltage of the Integrating Amplifier is failing from Vdd saturation toward Vss to terminate nulling.

The outputs of the comparators COM 1-3 are coupled to the hysteresis gates U79-U81, flip-flops D16 and D17, and the NOR gate U83 of the Comparator Network as follows. The output of the comparator COM 1 is coup- led via the inverting hysteresis gate U79 to the reset (R) terminal of the flip-flop D16. The output of the comparator COM 2 is coupled via the inverting hysteresis gate U80 to the clocking terminals (C) of D16 and D17. Both D 16 and D 17 are designed to trigger on the negative going edge of a clocking waveform. The output of the comparator COM 3 is coupled through the non-inverting hysteresis gate U81 to the reset (R) terminal of D 17, and to the Autonull Circuit 143 (D7; D input). The output of U81 is denominated the---NullSetwaveform. It is used to signal that the Amplifier output, initially set to maximum offset by the Autonull Circuit, has increased from Vref 2 at the input to COM 3, and is now ready to decrement the initial offset, toward whatever lesser value is required to achieve a null. The data (D) inputs of D16 and D17 are both coupled to Vdd. The set (S) terminals of D 16 and D17 are coupled to the POR 150 (POR output of U120). The Q output of flip-flop D16, denominated---Reset1-, is a waveform coupled to the Modulo 6 Counter 144 (D1-D3 C inputs); to the Input Gating 140 (U55, U56, U73-U78); to the Integrating Transconduc- 22 GB2177272A 22 tance Amplifier 141 (Q7, Q7); and to the Con- 20KHz clock pulse and the charging '. reset" trol Logic 145 (1.113). The d output of D16 is of capacitor C5 toward Vdd commences. The connected to one input of NOR gate U83. The duration of the nulling period is a variable de NOR gate U83 "NORs" the "Null Output" sig- pending upon the amplifier imbalance. The nal of the Autonull Circuit 143 (D7; Q) with 70 maximum count available in the present design (D16; (5) to produce the "Reset 2" waveform allows for 32 counts at the 20KHz clocking which is coupled to the Integrating Amplifier rate or approximately 1.5 milliseconds for a 141 (Q9, Q 18, Q23). The D 17; Q output, maximum duration for nulling. Assuming a re denominated the "Null Clock" waveform is set time of about 5 milliseconds, the nulling is coupled to the Autonull Circuit 143 at the in- 75 designed to accommodate a motor of the indi put to inverter U92. The output of U92 (Null cated design rotating at 20- 200 rpms, allow Clock Inverted), is coupled to the C input of ing an interval of from 17 to 170 ms between D6 and to the R inputs of 137-1312. The Null commutations.

* Clock waveform resets and holds the flip-flops D7-D12 until termination of the Null Clock interval which ends when the amplifier output exceeds Vref 2, and is ready to decrement toward a null.

The operation of the Comparator Network is illustrated in Fig. 8. The commutation period varies from 17 to 170 milliseconds depending on motor speed. The capacitor integration period begins when the voltage at the output of the Integrating Amplifier exceeds Vref 4 (the threshold of COM 1), and reset of the capacitor C5 is complete. The transmission gate U85 became conductive 3 to 5 milliseconds earlier, allowing reset to commence. When U85 is conducting, the output of the Integrat- ing Amplifier 141 is connected to the integrating capacitor C5, to the positive and negative inputs respectively of the comparators COM 1 and COM 2.

The transmission gate U85 is turned on when reset of the capacitor C5 is occurring at the conclusion of nulling. The transmission gate U85 remains conductive during the period that capacitor integration is occurring, and is non-conductive during amplifier nulling (Null

Output waveform: D7, d high). The gate U85 becomes non-conducting when the Comparator COM 2 signals that the voltage on the capacitor C5 has fallen below Vref 3, causing the Reset 1 pulse to be generated and the nulling of the Amplifier to commence.

During amplifier nulling (Null Output D7 (I high), the output of the Integrating Amplifier 141 is disconnected by transmission gate U85 from the integrating capacitor C5, and from the positive and negative inputs respectively to the comparators COM 1 and COM 2, but the amplifier output remains connected to the comparator COM 3. During nulling (as will be explained) the Integrating Amplifier is initially driven to force the output to go high. The balancing process decrements the offset to the point where a current reversal occurs at the output of the Integrating Amplifier, causing the amplifier output voltage to fall precipi- tously toward Vss. The fall is intercepted at Vref 2 by COM 3 which generates a pulse as the null is achieved, which terminates the nulling sequence upon the next 20KHz clock pulse. The transmission gate U85 also re-con- nects the integrating capacitor at the same The Fig. 8 waveform illustrates both the ap- proximate time scale (for a fast rotation) and the approximate values of the critical voltages in the commutation timing and nulling process. The voltage of Vref 4 is set slightly less than the Vdd supply voltage less one threshold drop plus "one Vds on" (i.e. Vds which occurs for Ids=0). The voltage of Vref 4 is set close to but below the upper saturation voltage of the Transconductance Amplifier. The voltage of Vref 4 should be small enough to assure that the amplifier saturation voltage is greater than that value. The amplifier output will be forced all the way to positive saturation by the positive back-emf signal which is occuring during this time. An error in commutation degrees may occur if the back emf does not saturate the Transconductance Amplifier prior to the zero crossing of the back emf, and the capacitor does not start to discharge from a full charge. The typical value for a Vdd of 9. volts is 6.5 volts for Vref 4.

The voltage of reference Vref 3 is somewhat arbitrary, and is selected to be significantly below Vdd/2. The voltage of Vref 3 should stay above the negative saturation vol- tage of the amplifier. A typical value for Vref 3 is 3 volts.

The value of Vref 2 is chosen below Vref 4, but the exact value is not critical. Vref 2 is selected to signal the end of the nulling pro- cess. Since the Amplifier 141 is disconnected from the capacitor C5 during nulling, the load on the Amplifier is very light, and the amplifier output voltage falls very rapidly after the null has been crossed. The nulling interval is timed by 20KHz clock counts. Setting Vref 2 too low may allow additional counts to occur after the null, which lessens the accuracy of nulling. A reasonable value for Vref 2 is about 5.5 volts.

A more complete understanding of the Comparator Network 142 requires resort to the timing diagrams of Fig. 12A, in particular, which illustrates the outputs of the comparators COM 1-3 already described, on a time scale large enough to show the individual 20KHz clock pulses, and assumes a nulling procedure requiring only a few increments. The Null Set waveform is alternately the COM 3 output. The drawing also shows the 20KHz clocking pulses, the Null Clocking Signal (D17 23 GB2177272A 23 Q), the Null Output Signal (D7 d) which is high during nulling; the Reset 2 waveform (U83 Output) which is high during capacitor C5 reset; and the Reset 1 waveform (D 16 Q) which is high during nulling and the reset of capacitor C5.

Starting consideration of Fig. 12A from the commutation instant when comparator COM 2 goes high (as the voltage on C5 falls below the 3 volts on Vref 3), the output of compare- 75 tor COM 2 goes high; and the U80 output goes low. With both D inputs of D16 and D17 high by the Vdd connection, the negative going edge from U80 output clocks the Q outputs of D16, D17 high. The Q output of D16 supplies the Reset 1 waveform to the Modulo 6 Counter 144, and the Input Gating 140. The Q output of D 17 (Null Clock) is con nected via the inverter U92 to the C input of D6 and to the R inputs of D7 and of the counter D8-D12. When the Null Clock wave form goes high, Q1 to Q5 go low; and (11 to Q5 go high. The flip-flops set S5 to S8 high and set S1 to S4 low, acting via gates U99-WO6. As will be explained, this forces 90 the output (152) of the Integrating Amplifier to swing from low starting from Vref 3 (e.g. 3 volts) toward high (6.5 volts) as shown in Fig.

8.

The Null Clock waveform going high also resets flip-flop D7 (Q low), which in turn di sables the gate U85, disconnecting the Inte grating Amplifier 141 from the integrating capacitor C5, allowing the autonulling se- quence to begin.

As the voltage at the output (152) of the Integrating Amplifier increases through Vref 2 (5.5 volts), see Fig. 8, the output COM 3 (U81) goes low, resetting D17 (Q low), re- moving forced reset from the Autonull Circuit, and the autonulling process begins (which will be treated subsequently). When the output of U92 goes high, flip-flop D6 is set by its positive going edge. This enables U93, which allows the clock signal to reach the counter D8-D 12.

When the decrementing causes a downward swing in the Amplifier output (see Fig. 8) below Vref 2 at the input to COM 3, a balance has been detected, and nulling is terminated. The output of COM 3 (U81) and the Null Set waveform goes high. This causes the D input to D7 to go high. The clock input to D7 is coupled to the output of U93, which NANDS the 20KHz clock (CLK) with the output of D6 (now high). When the next 20KHz pulse occurs after D7:D has gone high, U93 clocks D7, and the null output (D7 (1) goes low. The immediate effect of this (D7 (1) low output is to enable the transmission gate U85. This connects the Integrating Amplifier to C5. Simultaneously, with both D16, (1 low, and D7, (1 Icw, NOR gate U83 goes low, initiating the Reset 2 pulse. When D7, Q goes low, D6 is reset (Q low). This disables U93 removing the clock signal from the counter -freezing- the count at its present value.

As Reset 2 goes high, the Integrating Amplifier via Q9, Q 18 and Q23 begins to supply charging current to reset C5. The capacitor continues to charge until Vref 4 is exceeded at the input to Cl (see Fig. 8). When COM 1 goes high (in about 4 milliseconds), D16, (1 goes high, and Reset 2 is also terminated, discontinuing the resetting of C5, and allowing the capacitor integration period to begin.

In the event of significant imbalance---off--the IC, e.g. due to errors in the resistance ratios of the resistor divider network 125, a discharge means should be provided for C5 to prevent this imbalance from halting the application of successive starting commutations to the motor and preventing starting. The NPN transistor 0,92, having its collector connected to the pad Pl, its emitter returned to ground through 240K resistor R41, and its base coupled to node 129 to provide forward bias, is the preferred discharge means. A resistor could be used (approximately 2 meg. ) but it has the disadvantage of having a relatively small current near the lower threshold of Vref 3 (2-1/2 to 3 volts). The current error produced in the single in line package---SIP---resistor network 125 could be as high as 2pamps, which is enough to prevent the circuit from reliably starting.

The transistor current source herein provided has the same average current as the current that is generated when the trip voltage is reached and should always be capable of (1) overcoming th error in the single in line package (SIP) resistor network, and (2) providing a commutation period in excess of 0.2 seconds for good starting performance. The current is set for at least 21/2pamps which provides a commutation period of 0.3+ sec. with the indicated.15,uf capacitor C5 and provides a margin over the 2pamp SIP error.

The upper limit for current drain is approxi- mately 3.5pamp because this will provide a starting period of 0.2 sec., the smallest permissible to guarantee smooth starting performance. The lower limit for current drain is approximately 2pamps, which is set by the cur- rent error due to the SIP resistor tolerance.

The offset error in commutation timing caused by the current source Q92 becomes negligible at medium and high RPM.

THE AUTONULL CIRCUIT 143 The Autonull Circuit "Nulls" the Integrating Transconductance Amplifier 141 to remove any error in timing the commutation instant attributable to amplifier input offset and to improve motor starting performance. As shown in Fig. 8, the autonulling circuit is operative after the commutation instant.

The commutation instant occurs when the voltage on the Capacitor C5 falls below Vref 3 applied to COM 2, which causes D16 Q, at 24 GB2177272A 24 which the Reset 1 waveform is derived, to go high, and the Null Clock waveform derived at D 17 Q to go high.

When the Reset 1 waveform goes high, the switches Q7 and Q8 at the input to the Inte grating Amplifier are turned on, shorting out any differential input voltage at the gate of the input transistors Q5 and Q6. At the same time, the gates of both Q5 and Q6 are re turned to a 3 volt reference (Vrefl), selected to be equal to an average value of the ampli fier common mode voltage over the normal operating range.

The Null Clock waveform from D 17 Q is coupled to the Autonull Circuit. It causes D7 Q to produce the Null Output waveform which is coupled back to the input to the transmis sion gate U85, disabling the gate and discon necting the output of the Integrating Amplifier from the Capacitor C5 and the Comparators COM 1 and COM 2.

The Null Clock waveform from D 17 Q also resets and holds the Autonull Circuit in a preassigned initial state in which a maximum offset (+12pa) is applied to the Integrating Amplifier sensed to produce an assured cur rent supply at the amplifier output.

By these three events, the output voltage of the amplifier previously at 3 volts, begins to climb, and when it exceeds 5.5 volts at Vref 95 2, COM 3 produces a low in the Null Set waveform. The low in the Null Set waveform is accompanied by a low in the Null Clock waveform at D17 Q. This releases the Auton ull Circuit from its initial state, and allows decrementing of the offset at the amplifier input.

Decrementing occurs at the rate of the 20KHz clock coupled to the input of gate U93. When the output voltage of the amplifier fails below Vref 2, balance is achieved.

At the next clock pulse, the Null Output wa veform (D7 d) goes low, enabling the transmission gate U85, and causing the gener ation of the Reset 2 pulse, which as earlier noted, turns the Integrating Amplifier into a maximum current supply mode (150pa) for charging Capacitor C5. When the upper vol tage reference Vref of 6.5 volts is crossed, both Reset 1 and Reset 2 terminate, and the next capacitor integration period commences.

The Autonull Circuit 143 is depicted in Fig.

7. It includes the resistive elements (R3, R4) of a modified current mirror (Q10,Q1 1), which is in one channel of the two channel differen tial input Integrating Trpnsconductance Ampli fier 141. The current mirror is modified by the inclusion of means for introducing a digitally controlled offset current (S1-S8, G65-Q68), a counter (D8-1)12) for achieving a large initial current offset followed by an ordered decre menting of the offset current to the desired final value, the counter also storing the final decremented state, a decoder (U99-1J106) for translating the counter state to appropriate offset current settings, and control logic inter- 130 facing with the remainder of the control IC for initiating the nulling process and for terminating the process when a null in the amplifier output has been produced.

The digitally controlled current mirror consists of a first set of 4 digitally scaled resistances R3A, R3B, R3C and R3D and a second set of 4 digitally scaled resistances R4A, R4B, 114C and R4D; a first set of four N-channel transistor switches S8-S5 associated with the first set of resistances R3A-D; a second set of four N-channel switches S4-S1 associated with the second set of resistances; a set of four P-channel current source transistors Q68-Q65, each associated with the supply of current to a switch in each set of switches; and a current reference made up of transistors Q59-Q64 for the current sources Q65-Q68.

The elements of the decrementing current sink are interconnected as follows. The resistances R3A, 13313, 133C and R3D are serially connected in the order recited between the source of the reference transistor 010 in the current mirror Q 10, Q 11 and the IC ground, while the resistances R4A, R4B, R4C and R4D are serially connected in the order recited between the source of the output transistor Q1 1 in the current mirror. and IC ground. The "A" resistors are of 4 units magnitude, e.g., 100092; the "B" resistors are of 2 units magnitude, e.g. 500Q; and the "C" and "D" resistances are of 1 unit magnitude, e.g. 250Q.

A current source is provided for supplying current via a first transistor switch to each tap on R3, or via a second transistor switch to a corresponding tap on R4. Starting from the taps above R3D and MID, the current source Q65 has its source connected to Vdd, and its drain jointly connected to the drain of transis- tor switch S5, whose source is connected to the series resistance R3 above 1331), and to the drain of transistor switch S1 whose source is connected to its series resistance R4, above 1341). The current source Q66 has its source connected to Vdd, and its drain jointly connected to the draiq of transistor switch S6, whose source is connected to the series resistance R3 above 133C, and to the drain of transistor switch S2 whose source is connected to the series resistance R4, above 134C. The current source Q67 has its source connected to Vdd, and its drain jointly connected to the drain of transistor switch S7, whose source is connected to the series re- sistance R3 above R3B, and to the drain of transistor switch S3 whose source is connected to the series resistance R4 above R4B. The current source Q68 has its source connected to Vdd, and its drain jointly connected to the drain of transistor switch S8, whose source is connected to the series resistance R3 above R3A, and to the drain of transistor switch S4 whose source is connected to the series resistance R4, above 134A.

The current sources Q65-Q68 are of 45/12 p GB2177272A 25 geometry and have four gates tied to a com mon current reference comprising the transis tors G69-Q64. The current reference transis tors are connected in two series paths. The P-channel transistor Q59 has its source con- 70 nected to Vdd and its drain connected to the drain and gate of N-channel transistor Q61.

The source of Q61 is connected to the drain and gate of N-channel transistor Q62. The source of Q62 is connected to the drain and gate of N-channel transistor Q63, whose source is connected to IC ground. Transistor Q59 is of 4/40 geometry, while transistors Q61-0,63 are of 25/4 geometry. The second series path in the reference comprises a P channel transistor Q64 having its source con nected to Vdd and its gate and drain tied together and to the drain of N-channel transis tor Q60. The source of Q60 is connected to IC ground and the gate is connected to the interconnection between Q59 and Q61. The arrangement establishes a current of about 18 microamperes in the reference and because of the geometry ratio, currents of about 6 pa in each of the current sources Q68-0.65.

A current offset between input and output current in the Q10, Q1 1 current mirror of the Integrating Amplifier is achieved by the settings of the respective switches S1 to S8.

The gate to ground voltage of the transistor G1 1 is held into equality with the gate to ground voltage of Q10. If all switches S1-S8 are off, and assuming that the resistances R3 and R4 are equal, then the current in Q '11 will accurately mirror the current in Q10. If, however, a 6lia current is injected into a part of R3 (e.g., R3D by conduction of switch S5,) a small increase in gate to ground voltage will occur in Q10; and the increase in current should cause an equal IR drop in R4. Since R3D is 1/8th of the total resistance of R3, which equals R4, the 6pa current injected by Q65 in R3D produces a positive offset of ap proximately 6/8pa in the output current of the mirror. If all switches S5 to S8 are conduc tive, a positive offset of approximately 12pa in output current in Q1 1 may be expected with respect to the input current in Q10.

If switches S4 to S 1 are operated, it being assumed that switches S8 to S5 are open, 115 then the output current is decreased in relation to the input current by comparable decre ments: 6/8pa when S1 is conductive, and negative offset of approximately 12pa when S1-S4 are all conductive. The result is to give 120 a control range of approximately 24pa for null ing the amplifier.

The immediate control of the states of the switches S1-SEI, which control the offset cur- rent in the current mirror is provided by the 5 stage counter D8-D12, and the decoder consisting of 8 NOR gates U99-U106 interconnecting the output stages of the counter to the gates of the individual switches. The counter is in turn controlled by the control logic which comprises the gates U92-1J194 and the flip-flops D6 and D7. The decrementing of the counter occurs at the 20KHz clock rate of the Oscillator 147.

The switches, counter, decoder and control logic of the Autonull Circuit are interconnected and exchange control waveforms as follows. The two control waveforms applied to the Autonull Circuit are the Null Clock waveform derived from D 17 Q and the Null Set waveform derived from the comparator COM 3 (i.e., U81) both in the Comparator Network 142. The Null Clock waveform is connected to the input of inverter U92, whose output is coupled to the C input of the flip-flop D6 and to the R input of the flipflop D7 and to the R inputs of the counter D8-D12. The D input of the flip-flop D6 is connected to Vdd. The Q output of D6 and the 20KHz clocking wave- form CLK from Oscillator 147 are each coupled to one of the two inputs of NAND gate U93. The output of the NAND gate U93 is directly coupled to the C input of D7, and after inversion by inverter U94, is coupled to the C input of D8, the first flip-flop in the 5 stage counter.

The Null Set waveform is coupled to the D input of the flip-flop D7. The (1 output of D7 is coupled to the R input of P6. The Null Output waveform of the Autpnull Circuit, responsive to detection of a Null by the COM 3 in the Comparator Network, is derived from D7 d.

In the 5 stage counter, the count is propa- gated by connecting the Q1 output of D8 to the C input of D9. Similarly, the Q2 output of D9 is connected to the C input of D 10; the Q3 output of D10 is coupled to the C input of D 11, and the Q4 output of D 11 is connected to the C input of D12. Also on the Counter, the D and (11 terminals of D8 are joined, as are D and d2 terminals of D9. Similarly, the D and d3 terminals of D 10 are joined, the D and d4 terminals of D '11 are joined, and the D and d5 terminals of D 12 are joined.

The 8 NOR gates (U99-U 106) form the decoder which translates the states of the counter D8-D 12 to appropriate settings for the switches S1-SI3 in achieving the desired offset current. The 4 NOR gates U 103 to U 106 couple the Q1 to Q5 inputs to the switches S5-S8. More particularly, the NOR gate U103 has one input connected to Q1 and one input connected to Q5 and its output connected to the gate of S5. NOR gate U 104 has one input connected to Q2 and one input connected to Q5 and the output of U 104 is connected to the gate of S6. Similarly, one input of NOR gate U 105 is connected to Q3 and one input is connected to Q5, and the output of U 105 is connected to the gate of S7. Similarly, one input of NOR gate U 106 is connected to Q4 and one input is connected to Q5 and the output of U 106 is connected to the gate of S8. If Q5 is low, the NOR gates U 103-U 106 26 GB2177272A 26 are enabled so that a low on any of the Q1-Q4 counter terminals will produce a high at the output of the appropriate NOR gate and turn on the appropriate switch S5-S8.

The 4 NOR gates U99 to U102 couple the (11 to d5 outputs of the counter to the swit ches S1-S4. More particularly, the NOR gate U99 has one input connected to (11 and one input connected to d5 and its output con nected to the gate of S1. NOR gate 100 has 75 one input connected to d2 and one input con nected to (15 and the output of U100 is con nected to the gate of S2. Similarly, one input of NOR gate U101 is connected to (13 and one input is connected to (15 and the output 80 of U101 is connected to the gate of S3. Simi larly, one input of NOR gate U 102 is con nected to (14 and one input is connected to (15 and the output of U 102 is connected tothe gate of S4. If d5 is low, the NOR gates U99-1J102 are enabled so that a low on any of the dl-d4 counter terminals will produce a high at the output of the appropriate NOR gate and turn on the appropriate switch S1-S4.

Resetting the counter produces a maximum positive offset current (12pa) in the current mirrors by initially turning switches S5 to S8 on and S1 to S4 off. The effect of -clocking the current from a Reset condition of the counter is to decrement the maximum positive offset current in 3/4pa decrements through zero offset current until all switches S5 to S8 are off and then to progressively more nega tive offset currents until a maximum negative offset current (12pa) is produced when swit ches S5 to S8 are off and S1 to S4 are on.

The state of the switches and offset cur rents resulting from resetting the counter and then decrementing may be explained as fol lows. The first counter stage D8 is associated with the lowest (first) rank switches S1 and S5. The second counter stage D9 is associ ated with the second rank switches S2 and S4. The third counter stage D9 is associated with the third rank switches S3 and S7. The fourth counter stage is associated with the fourth rank switches S4 and S8.

If the counter D8-1D12 is reset, the Q1-Q5 outputs are set to zero and the dl-d5 out puts are high. Under these conditions, the switches S1-S4 are open and the switches S5-S8 are closed. Accordingly, a maximum positive offset current (12pa) is caused in the output current of the current mirror Q10, 0.11 (and the output of the Integrating Transconductance Amplifier goes high). If the counter is now clocked periodically from the C input of D8, with the stages Q1-Q4 initially at zero, the first clock pulse (after transfer to Q1) will cause the first stage of the counter to go high, which turns off S5 and which produces a 6/8pa decrement in the offset current. The counter state is 00001. The next clock pulse will produce a low at Q1 and a high at Q2.

This will turn switch S5 back on and turn off S6, causing a decrement in current of 11/2pa. The counter state is 00010. This process will continue for 16 counts until all the switches S1-S5 are turned off and the counter state is 01111.

The transfer to a negative offset current occurs at this point in the count. On the next count, Q5 goes high, disabling the gates U 103 to U 106 and the counter state, as seen at the 0.1 to Q5 outputs is 10000. On the same 10000 count, (15 (complementary to Q5) goes low, enabling the gates U99 to U102 so that additional counts will progressively turn on switches S1 through S4. On the same 0 1111 count, as seen at the d 1 to (15 outputs, the switches S5 to S8 are turned off. On the next count, the counter state will be 01110 ' as seen at the Cil to d5 outputs and switch S1 will be turned on. The count will now proceed as before, until all switches S11-S4 have been turned on, producing a maximum negative offset current 12pa, and the counter state is 00000 as seen from the (11 to (15 outputs. In normal operation, the count will be suspended at some point in the counting sequence by detection of a null that will halt the count between the maximum positive offset current and the maximum nega- tive offset current.

Assuming that the comparator COM 2 has gone high to signal the commutation instant, D 16 Q, at which the Reset 1 waveform appears, goes high. The Reset 1 waveform shorts out the differential input to the Integrating Transconductance Amplifier input, readying it to begin the nulling process. Clocked also by the output of COM 2, D 16 Q, at which the Null Clock waveform appears, goes high. The Null Clock waveform is coupled via the inverter U92 to the clock input of D6 to the resets of D7 and the counter stages D8 through D12.

The D input to D7, which is coupled to the output of COM 3 (i.e., U8 1) has been high since the amplifier output fell below 5.5 volts. Thus, the Null Clock waveform at the reset input of D7 produces a high at the D7 (1 output at which the Null Output waveform ap- pears. The Null Output waveform is coupled back to one input of the NOR gate U83 and to the control input of the transmission gate U85. While no change occurs at the NOR gate U83, the transmission gate is disabled, and the output of the Integrating Amplifier is now disconnected from the integrating Capacitor C5 and from the inputs to the Comparators COM 1 and COM 2. The amplifier output is now ready for nulling.

With the Null Clock waveform high, the counter is reset and held in a reset state in which a maximum positive offset current is produced. At this point, the differential amplifier input is shorted, a maximum positive off- set current is introduced at the input, and the 27 GB2177272A 27 amplifier output, disconnected from the Capa citor C5, is coupled to the comparator COM 3, and the counter (138-1312) is reset, holding the offset current at the maximum value. The output voltage of the amplifier which was near 3 volts upon commutation, begins to increase.

When the amplifier output voltage exceeds 5.5V, COM 3 goes low, resetting D17 Q (i.e., Q goes low), and the Null Clock waveform appearing at D 17 Q goes low. The Null Clock waveform coupled via U92 and inverted to a high, releases D7, and releases the counter D8 to D12, allowing the counter to increment in a direction to reduce the offset current, whenever 20KHz clocking pulses are supplied.

Meanwhile, the 20KHz clock pulses from Oscillator 147 have been coupled to one input of the NAND gate U93, whose other input is coupled to the Q output of D6. The Q output of D6 went high when D7 was reset, enabling NAND gate U93, and coupling clock pulses directly to the C input of D7, and after inver sion in U94 coupling inverted clock pulses to the C input of the counters D8-1)12. The in crementing can now proceed.

The counter continues to decrement the cur rent offset at the 20KHz clocking rate, and the comparator COM 3, to which the amplifier output is connected, senses a drop in the am plifier output voltage. When the voltage fails below 5.5 volts (Vref 2), the Null Set wave form (COM 3 output) goes high, coupling a high to the D input of D7. Upon the next positive going edge of the 20KHz clock pulse (CLK) from U93, coupled to the C input of D7, D7 (1, which provides the Null Output wave form, goes low. When D7 d goes low, it resets D6. (D6 Q goes low.) This effectively disables U93 from coupling clock pulses to D7 and D8. The output of U93, which is now high, is forced to remain high by the applica tion of a low to one input. This also forces the clock input of D8 to remain low, inhibiting another positive going edge from occurring and assuring that the counter state is ---fro zen- at the value which resulted in the null just detected.

The inversion in U94 delays the response of D8 by approximately 300 nanosceonds rela tive to the response of D7. This inversion as- 115 sures that the positive going clock edge of the CLK waveform supplied to D7 occurs about 300 nanoseconds before the positive going clock edge of the CLK waveform sup plied to D8. (The difference is due to the 120 width of the narrow portion of the CLK wave forms. The clock pulse has a duty cycle of less than 1 %.) The Null Output waveform (D7, d) having gone low, is coupled to the transmission gate U85, and to the NOR gate U83. U85 is now enabled and reconnects the output of the Inte grating Amplifier to C5, and to the compara tors COM 1 and COM 2. Simultaneously, U83 with two lows upon its input (D 17 Q low and D7 Cl low) goes high, generating the Reset 2 pulse. The Reset 2 pulse turns on the upper output portion (Q27) of the Amplifier 141, and with the connection made via U85 to the capacitor, the resetting of the capacitor is undertaken as shown in Fig. 8. When comparator COM 1 detects that Vref 4 is exceeded, the next capacitor commutation period begins again.

MODULO 6 COUNTER 144 The Modulo 6 Counter is a reversible counter, which maintains a count of the rotor commutation events and position so that the winding sensing sequence and the winding energization sequence keep in step. The Modulo 6 Counter, consistently with a 6 state succession of energization states, repetitively counts to 6, and each counter state corresponds to one of the 6 energization states illustrated in Fig. 3. As earlier noted, the forward sequence and reverse sequences are both illustrated. The event which steps the counter is the production of the Reset 1 pulse from D16, Q at the commutation instant. One output of the counter (the unenergized winding selection signals), in the form of one unique state at one of 6 sequential positions, is coupled via a 6 conductor connection to the enabling gates U73-U78 of the input gating 140. Another output of the counter deals with two state combinations, suitable when applied to the control logic 145 for forming the energized winding selection signals, for jointly energizing two windings in the stepping sequence illustrated in Fig. 3. A third output of the counter is the "Least Significant Bit" (130; D1Q) used to invert the sense of the neutral winding connection to the input gating (U55, U56) in syn- chronism with the gating waveforms applied to U73-U78. The controls applied to the modulo 6 counter include a Forward waveform from Forward/Reverse Logic 149 (U 112), and a Power on Reset waveform (POR; U120).

The Modulo 6 Counter 144 consists of the following logical elements: three flip-flops D1, D2, D3 forming the memory of the counter; three two input NAND gates U8, U9, U10, associated with D2 for decoding from the counter output stages the correct next state for D2 in either a forward or reverse counting sequence, three two input NAND gates U20, U21, U22 associated with D3 for decoding from the counter output stages the correct next state for D3 in either a forward or a reverse counting sequence; a first rank of three input NAND gates U24-U29, for decoding the memory states of D1-D3 to obtain a unique state (low) which follows the counting sequence; and a second decoder rank of two input NAND gates for detecting 2 state combinations for application to the control logic 145. Finally, a pair of inverters U12, U7 is provided for introduction of the Forward wa- veform to the Counter.

28 GB2177272A 28 The elements of the Modulo 6 Counter 144 are connected as follows. The R inputs of the D1-M flip-flops are connected for power on reset to POR 150 (U120 POR). In starting, FOR- is low, holding D 1, D2, D3 in a Q low Q high state. When FOR goes high, the count may proceed. The D 16, Q output (Reset 1) is connected to the clock (C) inputs of D1, D2 and D3. The d output of D1 is connected to the D input of D1. The Q output of D1 is coupled to one input of NAND gates U25, U27 and U29. The (1 output of D1 is coupled to one input of U24, U26 and U28. The Q output of D2 is coupled to one input of U26 and U27. The (1 output of D2 is connected to 80 one input of U24, U25, U28 and U29. The Q output of D3 is connected to one input of U28 and U29. The (1 output of D3 is con nected to one input of U24, U25, U26 and U27.

The three input NAND gates U24-LI29 in the first rank of memory decoders are arranged by the foregoing connections to provide a consecutive repeating succession of un- ique low states of U24, U25, U26, U27, U28, U29, U24, U25, U26, etc. as the memory of D1, D2, D3 is incremented. At the initial state of the memory, U24 is low. The zero binary state (000) may be verified by noting that U24 has its three inputs connected to D1, d; D2, (1 and D3, d. When the inputs are high, the U24 output is low (and all other NAND gates are high). This is the---CSO-state. Assuming that one count has occurred, and D1, Q is now high, U25 which has its three inputs connected to D 1, Q; D2 d; and D3 (1 (all high), the U25 output is low and the other NAND gates are high. This may be called the binary state 00 1 or the---CS1---state. That this decoding continues may be verified as to each successive counter state. At the next binary state (010 or the---CS2---state): U26 connected to D1, d (high); D2, Q (high); and D3, d (high) goes (low). At the next binary state (011, U27 goes low, etc). The low state remains unique in the NAND gate U24-U29 outputs, which are connected respectively via NOR gates U73- U78 to the inputs of transmission gates U62, U64, U66, U68, U70, U72, respectively, so that only one of the above transmission gates is enabled at one time, and it is enabled in the desired consecutive repeating succession.

The two input NAND gates U30-1J35 in the second rank of memory decoders aid in transferring the state of D1 to D2 to D3 in forward and reverse counting and in commutating the sequence in either a forward or a reverse count. This first requires---ORing-two succe- sive states in the first rank of NAND gates for coupling to the second rank. The second rank is also used to further the decoding required for the Control Logic and Output Drivers. In particular, U30 NANDing the outputs of the U24 and U25, is high on the first two states and goes low on the third state when U24 and U25 are both high, and it remains low until the end of the count. U31 NANDing the outputs of U25, U26 (-S-1, US--2) (equivalent to ORing the active high states CS1, CS2), is low on the first state, high on the next two and low on the last three states. NAND gate U32 NANDs the outputs of U26, U27; NAND gate U33 NANDs the outputs of U27, U28; NAND gate U34 NANDs the outputs of U28, U29; and NAND gate U35 NANDs the outputs of U29, U24.

Only the Forward waveform is applied to the Modulo 6 Counter, and both low and highs of that waveform are used to control the Counter for a forward or reverse count. The Forward waveform from U '112 is applied to U 12, U7. It is inverted in U 12, and reinverted in U7. The U8, U9, U10 gate assembly associated with counter D2 sets the next state for D2 depending on whether the counter is in a forward or reverse mode. Similarly, the U20, U21 and U22 gate assembly associated with counter D3 sets the next state for D3 depending on whether the counter is in a forward or a reverse mode. The gates U8 and U9 have their outputs coupled to NAND gate U 10, whose function is to ---OR-the inputs into the D input of D2. Simi- larly, the gates U20 and U21 have their outputs coupled to NAND gate 22, whose function is to---OR-the inputs into the D input of D3. When the counter is in a forward mode, the gate U9 is driven by U3 1, which decodes states ES-5, U-S2- if a---low-is present on either state it produces a high at the input of U10, which is coupled via U10 to the D input of D2. At the same time the output from U 12, which is in the inverse of the output of U7, is coupled to U8 and to U20. This signal which puts a low on the input of U8 and U20, inhibits the decoded output stage (if low) from being fed back to the D inputs of D2 and D3, respectively.

The transfer of states between flip-flops D1D3 and formation of the desired consecutive repeating succession is performed in the following manner. In the Forward state, the Forward waveform is high (see Fig. 3), and U 12 out is low, U7 is high, making U9 and U21 active in transferring the count D2 and D3. U9 NANDs the output of U7 and the output of U31. U31 is high on the 001 (CS1 low) and 010 (CS2 low) states. On the state 001, U9 goes low, and U10, irrespective of the input, goes high, which is coupled to the D input to D2. Upon the next commutation, Reset 1 clocks a high into the Q oLtut of D2 and D 'I increments again to 010 (CS2 low). On the state 010 (CS2 low), U31 remains high and U9 goes low again, and U10, irrespective of its other input, goes high at the D input to D2. Upon the next commutation, Reset 1 clocks the secon high into D2, and D2 Q stays high (011; CS3 low). Upon the next 29 GB2177272A 29 count, U33 goes high, U21 goes low, and U22 goes high. The next Reset 1 pulse clocks a high into D3, Q out, and a low into the D 'I Out for a (100: CS4 low). The next Reset 1 pulse, U33 remains high and a high is re clocked into D3; Q low into D2, Q; and a high into D1, Q (101: CS5 low). In the next Reset 1 pulse lows are clocked into D3 and D2 and D1 changes state to (000: CSO).

In the reverse state, the Forward waveform is low (see Fig. 3) and U 12 is high, U7 is low making US and U20 active in transferring the count to D2 and D3. The sequence is now inverted with U29 becoming low first (CS5 low); U28 low next (CS4 low), etc. until U24 80 is low last. Assuming the D1, D2 and D3 are low at the start of the count, U29 which is tied to the Q outputs of D1, D2, D3, goes low on the first count corresponding to CS5 low state. (The backward count will continue 85 in the same manner already explained.) The NAND gates U30-U35 also aid in de coding the states E-SO to E-S5 for application to the Control Logic 145. As noted above, U30, which NANDs the U24, U25 outputs, is 90 in an active high state during CSO and" ES---fl; U31 is in an active high state during CS1 and CS2; U32 is in an active high state during E-S2 and CS3; U33 is in an active high state during ES-3 and CS4; U34 is in an active high 95 state during ES-4 and CS5; and U35 is in an active high state during CS5 and CSO. In short, by a 6 count 6 overlapping timing wa veforms have been created, ordered in corre- spondence to the high durations of CT; AS; BT; CB; AT and BB (shown in Fig. 3), respectively. These timing waveforms can be coupled to the Control Logic 145 for timing the output signals coupled to the Output Drivers 146.

The Modulo-6 commutation counter (144) is virtually two counters in one, an up counter and a down counter sharing both the flip-flops D1, D2, D3 and parts of the decoding logic (U10, U22, and U29-U35).

The up or down counter is enabled/disabled by the Forward control signal. When the forward gates U9, U21 are enabled, they decode the outputs of the counter flip-flops D1, D2, D3 and set the inputs of these flip-flops to the values required for the next state.At the rising edge of the RESET 1 signal, these inputs are transferred to the output side of the positive edge triggered'flip-flops (D1, D2, D3).

Since this transition occurs simultaneously with the edge of the incoming RESET 1 signal, each flip-flop is clocked at exactly the same time. This prevents the outputs from changing at different times (i.e., not in synchronization) and causing voltage spikes (glitches) to appear at the counter outputs.

When the outputs of the flip-flops change state at the rising edge of the RESET 1 pulse, they are decoded into a variety of state sig- nals (CSO, CS1... CS5) by gates U24 to U29. Combinations of these states are also decoded by U30 to U35. This decoding occurs, substantially simultaneously with the rising edge of the RESET 1 signal. Any slight delay due to propagation delays (e.g., <100 nanoseconds) through the gates, is several orders of magnitude less than the time it takes for the next rising edge of RESET 1 to occur (milliseconds). Because of this, these signals (which are fed back to the inputs of D1, D2 and D3 to set the next state) will attain a steady value by the time the next rising edge of RESET 1 occurs. Having this stable input available at the inputs of the flip- flops ensures proper "Glitch-free" operation of the counter.

The decoding of each state and synchronous clocking of the flip-flops causes the length of each state to be fixed, and dependent on the length of the RESET 1 pulse and not on the specific state that the counter is in. This is especially important when, in the forward direction, the count reaches 5 and must then go to 0. This counter treats the 5 to 0 transition as just another state transition rather than causing the counter to be RESET when the counter reaches the end of its count. Simply resetting the counter at the end of the count would result in the unwanted shortening of the last state or "Glitches" when performing the RESET. The state transitions for the forward case are 0 to 1, 1 to 2, 2to3, 3to4, 4to 5, 5toO..., etc. The necessary outputs for the "next" state are available from the gates U24 to U29 which decode the individual states and combinations of these states which are available from gates U30-U35 and returned via gates US,U9,U10,U20,U21,U22. The gates U24-U35, serve the dual function of providing the next state to the commutation counter as well as providing an indication of the present state, or combination of states, to other circuits on the chip.

The reverse gates US and U20 operate in a similar fashion when enabled by the forward signal. In the reverse mode though, the state transitions are 0 to 5, 5 to 4, 4 to 3, 3 to 2, 2 to 1, 1 to 0..., etc. As mentioned before, the counter can only change state on the ris- ing edge of the RESET 1 signal. This ensures that even if the count direction is changed from forward to reverse by switching the "Forward" signal line, no pertubations (glitches) will occur in the output of the coun- ter. The counter will stay in the present state for its correct amount of time and will then continue counting in the opposite direction upon the next rising edge of the RESET 1 pulse.

All of the flip-flops of the counter are equipped with an asynchronous RESET. This RESET is controlled by he Power On RESET circuit (150). When the POR line is low, the counter is held in its OOO(zero) start state.

When the RESET line POR is released (allowed GB2177272A 30 to go high), the counter will start counting on the next rising edge of RESET 1 and transition to the next correct state after 0 (5 for reverse direction, 1 for forward direction).

Since there are three memory elements in the counter D1, D2, D3, there are 8 possible states that could occur (0-7). In the event that the counter would find itself in one of the unused states (6 or 7) the counter is designed so that it will transition to a correct state (into the regular counter loop) should one of these states occur. Also the decoder logic U24-U29 has been designed not to decode these two states should they occur. This is so their oc- curance does not cause problems to any other logic connected to this circuit.

THE CONTROL LOGIC 145 The Control Logic 145 accepts the timing information from the Modulo 6 Counter at the outputs of gates U30 to U35, and converts that information into a collection of waveforms suitable for application to the Output Drivers 146 on the IC for application to the three power switches 122, 123 and 124 on the printed circuit board. The Control Logic is timed by a first connection to the Comparator Network 142 for response to the (Reset) waveform (D16 Q), to cause commutation of the switches 122, 123 and 124 at the commutation instants. The Control Logic is controlled for a forward or reverse sequence by two connections to the Forward/Reverse Logic 149 (L1 112 Forward, U 111 Reverse). The out- put (PWiV) from the Pulse Width Modulator 148 is coupled to the Control Logic to modify the output driving waveforms coupled to the output drivers to permit control of the power applied to the motor windings. The least signi- ficant bit (B0) is sensed by a connection to the Modulo 6 Counter 144 (D1 Q) for further use in connection with power control.

The output waveforms of the Control Logic 145 are the six waveforms AT, AB, BT, BB, CT and CB illustrated at the bottom of Fig. 3. These waveforms, whose sequences are reversed through operation of the Wall Control 105 or the Forward/Reverse Switch S1 on the printed circuit board (Fig. 2), provide for for- ward and reverse rotation of the motor. Similarly, the lined portions of the output waveforms illustrate those periods during which the respective output switches may be subjected to a duty cycle control through operation of the wall control or potentiometer R40 also on the printed circuit board (Fig. 2) for adjustment of the motor speed.

The Control Logic 145 consists of a first rank of 3 input NAND gates 1. 1361141 associ- ated with reverse operation of the motor, a second rank of 3 input NAND gates U42-LI47 associated with forward operation of the motor, a third rank of two input NAND gates U48 to U53 acting to multiplex the forward or reverse sequences to the Output Drivers 146.

The Control Logic is completed by the gates U13 to U16, which respond to the least significant bit and to the pulse width modulation signals in achieving a continuous control of output power.

The logic elements of the Control Logic are connected as follows. The inputs of the Exclusive NOR gate U 13 are coupled to D 16 Q and D 'I Q as previously noted. The output on gate U 13 is coupled through inverter U 14 to one input of the two input NAND gate U 15 and to one input of the two input NAND gate U 16. The other inputs of NAND gates U 15 and U 16 are connected to the pulse width modula- tor 148(1189) The output of NAND gate U 15 is connected to one input of each of the three input NAND gates U37, U39 and U41 in the first rank of NAND gates associated respectively with the AB, BB and CB switching out- put pads of the]C and to U42, U44 and U46 of the second rank of NAND gates associated respectively with the AT, BT and CT switching output pads of the IC. The output of NAND gate U 16 is coupled to one input of the NAND gates U36, U38 and U40 in the first rank of NAND gates associated respectively with the AT, BT, CT switching output pads of the IC, and to one input of the NAND gates U43, U45 and U47 in the second rank of NAND gates associated with the AB, BB, CB switching output pads of the [C.

One input of gate U36 and one input of gate U43 are connected to the U31 output of the Modulo 6 Counter 144. One input of gate U37 and one input of gate U42 are connected to U34 in the Modulo 6 Counter; one input of gate U38 and one input of gate U45 are coupled to the output of gate U35 in the Moduto 6 Counter. One input of gate U39 and one input of gate U44 are connected to gate U32 in the Modulo 6 Counter. One input of the gate U40 and one input of gate U47 are connected to the output of U33 in the Modulo 6 Counter. One input of gate U41 and one input of gate U46 are coupled to the output of NAND gate U30 in the Modulo 6 Counter. Finally, one input of the gates of the first rank U36- L141 are coupled to the Forward/Reverse Logic (U1 11) for reverse operation; and one input of the gates in the second rank U42U47 are coupled to the Forward/Reverse Logic (U '112) for forward operation. The outputs of NAND gates U36 and U42 are connected to the inputs of the two input NAND gate U48. The outputs of NAND gate U37 and U43 are connected to the inputs of NAND gate U49; U38 and U44 outputs to the input of U50; U39, U45 outputs to the inputs of U51; U40, U46 outputs to the input of U52; and the outputs of U41, U47 to the input of U53. The outputs of the NAND gates U48-U53, as will be explained, are coupled to the Output Drivers for eventual connection to the separate output pads P7 (AT), P8 (AB), P 10 (BT), P9 (BB), P 11 (CT), P 12 (C13) respec- 31 It 45 1 GB2177272A 31 tively. As earlier noted, these are the six waveforms illustrated at the bottom of Fig. 3.

The production of the output waveforms listed above may be explained as follows. The Q outputs of the flip-flops D1, D2, D3 forming the memory of the Modulo 6 Counter and illustrated in Fig. 3 establish the timing nd duration of the Waveforms US-0, CS 1, CS2, etc. of the Modulo 6 Counter. Logical combi- nations of these waveforms taken two at a time by the gates U30-LI35 in the Modulo 6 Counter produce waveforms having high portions of double count duration corresponding to the high portions of the output waveforms, At the separate stages of the three stage motor, this means that in the middle of the energization period for one stage (e.g., A), a second stage (e.g., B) is being de-energized while a third stage (e.g., C) is being energized so that two stages are being energized at all times.

The logical combination of the CS1, CS2 states, which appears at the output of gate U31 is coupled for forward operation of Switch A to one input of gate U43, the output of which is coupled via gate U49, in forming the AB drive waveform, and via output driver BOBA to the Pad P8. For reverse operation of the Switch A, the output of gate U31 is coupled to one input of gate U36, whose output is coupled via gate U48, in forming the AT drive waveform,and via output driver TOBA to the Pad P7. The logical combinat!on of the CS2, CS3 states, which appears at the

output of gate U32 is coupled for forward operation of Switch B to one input of gate U44, the output of which is coupled via gate U50, in forming the BT drive waveform, and via output driver TOBB to the Pad P10. For reverse operation of the Switch B, the output of gate U32 is coupled to one input of gate U39, whose output is coupled via gate U5 1, in forming the BB drive waveform, and via output driver BOBB to the Pad P9.

The logical combination of the CS3, CS4 states, which appears at the output of gate U33 is coupled for forward operation of Switch C to one input of gate U47, the output of which is coupled via gate U53, in forming the CB drive waveform, and via output driver BOBC to the Pad P12. For reverse operation of the Switch C, the output of gate U33 is coupled to one input of gate U40, whose output is coupled via gate U52, in forming the CT drive waveform, and via output driver TOBC to the Pad P '11.

The logical combination of the CS4, CS5 states, which appears at the output of gate U34 is coupled for forward operation of Switch A to one input of gate U42, the output of which is coupled via gate U48, in forming the AT drive waveform, and via output driver TOBA to the Pad P7. For reverse oper- ation of the Switch A, the output of gate U34 is coupled to one input of gate U37, whose output is coupled via gate U49, in forming the AB drive waveform, and via output driver BOBA to the Pad P8.

The logical combination of the CS5, CSO states, which appears at the output of gate U35 is coupled for forward operation of Switch B to one input of gate U45, the output of which is coupled via gate U51, in forming the BB drive waveform, and via output driver BOBB to the Pad P9. For reverse operation of the Switch C, the output of gate U35 is coupled to one input of gate U38, whose output is coupled via gate U50, in forming the BT drive waveform, and via output driver TOBB to the Pad P10.

The logical combination of the CSO, CS1, states, which appears at the output of gate U30 is coupled for forward operation of Switch C to one input of gate U46, the output of which is coupled via gate U52, in forming the CT drive waveform, and via output driver TOBC to the Pad P '11. For reverse operation of the Switch C, the output of gate U30 is coupled to one input of gate U41, whose output is coupled via gate U53, in forming the CB drive waveform, and via output driver BOBC to the Pad P 12.

As already noted, forward rotation of the motor is provided when the Forward waveform is high and the Reverse waveform is low. Since the Forward waveform is high in the lefthand portion of Fig. 3', the waveforms of the counter states (CSO, W1, CS2, etc.) and the output switching waveforms (AT, AB, BT, etc.) to the left of the center of the figure illustrate forward operation. To the right of the center of the figure, the Forward waveform goes low and the Reverse waveform goes high. Accordingly, the waveforms of the counter states and output switching waveforms are reversed in sequence. Forward operation is provided by means of the gates U42-U47. Forward operation is enabled with a high due to the Forward waveform coupled to one input of each of the gates U42-1- 147. When all three inputs of U42-U47 are high, at selected times in forward operation, the outputs of selected pairs of these gates go low, and assist in forming the forward sequence of the output waveforms. During forward operation, all of the gates U36-U41 are quiescent due to a low of the reverse waveform on each of these gates.

Similarly, reverse operation is provided by means of the gates U36-U41. Reverse operation is enabled with a high due to the Reverse waveform coupled to one input of each of the gates U36-U41. When all three inputs of the gates U36-LI41 are high at selected times in reverse operation, the output of selected pairs of these gates go low, and assist in forming the reverse sequence of the output waveforms. During reverse operation, all of the gates U42-1147 are quiescent due to a 32 GB2177272A 32 low from the forward waveform on each of these gates. The two input NAND gates U48-1.153 are enabled for either forward or reverse operation and couple an input to the output drivers from either the active forward or the active reverse gates.

The output switching waveforms AT, AB, BT, etc. will be virtually as shown in Fig. 3 by the solid line high portions in a setting of the manual speed controls R40 and 105 (see Fig. 2) in which a maximum of power is applied to the motor windings. The amount of power that is applied is variable from a lower limit of no power to an upper limit of full power. Full power operation occurs when the two serially connected winding stages are energized 100% of the time. Duty cycling operation in the individual switching waveforms occurs in those regions defined by a solid line high in the output waveform and a dotted line low. For instance, the forward AT output switching waveform, has a high coincidental with the CS4 low and the CS5 low. The AT waveform has a dotted low for one Reset 1 pulse (equal to the width of the Reset (1) pulse) at the beginning of the CS4 low or a dotted low delayed one Reset (1) pulse at the beginning of the CS5 low, and continuing to the end of the CS5 low. These two periods, as will be shown, are periods during which a 20KHz waveform is subjected to pulse width modulation, which in one limit is not applied at all for a zero duty cycle and in ihe other limit loses the periodic component and becomes continu- ous for the 100% duty cycle. In the customary intermediate values of duty cycle, a square wave is produced having a 20KHz repetition rate, and some ON and some OFF time.

The production of the dotted line---lows-in the output switching waveforms, during which 105 duty cycled operation occurs, involves the gates U 13, U 14, U 15 and U 16. The waveform BO (the least significant bit) from the memory D1 of the Modulo 6 Counter, is---ex- clusive NORedwith the Reset 1 pulse from 110 the Flip-Flop (D16Q) of the Comparator. The Reset 1 waveform (referring to Fig. 8), cornmences at the commutation instant, and has a duration of about 1/3 of one commutation period in the fastest motor speed setting. In 115 the slowest motor speed setting, the Reset 1 pulse has a duration of about 1/30th of one commutation period. The -exclusive- NORing of the two waveforms produces a high when both waveforms are low and a low when both 120 waveforms are high, and produces a wave form at the output of gate U 13 which is a delayed inversion of the BO waveform having the same high and low durations, but delayed by the duration of the Reset 1 pulse as shown in Fig. 3. The output of gate U 13 is then coupled to the input of the gate U 16 and through the inverter U 14 to the input of the gate U15. The duty cycled waveform (PWM) is also supplied to the inputs of the gates 130 U 15 and U 16. The U 13 waveform is NANDed with a PWM output in U16 and the output of U16 is applied to the reverse gates (1.136-1.141). Similarly, the U13 waveform after inversion in U 14 is NANDed with a PWM waveform in gate U 15 and the output of gate U 15 is coupled to the input of forward gates U42U47.

Duty cycled operation occurs in the follow- ing manner when forward motor rotation is taking place. In forward rotation, the Forward waveform is high so that the forward gates U42-U47, which produce an active low output when all inputs are high, are enabled.

Thus, an active low is produced in gates 11421.147 during the ON times (highs) of the duty cycled waveform, occuring during the highs of the respective output waveforms from gates U31-U35 of the Modulo 6 Coun- ter. For example, during forward motor rotation, the gate U42 is active in formation of the AT output switching waveform. The output waveform from the gate U34, which corresponds to the AT waveform is high when C94 and CS5 are low.

If the duty cycle setting is zero, and the output from U 15 stays low, then the AT waveform is low for an initial portion of CS4 equal to the duration of Reset 1. It then be- comes high for a commutation period. The AT waveform (with U15 held low) goes low after CS5 has gone low with a time delay equal to the duration of the Reset 1 pulse. If the duty cycle setting is for 100%, and the output from U15 stays high, then the AT waveform remains high for the duration of CS4 and CS5. If an intermediate setting of duty cycle is involved, then the AT waveform as illustrated in Fig. 3, is partially ON and partially OFF. During the CS4 low switching occurs at the 20KHz rate for a period corresponding to the length of the Reset 1 pulse. The AT waveform then remains high (without duty cycling) for a commutation period, and then returns to duty cycled 20KHz switching for the balance of the CS5 low interval. It should be noted that the start of the second portion of the duty cycled switching begins after a delay equal to Reset 1 from the beginning of the bt? low.

The waveforms to the left of Fig. 3 illustrate forward rotation of the motor and the output switching waveforms illustrating duty cycled operation. The left portion of the drawing is affected by start-up conditions during the low portion of the POR waveform. The 1 start waveform, for this paragraph's discussion, is assumed to be high at all times. After POR (low) is completed, the waveforms assume with their conventional regularity-until the middle of the page is reached. At the middle of the page, a reversal in rotation is indicated, and waveforms corresponding to a reversal are provided for the righthand portion of the figure. For forward rotation, assuming that the BB waveform is first, CT follows, then AB, 1 2 Z 33 GB2177272A 33 then BT, C13, AT, BB, CT, etc. Two waveforms are always on togeLther, and the duty cycling occurs first (after POR) on the (---13---for bottom) ground connected switch (BB). Duty cycling occurs second on the (-T- for top) VDD connected switch (CT). Duty cycling occurs next on the ground connected switch (AB), next on the VDD connected switch (BT), etc. Each successive time, the switch connec- tion alternates between a Vdd and a Vss (ground) connection. In addition, at any instant, two highs exist-but one is duty cycled and one is not duty cycled. While this method of alternation causes a shift in the voltage of the winding neutral, the differential amplifier has very good common mode rejection, and by connecting both ends of the winding stage being measured to the differential inputs of the amplifier, the error produced is negligi- ble.The duty cycled sequence, in addition, is adjusted so that as a winding is de-energized the next winding to be energized has a sense to absorb the turn-off transient. The Reset 1 pulse is therefore selected to have a duration approximately equal to the duration of this transient or slightly longer. The effect is to produce smoother motor operation.

OUTPUT DRIVERS 146 The control IC has at its output 6 separata 95 output buffer amplifiers TOBA, BOBA, TOBB, BOBB, TOBC, AND BOBC coupled to the out put pads P7, P8, P 10, P9, P 11 and P 12 re spectively. The letter assignments having a coded meaning. The first two letters designate 100 whether switched connection is to be made between the winding stages and B+ or ground potential;---TO-for top means connec tion to B+ potential, while -BO- for bottom means connection to ground potential. The third -Bmeans buffer amplifier. The fourth letter, A, B, or C denotes whether connection is made to the A, B, or C winding stage. The output switching waveforms produced by the buffers (in the order already cited) are respec110 tively at the AT, AB, BT, BB, CT and C13.

Here, the initial letter designates the winding stage, and the terminal letter determines whether it is designed for load connection to B+ or to ground potential. The output switch- 115 ing waveforms are those shown as the bot tom 6 waveforms illustrated in Fig. 3. The waveforms with a final -T- indicate that they are to be connected to the base of Q82 in switch A or its counterpart in switches B or C 120 for connection to B+ potential. The wave forms with a final -B- indicate that they are to be connected to the gate of Q91 in switch A or its counterpart in switch B or C for connection to ground potential. The conduc- 125 tion periods that are produced in the top and bottom switches correspond to the highs in the waveforms, with the vertical lines indicat ing duty cycled operation, as earlier explained.

The logical design of the Output Drivers 146 130 is illustrated in Fig. 9. The---Top-buffers are each two stage amplifiers consisting of two successive inverters designed to drive the Top portion (Q82, etc.) of the switches A, B and C. The---Bottorn-buffers, each consist of a two input NAND gate in the first stage followed by an inverter in the second stage designed to drive the Bottom portion (Q91) of the switches A, B and C. The second input of each NAND gate is connected to the POR 150 for application of the 1 start waveform. The effect of an inhibition of the bottom buffers is to prevent the application of power to the motor, since both a top and bottom switch must be conductive for power to flow to the winding stage. As will be explained in connection with the POR 150, upon starting the motor, power is not applied to the windings until the fifth count (CS5) in operation of the Mo- dulo 6 Counter 144.

OSCILLATOR 147 AND PULSE WIDTH MODULA TOR 148 The Oscillator 147 is used for two purposes on the Control IC. In the operation of the Autonull Circuit, the Oscillator output controls the counting rate used to decrement the offset current in nulling the Amplifier 141. The Oscillator 147 and the Pulse Width Modulator 148 together enter into the adjusTment of the speed of the fan motor. The. electronically commutated motor is designed to operate at a speed established by the amount of electrical power supplied to the motor. When more electrical power is supplied, the motor rotates at a higher rate and when less electrical power is supplied, the motor rotates at a lower rate. In the present embodiment, the amount of power supplied to the fan motor is subject to control from approximately 100% to less than 1 % of maximum power. This range of power adjustment produces at least a 200: 10 rpm speed range. The AT, AB, BT, BB, CT, CB waveforms illustrated in Fig. 3 depict the mode of application of duty cycled energization to the motor windings. The creation of these waveforms based on the supply of a pulse width modulated waveform from the Pulse Width Modulator 148 has been described in connection with the Control Logic 145 and the Output Drivers 146. The present discussion deals with the Oscillator 147 and the Pulse Width Modulator 148 in the creation of that waveform, a combination which facilitates the wide range of motor speed adjustment sought herein.

The Oscillator 147 is a relaxation oscillator. The circuit elements of the Oscillator external to the IC are shown in Fig. 2. Those circuit elements on the IC are shown in Fig. 10A. It comprises a capacitor C6, a transistor Q42 for recurrently discharging the capacitor and a resistor R24 for recurrently charging the capacitor. The Oscillator circuit also includes two comparators (COM 4 and COM 5) for setting 34 GB2177272A 34 the limits of the voltage swing of the relaxation oscillator, each comparator being followed by an inverting hysteresis gate, U87, U88, a flip-flop comprised of NAND gates U90, U91, 5 a reference voltage comprising transistors 0.47, C148, G49, resistors R9 and R10, and a protective network including resistor R1 1 and diodes D2 and D3.

The elements of t6e Oscillator are intercon- nected as follows. The capacitor C6, which is external to the integrated circuit, has one terminal connected to pad P15 and the other terminal connected to the system ground. The resistor R24, which is also external to the integrated circuit, is connected between pad P13 to which the source of Vdd voltage is applied and the pad P15. The N-channel transistor C42 has its drain connected to pad P15 and its source connected to IC ground. The drain of transistor Q42 is also connected via 250Q resistor R '11 to the positive input of the comparator COM 4 and to the negative input terminal of comparator COM 5. The negative input terminal of the comparator COM 4 is connected to the voltage reference circuit at a point having a normal potential of 1.8 volts. The positive input terminal of comparator COM 5 is connected to a voltage reference (Vref5) having a potential of 0.75 volts. The output terminal of the comparator COM 4 is connected via the inverting hysteresis gate U87 to one input terminal (5) of the NAND gate U90. The output terminal of the comparator COM 5 is connected via the inverting hysteresis gate U88 to one input terminal (R) of the NAND gate U9 1. The other input of the NAND gate U90 is connected to the output of the NAND gate U9 1, at which the Q output of the Flip-Flop appears. The other input of the NAND gate U91 is connected to the output of the NAND gate U90 at which the Q output of the Flip-Flop appears. The Q output of the Flip-Flop (U90, U91) is connected to the gate of Q42. The output of the oscillator CLK in the form of a rectangular pulse having a short interval duration of approximately 300 nanoseconds and a pulse repetition rate of 20KHz is coupled from the output of U91 to U93 in the Autonull Circuit for timing the counting rate.

The voltage reference and the remainder of the Oscillator circuit components are interconnected as follows. The P-channel transistor G47, of 4/8 geometry, has its source connected to Vdd, its gate connected to IC ground, and its drain connected via 1.6K resistor R9, and 1.6K resistor R10 to the drain of the N-channel transistor Q49, of 50/4 geometry. The gate and drain of Q49 are connected together, and the source of Q49 is connected to IC ground. The 1.8 volt reference coupled to the negative input terminal of COM 4 appears at the drain of Q49. Protective diodes D2 and D3 are serially connected between Vdd and IC ground, their interconnection being connected to the positive input terminal of COM 4 and the negative input terminal of COM 5.

The Oscillator operates as a relaxation oscillator whose amplitude is defined by the limits set by the voltage references at the comparator inputs. Waveforms useful to understanding oscillator operation are provided in Fig. 1013. When first energized, capacitor C6 begins to charge toward Vdd, the voltage on the capaci- tor C6 appearing at the inputs of both cornparators. When the voltage exceeds PWM ---Ref---(+ 1.8 volts), COM 4 sets the Flip-Flop, and the Q output goes high, turning on G42, which discharges the capacitor C6. When the voltage on C6 fails below Vref 5 (+0.75 volts), COM 5 goes high, resetting the FlipFlop, with Q low and turning off Q42. Since the discharge of C6 is extremely fast (for the values of R24, C6 shown), and COM 5 has a finite response time, the voltage on C6 tends to fall all the way to ground. The capacitor C5 then begins to recharge, and the cycle repeats. The output waveform (CLK) appearing at the output of U91 is coupled to U93 of the Autonull circuit. The waveform appearing at the capacitor C6 is the sawtooth waveform in the upper part of Fig. 1013. The CLK waveform is the rectangular pulse superimposed on the sawtooth waveform. The duty cycle, as earlier noted, for the clock waveform is <1%, using the indicated parameters. The selection of the parameters is designed to create a relatively linear sawtooth waveform on the capacitor C5.

The Pulse Width Modulator 148 utilizes the sawtooth capacitor waveform and provides an output waveform (i.e., PWM output), which is selectively either always off; on some off some; or always on. The ratio of on-to-off time (i.e. Pulse Width) is controlled by the setting of the external potentiometer R40 or the wall speed control 105. These three possibilities are described in Fig. 10B.

The Pulse Width Modulator comprises the external potentiometer R40, external transistor Q81, external resistances R25, R26, R27, R29 R30 and external capacitor C4 associated with "Regulate" pad P14 and the comparator COM 6, and hysteresis gate U89 on the IC. The 100K ohm potentiometer R40 has its end ter- minals connected between Vdd (pad P13) and the system and IC ground (pad P6). The tap on the potentiometer R40 is connected via the 150K resistor to the pad P14. The 2.2,uf capacitor C4 and the 39K resistor are connected between the pad P14 and system ground. PNP transistor Q81 has its collector coupled to pad P14, its base connected to the tap on a voltage division network compris- ing 430K resistor R26 connected to the 150 volt supply and 36K resistor R27 connected to system ground, and its emitter connected via 36K resistor R25 to Vdd. The principal collector load is the 39K resistor R30 con- nected between the collector of Q81 and sys- 1 tem ground.

On the IC, the comparator COM 6 has its negative input terminal coupled to the pad P14, and its positive input terminal coupled 5 via the resistance R1 1 to the capacitor C6. The output of the comparator COM 6 is coupled to the inverting hysteresis gate U89 at the output of which the PWIVI output appears.

The limits and an intermediate form of the PWM output wave are illustrated in Fig. 10B. The duty cycle is affected by both potentiometer R40 and the wall control 105. When the potentiometer R40 is set very low, the negative input of the comparator is always below the voltage on the cap _2citor C6, and the COM 6 output is high. The PWM output derived from U99 is always low. When R40 is set very high, the_qm arator output is always low, and the PWIVI output is always high.

When R40 is set at an intermediate position between the limits of the oscillation _yoltage appearing across the capacitor, the PWIVI out put waveform is high part of the time and low part of the time. Since the capacitor voltage is controlled to rise and fall substantially linearly, 90 the practical linear adjustment range of the duty cycle is very close to the 0 to 100% absolute limits.

Fig. 10C, which also applies the Forward/ Reverse Logic, illustrates how the duty cycle is affected by the wall control 105. When the wall control is used, the maximum B+ voltage is limited to about 135V. Downward adjust ment of the motor potentiometer in the wall control reduces the B+ (+ 135V) applied to the motor. Initial downward adjustment of the control brings about a reduction in speed by a reduction in the voltage applied to the motor.

After the voltage has been reduced from a nominal value of 150 volts to approximately volts, further downward adjustment of the wall potentiometer brings about simulta neous downward adjustment of the B+ and the imposition of a pulse format upon the out put waveform, whose duty cycle is gradually decreased. This is illustrated in Fig. 10C. The duty cycle is controllable by this control from 100% to nearly 0% as indicated in relation to the adjustment of R40.

The operation of the wall control 105 involves the components earlier named connected to the Regulate pad P14. These include the transistor Q81 and resistors R25, R26, R27, R29, R30 and R40. Operation of the wall control adjusts the average voltage applied to the motor. The maximum voltage (e.g. 135 volts) produces the maximum speed. Decreasing the average voltage by means of the wall control produces a substantially linear reduction in voltage applied to the motor as indicated by the upper solid line. (When this reduction begins, let us assume that R40 is set at the maximum value.) At the maximum value, Q81 is biased off by an approximately 1.4 volts difference between its emitter vol- GB2177272A 35 tage, which is defined by the Zener diode CR1 at 9 volts above ground, and the base voltage, which is defined at about 10.4 volts by the voltage divider formed by R26 and R27 connected between the 135V B+ terminal and ground. As the B+ potential is adjusted down, the voltage on the emitter connected to the Zener diode remains constant, while the voltage on the base connected to the vol- tage divider fails in proportion to the reduction in B+ potential. At about 11 OV B+, the reverse bias on Q81 is removed, and adequate forward bias provided to overcome the junction drop, and initiate conduction. To this po- int, in the downward adjustment of the potential, the voltage on the Regulate pad P14 has been unaffected, and has remained at zero potential. Beyond this point, conduction by transistor Q81 between Vdd and the Regulate pad causes the voltage on the pad to increase. Any slight increase in voltage raises the threshold of U89, and causes a decrease in the Pulse Width. The joint reduction in absolute B+ voltage and in the duty cycle produces an increased rate of decrease in average voltage. At about 60 volts, a minimum rotation rate gust above the stalling speed of the motor) is achieved and the PWM duty cycle is near zero. For a REG voltage equal to about 2.2 volts, the PWM duty cycle and speed are both zero. At this point any further decrease in voltage provides no further decrease in speed of the motor, but rather a further elevation of the voltage on the Regu- late pad. This last range of adjustment permits the voltage increase on the Regulate pad to signal a reversal in rotation by tripping a comparator set at 2.4 volts, as will be described in connection with the Forward/Reverse Logic 149.

Control of the rate of rotation of the fan motor is achieved by a combination of an initial reduction in the B+ voltage supplied to the fan motor followed by the utilization of a pulse width modulated form of energization in which further reduction of the B+ supply is accompanied by a progressive narrowing of the energizing pulses of fixed repetition rate. As the voltage is further reduced, a minimum point is reached at which there is essentially no---on-time for the pulses and the energizetion is essentially cut off. The practical range of speed adjustment exceeds 200:20 rpms.

To get a 10: 1 speed control range using a variation of B+ supply voltage only would require a 10:1 range of voltage. This is difficult to do and still use a single zener diode power supply to power the IC from the B+ supply. By proportionately reducing pulse width with B+ voltage reduction, a 10:1 speed range can be obtained with only a 2 to 3:1 variation in B+. The B+ supply voltage variation is used in order to control motor speed with the wall control. If a wall control is not used, the full speed range can be obtained using PWM 36 GB2177272A 36 only.

Achieving this range of control requires a system capable of stable operation at both the upper and lower limits of operation. This has been achieved by the avoidance of a pulse by pulse feedback loop for current control, and the use of a higher PWM rate. The present arrangement, which uses an open loop pulse width modulation configuration is particularly advantageous when it is desired to achieve the present wide range of control. Open loop operation is characterized in a block diagram in Fig. 10E. The applicable waveform is the AT waveform of Fig. 1 OF, also illustrated with less detail in Fig. 3.

In the Fig. 10E illustration, the motor speed is set by an energy balance between a mechanical load imposed on the ECM motor 206 primarily by the fan 207 and the electrical en- ergy supplied to the motor and determined by the operator. The block diagram illustrates a manually adjusted potentiometer 203 whose end terminals are connected between Vdd and ground and whose tap is connected to the negative input terminal of comparator 202. The positive input terminal of the comparator 202 is coupled to the output of a source of sawtooth waveforms 201. The comparator 202 output is coupled to Electronic Gating 205. Power is supplied to the Electronic Gating 205 from the dc power source 204. Power is derived from Electronic Gating by three separate connections (A, B, Q to the three winding stages of the ECM 206. The output of the comparator, depending upon the 100 setting of 203 produces an output waveform which is a sustained logical "one", a pulsed logical "'I" having a fixed 20KHz repetition rate whose duration is determined by the set ting of 203 or finally, a sustained logical 105 zero The intermediate case is illustrated in Fig. 10E. The Electronic Gating 205 is primarily the Control Logic 145 whose

function is to provide gating in response to the pulse width modulation which appears at U89 and in response to the output of the Modulo 6 Counter which defines the double commutation periods for energizing the separate winding stages.

The setting of the input of the comparator is determined by the operator when he sets the voltage at 203. This arrangement provides a full range of control and does so with the required stability at both the upper and lower limits. While lacking the drift stability of a closed loop feedback system, the open loop system has the advantage of simplicity, and any slight drift which might occur is not ordinarily objectionable.

The objective of open loop PWM (pulse width modulation) operation is to avoid anomalies due to time delay which occur in closed loop PWM systems. Specifically, in feedback PWIVI systems the system is turned on and then turned off at a later time by 130 some motor related parameter such as current or voltage. There is a minimum pulse width that can be thus generated which corresponds to the total time delay of the system including the turn-off delay of the power transistors. If an attempt is made to generate a PWM pulse which is shorter than the system time delay, the system will either jump to zero from some finite value or it will duty cycle back and forth between zero and this minimum finite value, in a bang-bang way, trying to achieve the -forbidden- setting by averaging over many pulses some of which are too large and the others of which are zero.

The avoidance of these anomalies sets requirements upon the manner of adjusting the variable level and the mode of generation of the periodic waveform, the two being illustrated as the inputs to the comparator 202 of Fig. 10E. Requirements are also placed upon the relationship of one to the other.

In the disclosed embodiment, the user of the fan may look at the fan, determine whether it is going at the desired speed and make an upward or downward adjustment. The adjustment, once made is essentially independent of what happens to the motor and the power circuit, and when the user has moved away from the control and is no longer regulating by hand and by eye, this operation is also open loop.

The control 203 need not be manually adjusted in the manner just described, however. The adjusted level may be part of a power sensing, current sensing, cooling sensing, etc. feedback system in which average levels of slowly varying parameters such as average currents, average temperatures, etc. may be used. It is thus possible to have an open loop modulator used in a closed loop motor system.

The adjustable level in the PWM input must meet two criteria. It should not be instantanously responsive to motor circuit parameters nor have any frequency components comparable to that of the repetitive wave such as would disturb the distance between intercepts used to define the active state of the comparator output and thus the duty cycle of the PWM waveform. Re-phrased, the adjustable wave should not have any components whose rate of change is comparable to the rate of change of the repetitive waveform.

Another requirement is that the repetitive waveform should be independent of the motor in a strict sense in that in both the short term and in the long term there is no relationship between them. In the actual embodiment, the oscillator is powered from the same DC sup- ply as the motor but the supply is controlled by a Zener voltage regulator and DC levels as well as short time current instabilities are precluded from affecting the oscillator frequency, amplitude, or waveform. If these conditions are maintained, then the motor speed is ad- c a 37 GB2177272A 37 4 0 justed throughout essentially all of its range without any unevenness in the motor speed function.

The present arrangement achieves a large range of speed adjustment with quiet operation. The continuous control range is from approximately 0% to 100% duty cycle adjustment corresponding to a rate of rotation of approximately 10 rpms to approximately 200 rpms maximum. At near zero duty cycle, the power switches do not fully turn on and operate in an analog fashion down to 0 duty cycle. The pulse to pulse feedback systems on the other hand are usually restricted to 5% to 95% duty cycle adjustment because of limitations in the delay times of available low cost semiconductor switches and the delay times in the signal logic itself.

Economics normally dictates that the repeti- tion rate of the pulses be in excess of the audible limits (20KHz) but not so significantly above audible limits as to require high cost, high frequency transistor switches. An economically practical limit is approximately 30KHz.

In practical circuits using NPN devices, the sawtooth waveform has a very accurate positive peak and a not too accurate lower peak. This is because the positive peak is associ- ated with the turn on of a device while the negative peak is associated with the turn off of the device. For this reason the 0% modulation is associated with the positive peak which occurs at approximately 2 volts and the 100% modulation is associated with the negative peak which occurs at ground, since smooth modulation to 0% is more critical. The turn-on time always embraces the positive peak, the turn-off time the negative.

THE FORWARDIREVERSE LOGIC 149 The Forward/Reverse or direction control Logic is responsive to the setting of the forward/reverse switch S1 coupled to the pad P 16 on the IC, and to a controlled diminution in the B+ supply, effected by the wall motor speed control. An inversion in the logic state of the output of 149 causes an inversion in the counting sequence and a reversal in the sense of rotation of the motor.

The direction control Logic 149 comprises the transistor Q48, the comparator COM 7, hysteresis gate U1 13, the flip-flops D13, D14, D 15, exclusive OR gates U 107, U 110, and NOR gates U 111 and U 112. External to the IC, the transistor Q81; resistors R25, R26, R27, R29 and R30 (mentioned in connection to PWM 148); and the switch S1 enter into forward/reverse operation.

The comparator COM 7, which is the heart of the control, has its positive input terminal coupled to the---REG-pad P14 and its negative input terminal coupled to an internal reference (Vref 9) at 2.4 volts. The potential at pad P14, while affected by the setting on po- tentiometer R40, will not change the state of COM 7. The state of COM 7 may be changed only by adjustment of control 105, which affects the state of conduction of Q81, as ear- lier described.

The negative input terminal of COM 7 is connected to a voltage reference to which hysteresis is added at the moment that switching takes place. The input connection is made to the drain of the P-channel transistor Q47, which is never less than 1.8 volts irrespective of reductions in B+. The drain of Q47 is connected via serially connected resistances R9, R10 and transistor Q49 (with inter- connected gates and drain) to ground. The PWM reference voltage of 1.8V appearing across Q49 is used as the reference to set the maximum amplitude of the sawtooth waveform. By adding the voltage drops across R9 and R10 to this level (1.8V) and coupling the resulting voltage to the negative input terminal of COM 7, the trip point for COM 7 is set in a manner which assures that reverse always occurs below zero speed. One of the two outputs taken from COM 7 is connected via an inverting hysteresis gate U 113 to the C input of the flip-flop D15. The other output of COM 7 is connected to the gate of N-channel transistor Q48 of 500/4 geometry, whose drain and source are connected to shunt resistance R9. When Q48 becomes conductive as the COM 7 output goes high upon sensing an increase in voltage at P14 in excess of the Vref 9, it reduces the voltage on Vref 9 by approximately one quarter volt. This introduces hysteresis which makes the reversal more positive acting, assuring that only a single reversal occurs every time VREG exceeds Vref 9.

The reduction in B+ is coupled to the for ward/reverse circuit in the following manner.

When the B+ voltage is reduced by wall con trol 105 to a point where Q81 becomes con ductive, the voltage on the Regulate pad P14 monotonically increases as shown in Fig. 10C, (It is assumed that R40 is set at a maximum clockwise position when the wall control 105 is used).

Adjustment of wall control 105 over the normal range of PWM control leads to a final value of 1.8 volts. Adjustment past 1.8 volts produces a voltage peak in excess of 2.4 volts. The comparator COM 7 is set to trip the Forward/Reverse Logic at about 2. 4 volts.

The setting of R40 does not interfere with the reversal achieved by control 105 and will not itself produce a reversal in motor rotation. So long as 081 is nonconductive, the voltage on the Regulate pad P14 is determined by the setting of the potentiometer R40 and resistors R29 and R30. With Q81 nonconductive, the configuration sets a maximum voltage on the Regulate pad P14 of approximately 2.2 volts, when the tap on R40 is at Vdd (and no rever- sal will occur). The 2.2 volts is used to assure 38 GB2177272A 38 that minimum speed is reached even under worst case conditions. The minimum value of zero volts occurs when the tap on R40 is at ground. When transistor Q81 becomes con5 ductive by a suitable fall in B+ voltage with adjustement of 105, the voltage on the Regulate pad P14 will increase toward Vdd as shown in Fig. 10C. The setting of R40, which is isolated by the 150K ohms of R29, has only a slight affect on the Fig. 10C characteristic.

In normal operation, the operator, when it is decided to reverse the fan motor rotation, reduces the manual control to its lowest speed setting, which first reduces the speed to a minimum value (stalling), and then continues past that setting to a value which trips the reversing comparator COM 7. Since the setting is too low for use, the operator returns the setting forward to the desired speed of rotation. In this manner, the speed characteristic illustrated in Fig. 10C is reproduced in the course of either a speed increase or a speed decrease.

The output of U '113 is connected to the C input of flip-flop D15. The R input of D15 is connected to the POR 150 (U120). The (1 output of D 15 is connected to the D input of D 15, and the D 15 Q output is connected to one input of the exclusive OR gate U 107. The other input of the gate 107 is connected to pad P16 for application via single pole, double throw switch S1 to either Vdd or system ground potential. Switch S1 provides the per- manent memory for motor direction, and determines the direction of rotation when power is first applied.

The output of the exclusive OR gate U107 is connected to the D input of flip-flop D13, which together with flip-flop D14, provides at least one clock pulse of delay before a reversal can occur. The Q output of D 13 is connected to the D input of flip-flop D14. The CLK signal is connected to the C inputs of D 13, D 14. The exclusive OR gate U 110 has one input connected to the output of U 107 and one input connected to the Q output of D 14, from which is coupled an input of U 116 (in POR 150). The (1 output of D14 is coupled to an input of U '115 (in POR 150). NOR gate U 111 has one input connected to the output of exclusive OR gate U 110, and one input connected to D 14 Q. NOR gate U 112 has one input connected to the output of exclusive OR gate U 110 and one input coupled to D 14 (5. The output of U '112, at which the Forward waveform appears, is coupled to gate U 12 in the Modulo 6 Counter and after two successive inversions in U 12, U7 is coupled unin- verted to the gates of U42-U47 of the Control Logic. The output of NOR gate U 111, at which the Reverse waveform appears is coupled to the gates L136-1141 in the Control Logic.

The output state of the Forward/Reverse Logic is defined by the state of D 15, which is in turn dependent on the state of COM 7, and on the setting of switch S 1 connected to pad P 16. When the installation is first turned on, D 15 is reset (Q low) by the POR. If P 16 is connected to ground by S 'I (a logical low), then with two lows at the input of U 107, a low is produced at the U 107 output. This produces one low immediately at the input to exclusive OR gate U 110. Meanwhile, after a 1 to 2 clock pulse delay, D 13 Q and D 14 Q have gone low. With two lows at the input to U 110, the U 110 output goes low. This causes U 112 (forward) to go low, and U 111 (reverse) with inputs which are connected to D 13 Q and U 110 (both low), to go high, and reverse operation to occur.

If switch S 'I is set high, D 15 Q being low, then the exclusive OR gate U107 output goes high, and a high is propagated directly and indirectly via D13 Q, D14 Q to exclusive OR gate U 110. The output of gate U 110 goes low after a delay of at least one clock pulse, and NOR gate U '112, with lows at both in- puts, goes high for forward operation.

The delayed operation of at least one pulse is achieved by the insertion of D 13 and D 14 in the signal path in parallel with the U 107 output; and the application of the delayed and undelayed signal to the exclusive OR U 110. The exclusive OR produces no high unless both inputs are different. Thus, it acts to defer the transmission of a high to the output gate U 110 until the delayed and undelayed wave- forms have reached the gate U 110 output. The logical use of the Q and d outputs of the flip-flops allows the delay to occur with both a change to reverse or a change to forward rotation.

The direction control logic 149 produces output signals at U '111 and U '112 for control of the direction (clockwise/counter clockwise; or Forward/Reverse) of motor rotation. The absence of an active output signal from U 111 or U '112 inhibits any input to the winding stages. The active outputs (highs) for U 111 (Reverse) and U1 12 (Forward) never coexist, and an interruption occurs for long enough to protect the solid state switches 122-4 after one active state is terminated, before the other active state starts.

The Forward and Reverse waveforms have been illustrated in the waveforms of Fig. 3 and assume a logical high or low. The con- nections of the output of the Forward/Reverse Logic 149 are made to the Commutation Counter for inverting the count sequence within the counter (U8, U9, U20, U21), as earlier described, and to the Control Logic for selecting the forward (L142-U47) or reverse (U36-U41) -decoders- for achieving the correct switching sequence in the output drivers 146.

POWER ON RESET 150 Z 39 GB2177272A 39 m The Power on Reset or Protection Circuit senses Vdd as it increases after power is first turned on (i.e. "Power On") and holds certain portions of the logic in an initial state (i.e. "Reset") until the appearance of sufficient Vdd voltage gives assurance that the logic is valid. It performs a similar function after power is turned off. When power is turned on, it also dictates the initial operation, which is nulling of the Amplifier 141 before it is 75 used for integration timing.

In addition, the POR 150 precludes the ap plication of power to the motor windings until other portions of the control IC have been properly initialized and are ready to perform the normal control functions. The present POR circuit performs its function with the addition of an external pad, and does not require the provision of an additional capacitor.

The analog and digital portions of the POR Circuit 150 are illustrated in Fig. 11 A. The input voltages to the comparator (COM 8 of the POR), illustrating the operation of the POR in response to increasing Vdd upon turn on, are illustrated in Fig. 11 B. The waveforms de- 90 rived from the POR 150 are shown in Figs. 3, 12A and 12B.

The Power On Reset 150 maintains an initial reset condition by means of the POR wave form responsive to the instantaneous value of the Vdd voltage. The POR waveform becomes inactive when the Vdd voltage exceeds the desired threshold (i.e. 7 volts). The POR wa veform is coupled to the Set inputs of the flip-flops D16, D17 of the Comparator Net work 142; to the Reset inputs of the flip-flops D 1, D2 and D3 (assuring a 000 initial state) in the Commutation Counter; and to the Reset input of D15 of the Forward/Reverse Logic 149, assuring a return to the state (Forward or Reverse) established by the position of S1.

The D 1 7Q output is coupled via U92 to D7, and D7d opens gate U85, disconnecting the Amplifier 141 from capacitor C5. When the Amplifier is reconnected after nulling, a signifi cant (6,A) current (IST) is injected into (R4A-D) of the Integrating Amplifier in a sense to cause a discharge of capacitor C5, via gate U85, below the comparator COM 2 threshold (3 volts). This current, which is in terrupted during each of four subsequent null ings, prevents the Amplifier from "hanging up" in a Vdd saturated state upon turn on, but is not so great as to interrere with the reset of the capacitor C5.

The Vdd sensing portion of the POR Circuit comprises the transistors Q52-Q59, the comparator COM 8 and the non-inverting hys teresis gate U120. The positive terminal of the comparator is connected to a first series circuit comprising diode D1 and N-channel transistors Q58 and Q59. The negative termi nal of the comparator COM 8 is connected to a second series circuit comprising the P-chan nel transistors Q52-Q57.

In the first series circuit, the anode of D1 is connected to the source of Vdd potentials and the cathode is connected to the gate and drain of Nchannel transistor Q58 of 500/4 geometry. The source and body of Q58 are connected together and to the drain of Nchannel transistor G59 of 4/40 geometry. These three connections are interconnected to the positive input terminal of the comparator COM 8. The source of Q59 is connected to the IC ground. The gate of Q59 is connected to the Vdd source. The foregoing connections apply a potential to the positive input terminal of comparator COM 8 which is equal to the instantaneous Vdd voltage less a constant, which is equal to the voltage drop in diode D1 and drop in Q58. This is approximately 1.4 volts.

The negative input terminal of comparator COM 8 is connected to a second series circuit in which the slope is a fixed fraction (K< 1) of the Vdd voltage and which is provided with hysteresis to insure positive operation of the POR. In particular, P- channel transistor 052 of 10/6 geometry has its drain connected to the source of transistor Q54. P-channel transistor Q54 of 100/4 geometry has its drain connected to the source of Q55. P-channel transistor Q55 of 25/4 geometry has its gate and drain joined, and the two electrodes are connected to the source of Q56. P-channel transistor Q56 of 25/4 geometry has its gate and drain joined, and the two electrodes are connected to the source of Q57. P-channel tran- sistor Q57 of 25/4 geometry has its gate and drain connected to IC ground. The P-channel transistor Q53 of 20/6 geometry has its source connected to Vdd. The gate and drain of Q53 are joined and connected to the gate of Q52, to the drain of of Q54 and to the negative input terminal of COM 8. The output terminal of COM 8 is connected to the gate of Q54 for effecting hysteresis.

The output terminal of comparator COM 8 is connected to the input terminal of the noninverting hysteresis gate U120. The POR output waveform is derived from the output of U 120.

Upon energization, the output of comparator COM 8 arrives at a logical "low" value once Vdd is in excess of several volts and so remains until the trip point occurs (at a Vdd of about 7 volts).

As shown in Fig. 1113, the trip point of the comparator COM 8 occurs when the voltages at its positive and negative inputs intersect. At this point, the POR waveform goes to an inactive high. The voltage of this intersection is designed to be at a level which allows the logic in the digital circuitry of the IC to become valid and the analog circuitry, particularly that involved in nulling, to become functional. This voltage is set at approximately 7 volts for an upward change in Vdd and 6.5 volts for a downward change in Vdd as a result of GB2177272A 40 the provision for hysteresis.

The foregoing trip point is determined by two independent variables characterizing the series circuits associated with the positive and negative input terminals, respectively, of the comparator COM 8. The first is the voltage offset provided by the diode D l and Q58 in the first series circuit at the positive input termina[ of the comparator, it being assumed that the slope of the resulting input voltage is unitary as a function of Vdd. The second independent variable is the voltage division ratio of the second series circuit, which is coupled to the negative input terminal of the compara- tor COM 8 and which is assumed to act as a simple resistive voltage divider. The fraction K has a value of 0.8 for an intercept at about 7 volts. These values are approximate and appreciable latitude is to be expected.

Hysteresis is provided by the output connection of the COM 8 to the gate of Q54. If the output of COM 8 is low, Q54 is conductive and, similarly, Q52 in series with it is conductive. Thus, current is provided to the transistors Q55, Q56 and Q57 via both tran- sistors G52 and Q54 in one path and Q53 in the other path. When the output of COM 8 goes high, then G54 and Q52 are disabled to conduct current in parallel with Q53, and the voltage at the negative input to COM 8 fails from 5.53 to 5.41, or 120 millivolts, implying a lower conductance. The change in the Vdd threshold is approximately 1/2 volt and in sures a positive switchover.

The output circuitry of the POR circuit 150 100 responds to both the state of the Vdd as sensed at the comparator COM 8 and to the state of the other circuits on the IC which are caused to go through a preliminary series of simulated commutations by the POR. The out put circuitry of the POR consists of the SR flip-flop U 118, U 119, the NOR gate U86, the three NOR gates U 115, U 116, U 117 and the transistors Q69 and S9. The five commutation count duration of the IST and 1 start POR waveforms is drived from a connection of U 115, U 116 to U25, U29 of the Commutation Counter 144. The connection of U 118, U 119 to U86, and U86 to D7G of the Autonull Cir cuit 193 causes the Ist waveform to be de layed until after the first nulting, and inter rupted for the next four nullings. The circuit is as follows.

The SR flip-flop consists of two, two termi- nal NAND gates U 118 and U 119 with the A 120 input being responsive to the Modulo 6 Coun ter and to the Forward/Reverse Logic, and the S input being responsive to the state of the Vdd (COM 8, U 120). The outputs of the two NOR gates U 115 and U 116 are connected to 125 the input of the two input NOR gate U 117.

One input of the two input NOR gate U '115 is connected to the CS5 output of the Modulo 6 Counter and the other input of U '115 is con nected to the D14 (1 of the Forward/Reverse 130 Logic. One input of the two input terminal NOR gate U l 16 is connected to the Modulo 6 Counter for application of the CS1 waveform. The other input of U '116 is connected to the D14 Q output of the Forward/Reverse Logic. The two outputs of NOR gates U 115 and U1 16 are connected to the two respective inputs of NOR gate U 1 17. The output of U 117 is connected to the R input of the flip-flop.

The set (S) input of the flip-flop at the input of U 119 is connected to the output of hysteresis gate U120.

The NAND gates U 118 and U 119 have cross-coupled outputs, one (d) of which is connected to one input of U86, and to the Output Drivers 146. The Q output of the flipflop appearing at the output of U 11 g-is coupled to the other input of U '118. The G output of the flip-flop appearing at the output of U '118 is connected to the other input of U 119. The (1 of the flip-flop is then connected to one input of the two input NOR gate U86. The other input of U86 is connected to D7 Q in the Autonull Circuit 142 for application of the Null Output waveform. The output of NOR gate U86 is coupled to the gate of N-channel transistor S9 whose source is connected to the resistance R4A-D in the Autonull Circuit. The drain of S9 is connected to the drain of P-channel transistor Q69 whose source is connected to Vdd and whose gate is connected to Vref 8 in the Autonull Circuit.

Conduction of switch S9 allows a 6pA current to flow from current source Q69 to R4A-1). Transistor Q69 is a P-channel transistor of 45/12 geometry, which has its source connected to Vdd and its drain connected to the drain of transistor switch S9. Transistor switch S9, an N-channel device of 45/4 geo- metry, has its source connected to the upper terminal of R4A-D for return to IC ground. The gate of S9 is connected to the output of U86. The gate of Q69 is connected to the voltage reference Vref 8 in the Autonull Cir- cuit, which is adjusted to supply a 6pA (IST) current to the resistance R4A-D in the Autonull Circuit. The current (IST) causes a negative output current of the same annount to occur in the output of the Integrating Amplifier and in- sures the discharge of the capacitor C5, should there be a tendency of the Amplifier 141 to hang up at a positive saturation during this start- up period.

The overall Power On Reset process takes place in the following manner. The waveforms of greatest relevance are those provided in Fig. 1213. The output of the comparator COM 8 is assumed to be low immediately (and active as soon as any other protected circuitry) upon turn-on of the power. The output of U 120 whose input is coupled to COM 8, remains low and the POR waveform is in its active low state holding the Comparator Network 142, the Modulo 6 Counter 144, and the Forward/Reverse Logic 149 in the appro- t Q 41 GB2177272A 41 W qv priate initial states. More particularly, the flipflops D16 and D17 of the Comparator Network 142 are set (Q high) providing a--- falsecommutation signal causing the Reset waveform and the Null Clock waveform to be high. The flip-flops D1, D2, D3 of the Modulo 6 Counter 144 are reset to the 000 state (Qs low) and the flip-flop D15 of the Forward/Reverse Logic 149 are returned to a state corre- sponding to the setting of the forward/reverse switch S1.

A further consequence of a valid low at the output of the comparator COM 8 is that the Output Drivers 146 are disabled immediately after turn-on. This condition assumes that the 8 input of U 119 is low, the flip-flop (U 118, U '119) is---set-(d output low). The (1 low output of the flip-flop applies a low to the bottom output drivers BOBA, BOBB and BOBC in 146, precluding energization of the motor winding stages. These drivers remain disabled so long as the flip-flop (L1 118, U 119) is set.

A further consequence of a low at the output of COM 8 is that a negative offset current IST is supplied to R4A-D in the Autonull Circuit, which is intended to facilitate the Integrating Amplifier's discharge of C5 below the 3 volt threshold of comparator COM 2 when it is connected by Y85 to reset and charge capacitor C5. The Q low output of the threshold of flip-flop (U1 18, U1 19) is also coupled to one input of the NOR gate U86, which has a high due to the Null Output waveform on the other input. The output of U86 is there- fore low, causing transitor switch S9 to remain off until the initial Autonull (and next four) periods are over. The Autonull period is defined to be the interval between the moment when the Null Clock waveform goes high (at power on) and when the Null Output waveform goes low.

During the continuation of the active low of POR waveform, the states indicated above are maintained. In addition, the capacitor C5, which influences the state of the comparators COM 1, COM 2 and COM 3, is normally discharged at the start of energization, and is not likely to significantly charge for the duration of the active low of the POR waveform. During this time the capacitor C5 is disconnected from the amplifier output since U85 is open because the Null Output waveform is high. As soon as Vdd exceeds 4 or 5 volts and the Amplifier is active, itsoutput will swing to the positive saturation limit since the Autonull Circuit is now supplying it maximum positive offset current (IST is off). This will cause Nullset to go low and remain low until after POR goes high and a null is detected.

When the POR waveform goes to an inactive high, the forced sets and resets are removed and the Modulo 6 Counter and Autonull Circuits are free to function in a more conventional repeating manner for the next four periods.

After the initial Autonull period has concluded (Null Out low), S9 turns on supplying current IST to R4A-D. In respect to the Modulo 6 Counter, the CS5 waveform is NOR'd (U 115) with the D 14 (5 output from the Forward/Reverse Logic, which is high in the reverse direction, disabling U 115. The CS 1 waveform is NOR'd (U 116) with the D 14 Q output. If the Forward/Reverse Logic is operating in a forward sense, then D14 Q is high, disabling U116. If the Forward/Reverse Logic is operating in a reverse sense, then D14 6 is high, U 1 15 is disabled and U 116 is enabled. Initially, CM is active and - CS75-- goes high. This is true for five counts, until CS5 goes low. When CS5 goes low, the output of Ul 15 goes high, forcing the output of Ul 17 low, resetting the flip-flop U 118, U 119, turning off the current IST.

The addition of IST assures that the amplifier offset current remains negative during the time before Vdd has stabilized. The similar POR output waveform I start, which lasts for a five commutation count duration, but is not interrupted during nulling, is coupled to prevent the application of power to the motor until five commutations have occurred.

The protection circuit gives the Autonull circuit five counts to stabilize, qnd insures ade- quate (negative) integration cprrent to discharge the timing capacitor C5 should the Amplifier drift toward saturation in this interval.

The protection circuit acts on behalf of the control circuit, and the power switches and, as earlier noted, operates both during power up and power down.

Upon turn on (POR active) the Amplifier 141 is disconnected from the integrating capacitor C5, due to the high on D7 d. Nulling of the Amplifier is initiated when the POR goes to an inactive state. After nulling, the Amplifier is connected for the first time to C5. The circuit thus insures that nulling will occur as the POR goes inactive and that the Amplifier will not be allowed to affect the timing until it is nulled.

The invention has been used primarily with available neutral connections from the winding stages of the motor. The available neutral connection is not mandatory, however, and a synthetic neutral may be used instead. In general, the requirements of the synthetic neutral are that switching take place in accordance with winding stage energization sequences, and that a resistance or reactance matrix be substituted for the actual windings. The synthetic neutral should not degrade the system and must respond at the same level of accu- racy as other elements of the system.

The motor control circuit herein described in utilizing a periodically balanced transconductance amplifier responding to the back emf of an unenergized winding stage for commutation timing of an ECIVI need not be restricted to 42 GB2177272A 42 the illustrative example. The invention need not be restricted to variable speed designs nor to the lower speed ranges characteristic of ceiling fan operation. The nulling can be accomplished at higher clocking rates within shorter times to fulfill rpm requirements.

The transconductance amplifier with intensive distributed degeneration and self-balancing, is well suited to a maximally integrated motor control circuit, in that it places a minimum requirement upon external components and upon external precision resistors, and has an extremely low power dissipation. The power dissipation on the IC is typically 18 milliwatts and on the control circuit is typically from 0.3 to 1 watt. The resulting motor control circuit thus represents a significant improvement in performance over non-integrated prior art electronic commutation circuits and does so with a significant decrease in cost.

Claims

1. In a motor control circuit for an electronically commutated reversible motor adapted to be energized from a power source, said motor having a multistage winding assembly, and a magnetic assembly, the two arranged for mutual relative rotation, said motor in a given state of a multistate energization sequence having an unenergized winding stage in which an induced back emf is integrated over time to determine the instant at which the mutual relative angular position has been attained suitable for commutation to the next state of sequence, and wherein in said given state at least one other winding stage is energized in the appropriate sense to cause relative rotation, the combination comprising power input terminals for connection to a power supply suitable for motor operation; first adjustable voltage reduction means for serially connecting a motor via said input terminals to the power supply to provide a variable output voltage suitable for variable speed or torque operation; means for producing a substantially smooth control voltage dependent on said variable output voltage, said control voltage, upon passing through an intermediate value corresponding to a useful limit of said adjustable means, continuing monotonically toward a final value, and means responsive to a value of said control voltage between said intermediate and final corresponds approximately to motor stalling, said change in direction occurring toward minimum output voltage.

4. The combination set forth in claim 3 wherein means are provided to interrupt energization of said motor for a short time when the direction of rotation is changed.

5. In a motor control circuit for an electronically commutated reversible motor adapted to be energized from a power source, said motor having a multistage winding assembly, and a magnetic assembly, the two arranged for mutual relative rotation, said mo- tor in a given state of a multistate energization sequence having an unenergized winding stage in which an induced back emf is integrated over time to determine the instant at which the mutual relative angular position has been attained suitable for commutation to the next state of the sequence, and wherein in said given state at least one other winding stage is energized in the appropriate sense to cause relative rotation, the combination comprising 90 power input terminals for connection to a power supply suitable for motor operation; first adjustable voltage reduction means for serially connecting a motor via said input terminals to the power supply to provide a vari- able output voltage suitable for variable speed or torque operation; means for producing a substantially smooth control voltage dependent on said variable output voltage, said control voltage, upon passing through an intermediate value corre- sponding to a minimum useful setting of said adjustable means, continuing monotonically toward a final value, and control logic means comprising 105 energy control means responsive to said control voltage for adjustment of the rate at which electrical energy is supplied from the supply to the motor for determining motor speed or torque, and 110 motor direction control means responsive to a value of said control voltage between said intermediate and final values to generate a signal for changing motor direction. 6. In a motor control circuit for an elec- tronically commutated reversible motor adapted to be energized from a power source, said motor having a multistage winding assembly, and a magnetic assembly, the two arranged for mutual relative rotation, said mo- values for generating a signal for changing the 120 tor in a given state of a multistate energization direction of motor rotation.

2. The combination set forth in claim 1 wherein said intermediate value of control voltage corresponds to the desired minimum motor speed or torque, said change in direction oc curring toward minimum output voltage.

3. The combination set forth in claim 1 wherein said intermediate value of control voltage 130 W sequence having an unenergized winding stage in which an induced back emf is integrated over time to determine the instant at which the mutual relative angular position has been attained suitable for commutation to the next state of the sequence, and wherein in said given state at least one other winding stage is energized in the appropriate sense to cause relative rotation, the combination comprising power input terminals for connection to a a 45 v 43 GB2177272A 43 power supply suitable for motor operation; first adjustable voltage reduction means for serially connecting a motor via said input terminals to the power supply to provide a vari- able output voltage suitable for variable speed or torque operation; means for producing a substantially smooth control voltage dependent on said variable output voltage, said control voltage, upon passing through an intermediate value, continuing toward a final value, and control logic means comprising a pulse width modulator responsive to said control voltage for adjustment of the rate at which electrical energy is supplied from the supply to the motor for determining motor speed or torque, and motor direction control means responsive to a value of said control voltage between said intermediate and final values to generate a control signal for changing motor direction.

7. The combination set forth in claim 6 wherein said pulse width modulator produces output pulses of constant repetition rate, said repetition rate being high in relation to the commutation rate, said electrical energy being supplied to the motor during the active on time of said pulses.

8. The combination set forth in claim 7 wherein a portion of said control circuit is energized by said output voltage and requires a predetermined value for proper operation, and wherein said pulse width modulator produces a reduction in active on time of said pulses adequate to produce a minimum desired motor speed or torque before said output voltage falls below said predetermined value.

9. The combination set forth in claim 7 wherein a portion of said control circuit is energized by said output voltage and requires a predet- ermined value for proper operation, and 110 wherein said pulse width modulator produces a reduction in active on time of said pulses substantially adequate to produce motor stalling before said output voltage falls below said predetermined value.

10. In a motor control circuit for an electronically commutated reversible motor adapted to be energized from a power source, said motor having a multistage winding assembly, and a magnetic assembly, the two arranged for mutual relative rotation, said motor in a given state of a multistate energization sequence having an unenergized winding stage in which an induced back emf is integrated over time to determine the instant at which the mutual relative angular position has been attained suitable for commutation to the next state of the sequence, and wherein in said given state at least one other winding stage is energized in the appropriate sense to cause relative rotation, the combination comprising power input terminals for connection to a power supply suitable for motor operation; first adjustable voltage reduction means for serially connecting a motor, and a portion of said control circuit connected in parallel with said motor, via said input terminals to the power supply to provide a variable output voltage suitable for variable speed or torque operation of the motor, the minimum output voltage being adequate for control circuit energization, means for producing a substantially smooth control voltage dependent on said variable output voltage, said control voltage, upon passing through an intermediate value corresponding to a minimum useful setting of said adjustable means, continuing monotonically to- ward a final value, and control logic means comprising energy control means, including a pulse width modulator responsive to said control voltage for producing output pulses of con- stant repetition rate, said repetition rate being high in relation to the commutation rate, the energy being supplied to the motor during the active on time of said pulses, being reduced at said intermediate value of said control vol- tage to produce the minimum desired motor speed and torque, and motor direction control means responsive to a value of said control voltage between said intermediate and final values 'to generate a control signal for changing motor direction.

11. The combination set forth in claim 10 wherein said pulse width modulator comprises a waveform generator for supplying a repetitive low voltage waveform of substantially constant repetition rate, amplitude and configuration, said characteristics being substantially free of dependence on said motor, said waveform having a first slope of a first duration and a second slope of a second duration and of opposite sense to said first slope, and a repetition rate which is high in relation to the commutation rate; and a modulating comparator having a first input to which said repetitive voltage waveform is supplied and a second input to which said adjustable control voltage is supplied, to produce output pulses when intersections occur between said inputs, said output pulses occurring at said constant repetition rate, and hav- ing an---active-on time equal to the interval between alternate pairs of intersections. 12. The combination set forth in claim 11 wherein said motor direction control means comprises 125 a reversing comparator having a first input to which said adjustable control voltage is supplied, and a second input to which a voltage reference is supplied having a value between said intermediate and final values, said reversing comparator in response to equality 44 GB2177272A 44 between inputs, generating a signal for a change in the direction of motor rotation.

13. In a motor control circuit for an elec tronically commutated reversible motor adapted to be energized form a power source, 70 said motor having a multistage winding as sembly, and a magnetic assembly, the two arranged for mutual relative rotation, said mo tor in a given state of a multistate energization sequence having an unenergized winding stage 75 in which an induced back emf is integrated over time to determine the instant at which the mutual relative angular position has been attained suitable for commutation to the next state of the sequence, and wherein in said given state at least one other winding stage is energized in the appropriate sense to cause relative rotation, the combination comprising:

power input terminals for connection to a power supply suitable for motor operation; first adjustable voltage reduction means for serially connecting a motor, and a portion of said control circuit connected in parallel with said motor, via said input terminals to the power supply to provide a variable output vol- 90 tage suitable for variable speed or torque operation of the motor, the minimum output voltage being adequate for control circuit energization; means for producing a substantially smooth 95 control voltage dependent on said variable output voltage, said control voltage upon passing through an intermediate value, contin uing toward a final value, and control logic means comprising energy control means, including a pulse width modulator responsive to said control voltage for producing output pulses of con stant repetition rate, said repetition rate being high in relation to the commutation rate, the energy being supplied to the motor during the active on time of said pulses, being reduced at said intermediate value of said control voltage to produce the minimum desired motor speed and torque, and motor direction control means having a first input coupled to a reversing comparator for response to a value of said control voltage between said intermediate and final values for generating a signal for changing the direction of motor rotation, and a second input coupled to a switch for generating a signal for controlling the direction of motor rotation.

14. The combination set forth in claim 5 or 13 wherein means are provided to interrupt energization of said motor for a short time when the direction of rotation is changed.

15. The combination set forth in claim 12 or 13 wherein solid state switching means are provided for serially connecting said winding stages via said input terminals to the power supply, said switching means conducting to energize said winding stages in one energization sequence, and wherein means are provided to interrupt conduction of said switches for a short period adequate to turn off said switch(es), when the direction of motor rotation is changed, before energization of said winding stages in another energization sequence.

16. The combination set forth in claim 15 wherein said conduction interruption period is derived from said waveform generator, and exceeds one period of said repetitive low voltage waveform.

17. The combination set forth in claim 15 wherein said motor direction control means has a dual output one output having an active state for facilitating clockwise motor rotation, and a second output having an active state for facilitating counterclockwise motor rotation, the two active outputs states never occurring simultaneously and wherein said means for interrupting conduction of said switch, produces said interruption by maintaining both output states inactive for the interruption period.

18. The combination set forth in claim 17 wherein second voltage reduction means is provided, coupling the portion of said control circuit in parallel with said motor via said input terminals to the supply, and establishing low voltage dc supply for said control circuit portion, the voltage of said low voltage dc supply changing at a finite rate when power is applied or removed; and a protection circuit producing an output responsive to the voltage of said low voltage dc supply and when said voltage has exceeded a first value as power is turned on, releasing said motor direction control means in an output state determined by the setting of said switch, said first value being set such that normal circuit operation is assured at low vol- tage supply voltages exceeding said value.

19. The method of controlling an electronically commutated reversible motor energized from a power source, said motor having a multistage winding assembly, and a magnetic assembly, the two arranged for mutual-relative rotation, said motor in a given state of a multistate energization sequence having an unenergized winding stage in which an induced back emf is integrated over time to determine the instant at which the mutual relative angular position has been attained suitable for commutation to the next state of the sequence, and wherein in said given state at least one other winding stage is energized in the appro- priate sense to cause relative rotation, comprising reducing the output voltage supplied to the motor through a range of values suitable for variable speed or torque operation, producing a substantially smooth control GB2177272A 45 4 45 voltage dependent on said variable output vol- tage, said control voltage, upon passing through an intermediate value corresponding to a minimum useful reduction, continuing mo- notonically toward a final value, and generating a signal for changing the direction of motor rotation at a value of the control voltage between said intermediate and final values.

20. The method of controlling an electroni- 75 cally commutated reversible motor energized from a power source, said motor having a multistage winding assembly, and a magnetic assembly, the two arranged for mutual relative rotation, said motor in a given state of a mul- 80 tistate energization sequence having an unen ergized winding stage in which an induced back errif is integrated over time to determine the instant at which the mutual relative angular position has been attained suitable for com- 85 mutation to the next state of the sequence, and wherein in said given state at least one other winding stage is energized in the appro priate sense to cause relative rotation, corn prising reducing the output voltage supplied to the motor through a range of values suitable for variable speed or torque operation, by means of a first adjustable voltage reduction means serially connecting the motor to a power sup- 95 ply producing a substantially smooth control voltage dependent on said variable output vol tage, said control voltage, upon passing through an intermediate value corresponding 100 to a minimum useful setting of said adjustable means, continuing monotonically toward a final value, and generating a signal for changing the direc tion of motor rotation at a value of the control 105 voltage between said intermediate and final values.

21. The method of controlling an electroni cally commutated reversible motor energized from a power source, said motor having a multistage winding assembly, and a magnetic assembly, the two arranged for mutual relative rotation, said motor in a given state of a mul tistate energization sequence having an unen ergized winding stage in which an induced back errif is integrated over time to determine the instant at which the mutual relative angular position has been attained suitable for com mutation to the next state of the sequence, and wherein in said given state at least one other winding stage is energized in the appro priate sense to cause relative rotation, corn prising reducing the output voltage supplied to the motor through a range of values suitable for variable speed or torque operation by means of a first adjustable voltage reduction means serially connecting the motor to a power sup ply producing a substantially smooth control voltage dependent on said variable output voltage, said control voltage, upon passing through an intermediate value, continuing monotonically toward a final value, 70 enhancing the rate of downward adjustment in energy per unit change in output voltage supplied to the motor and thereby reducing said range of values by means of a pulse width modulator for producing output pulses of high repetition rate in relation to the commutation rate whose on time, during which energy is supplied to said motor, is responsive to said control voltage, said intermediate values corresponding to a minimum useful setting of said adjustable means, and generating a signal for changing the direction of motor rotation at a value of the control voltage between said intermediate and final values. 22. The method of controlling an electronically commutated reversible motor energized from a power source, said motor having a multistage winding assembly, and a magnetic assembly, the two arranged for mutual relative rotation, said motor in a given state of a multistate energization sequence having an unenergized winding stage in which an induced back errif is integrated over time to determine the instant at which the mutual relative angular position has been attained suitable for commutation to the next state of the sequence, and wherein in said given state at least one other winding stage is energized in the appropriate sense to cause relative rotation, cornprising reducing the output voltage supplied to the motor through a range of values suitable for variable speed or torque operation by means of a first adjustable voltage reduction means serially connecting the motor to a power supply producing a substantially smooth control voltage dependent on said variable output voltage, said control voltage, upon passing through an intermediate value, continuing monotonically toward a final value, enhancing the rate of downward adjustment in energy per unit voltage supplied to the motor and thereby reducing said range of values by means of a pulse width modulator for producing output pulses at high repetition rate in relation to the commutation rate whose on time, during which energy is supplied to said motor, is responsive to said control voltage, said intermediate values corresponding to a minimum useful setting of said adjustable means, generating a signal for suspending the energization for motor rotation in one sense at a value of the control voltage between said intermediate and final values, and after a short interruption for protection of motor switches, generating a signal for motor rotation in an opposite sense.

46 GB2177272A 46 Printed in the United Kingdom for Her Majesty's Stationery Office, Dd 8818935, 1987, 4235. Published at The Patent Office, 25 Southampton Buildings, London, WC2A 'I AY, from which copies may be obtained.

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