GB2173617A

GB2173617A - Apparatus for locating and indicating the position of an end }1} bit of a number in a multi-bit number format

Info

Publication number: GB2173617A
Application number: GB08506948A
Authority: GB
Inventors: Richard David Simpson; Michael David Asal
Original assignee: Texas Instruments Ltd
Current assignee: Texas Instruments Ltd
Priority date: 1985-03-18
Filing date: 1985-03-18
Publication date: 1986-10-15
Also published as: GB2173617B; GB8506948D0; JPS61267823A; JPH0799494B2; US4849920A

Description

1 GB 2 173 617 A 1

SPECIFICATION

Apparatus for locating and indicating the position of an end -1- bit of a number in a multi-bit number 5 format This invention relates to apparatus for locating and indicating the position of an end '1---bit of a number in a muffi-bit number format and is of particular use in providing an indication of the placing of the most significant bit of a multi-bit number e.g. priorto effecting floating point arithmetic operations using the number. In other applications the placing of the least significant '1 " bit may need to be known.

In floating point notation a binary numbertakes the form of a mantissa having a value between 1 and 2 and an exponent indicating the power of 2 by which the mantissa is to be multiplied to equal the number represented. Although the use of floating point notation requires the arithmetic circuits of the computer to be complicated by the need to perform operations on both the mantissa and the exponent, it does enable the circuits to handle a much wider range of numbers than they could using fixed point notation. To convert a binary number to floating point notation requires locating the most significant '1 " bit of the number, shifting it left or right so that the most significant bit is just to the left of the point and noting the number of places of the shift as the exponent, positive if the shift was to the right and negative if it was to the left. It is clearly desirable to perform the conversion to floating point notation as quickly as possible, and to assist in this an apparatus able to locate the most significant---V'digit and produce an indication of the location rapidly would be useful.

If such apparatus is to be constructed as an integrated circuit or part of such a circuit for use with other units formed using MOS transistor logic, it would be desirable for the apparatus to use the same 105 logic system, both to simplify manufacture and to ensure its compatibility with the other units.

It is an object of the present invention to provide such apparatus which is able to perform its function rapidly and which is suitable for construction as all or part of an integrated circuit. According to the present invention there is provided apparatus for locating and indicating the position of an end "1" bit of a number in a multi-bit number format including input terminals for respectively receiving representations of the bits of an input number, a series chain of MOS transistor logic elements equal in numberto the bits of the numberformat and having their gates respectively connected to the inputterminals, the logic elements and the representations being such that a logic element is closed by the application of the representation of a '1---bit to its gate. Means for setting the inputs and outputs of the logic elements to a first reference potential, means for applying a second reference potential to an end of the series chain, so that a change from the first to the second reference potential is propagated along the chain until it reaches a logic element which is closed because the representation of a '1 " bit is applied to it, and logic circuits responsive respectively to the representations applied to the input terminals and to the signals at the outputs of the logic elements to which they are applied to produce an indiction where the end "1 " bit of the input number occurs.

The apparatus may further include a binary coded logic array responsive to the output indications of the logic circuits to produce binary output signals representing the position of the end "1 " bit of the input number.

The apparatus may be divided into several units each responsive to a group of bits forming part of an input numberto produce an indication of the position of an end "1" bit in the group, the units being coupled together so thatthe generation of an indication by a unit is inhibited if an indication is generated by a preceding unit.

In orderthat the invention may be fully understood and readily carried into effect it will now be described with reference to an embodiment shown in the single figure of the accompanying drawing.

The embodiment of the invention shown in the figure consists of four units Ul, U2, U3 and U4, of which onlythe unit Ul is shown in detail because the otherthree units are each identical in construction to the unit Ul, with the exception thatthey receive as inputs different groups of 8 bits of the number and use different logic arrays LA. The embodiment operates with a number having 32 bit positions, B31, 1330, B29. B2, Bl, BO in descending order of significance, and is arranged to locate the leftmost, or most significant, ---1 " bit in the number. Each of the units Ul, U2, U3 and U4 has inputs for 8 consecutive bit positions, the unit Ul having inputs for B31, B30. B25, B24, as shown, the unit U2 having inputs for B23, B22. B17, Bl 6, the unit U3 having inputs for Bl 5, B14. B9, B8, and the unit U4 having inputs for B7, 136------Bl, BO. The different logic arrays LA use combinations of logic elements representing binary numbers in ascending order from leftto right as described below.

The embodiment uses dynamic MOS transistor charge transfer logic.

In the unit Ul each of the inputs B31, B30------B25, B24 is connected to an input of a respective one of eight NOR gates G1, G2. G7, G8, and also to the gate of a respective one of eight MOS transistors Al, A2_--- A7, A8 having their channels connected in series. The outputs, i.e. the drains, of the transistors Al to A8 are connected to the second inputs of the NOR gates G l to G8 respectively. The channels of eight further MOS transistors Cl, C2,..., C7, C8 are connected respectively from a conductor 1 maintained at a suitable supply potential Vc,: to the drains of the transistors Al to A8. Another MOS transistor C9 has its channel connected from the conductor 1 to the source of the transistor A8. The gates of the transistors Cl to C8 and C9 are connected to a terminal 2 to which a---PRECHARGECLOCK" signal is applied. The drain of the tansistor A1 is also connected to ground through the channel of a transistor D, the gate of which receives an EVALUATE CLOCK signal via terminal 4.

The source of the transistor A8 is also connected through an inverter 3 to the gates of five MOS transistors Fl, F2,..., F5, the channels of which are 2 GB 2 173 617 A 2 connected from five input conductors 11 to 15to five output conductors J 1 to J5 respectively. The conductors J1 to J5 arejoined to outputterminals K1 to K5 and to the outputs L1 to L8 of the NOR gates G 'I to G8 through the binary coded array of logic elements LA (0-7). In the array LA (0-7) the leftmost column, that connected to output Ll, represents 000 and contains no logic elements. The next column is connected to output L2 and represents 001 and therefore has a single logical element, shown as a transistor connected to ground, linking the output L2 to the conductor J1. In the next column the output L3 has an element linking it to conductor J2 representing 010. The output L4 has elements linking it to both J1 and J2 which represents 011, and so on. Finally, output L8 has 3 elements linking it to J1, J2 and J3 representing 111 (=7). It will be appreciated that the array LA (0-7) has 8 columns of logical elements respectively representing 0 to 7 in binary code. The units U2, U3 and U4 have arrays LA (13-15), LA (16-23) and LA (24-31), each with 8 columns of logical elements and respectively representing 8 to 15, 16-23 and 24-31 in binary code. Each logical element consists of a single MOS transistor with its channel, connected from ground to the particular J conductor and its gate connected to the particular L conductor; itwill be appreciated that such a logical element has an inverting effect and serves to ground the J conductor when the L conductor is high.

The conductors J1 to J5 are respectively con- nected through the channels of transistors M1 to M5 to a conductor 5 held at Vcc, the gates of the transistors being connected to a terminal 6 to which the PRECHARGE CLOCK signal is applied.

Because of the inverting effect of the logical 100 elements and the precharging of the conductors J through the transistors M to a high level (VJ the logic levels set up on the conductors J by a high on one of the conductors L is the complement with respect to 31 (= 251) of the binary number represented by the logical elements connected to the particular conductor L. Thus a high on conductor L8 will set up 11000 (=24) on the conductors J and appear at the terminals K.

The conductors joined to the left hand sides of the units U2, U3 and U4 correspond to the conductors J and those joined to the right hand sides of units U2 and U3 correspond to the conductors 1. There is no connection to the conductors atthe right hand side of the unit U4, and, if desired, the inverter 3 and transistors F1 to F5 may be omitted from this unit.

The operation of the apparatus will now be described. The operation of the unit U 1 will be considered first of all, assuming that an 8-bit number is to be applied to the inputs B31,, B24. Initially, the 120 EVALUATE CLOCK signal is low so thatthe transistor D is non-conducting, and the PRECHARGE CLOCK signal goes high for a short period and then falls again, leaving the sources and drains of the transis- tors A1 to A8 and the conductors J 'I to J5 charged to Vcc. This means thatthe outputs of the NOR gates G1 to G8 are all low. The 8-bit number is applied to the inputs, B31,..., B24 in inverted form, i.e. a "1" being low and a "0" being high. The EVALUATE CLOCK signal now goes high causing the transistor D to conduct so that the drain of the transistor A1 is discharged to low. This in turn discharges the drain of the transistor A2 if a high representing "0" is applied to the input B31, and so on. The "low" progresses rightwards along the chain of transistor A1 to A8 until it reaches the drain of a transistor to the gate of which a low representing 1 is applied. Suppose it is the transistor A5. This means thatthe bit applied to the input B27 isthe left most '1 " of the number and is represented by a low signal. The NOR gate G5 therefore has two low inputs and consequently produces a high output. The outputs of all the other NOR gates are low because they each have at least one high input. Because of the inverting effect of the logical elements of the logic array LA (0-7), the single logical element at the crossover of conductors L5 and J3 causes the conductor J3 to be discharged to low, the other conductors J 1, J2, J4 and J5 remaining high. An output of 11011 (=27) is therefore produced at the terminal K indicating that the leftmost---1--- bit was applied to the input B27.

It will be apparent from a consideration of the described embodiment that had the leftmost---1 " been applied to any other of the inputs B31,..., B24 then the corresponding 5-bit binary number would have been produced as output at the terminals K.

Whilst the unit U l is operating as described above, each of the other units U2, U3 and U4 is operating in the same wayto locate the leftmost "1" bit of the group of 8 bits applied to it and to produce a 5-bit binary output on the conductors corresponding to the conductors J of the unit Ul. These outputs are not utilised and do not appear as an output of the apparatus as a whole atthe terminals K, because they are blocked by the transistors F (and possibly also their counterparts in the units U2 and U3) which remain non-conducting as long as the source of the transistor A8 remains high. On the other hand if none of the bits applied to the inputs 1331---- --B24 is a '1% all of the transistors A1 to A8 will be conducting and the low initiated by the EVALUATE CLOCK signal turning on the transistor D will propagate the whole length of the chain of transistors A1 to A8 and the source of the transistor A8 will become low. If this happens none of the outputs of the NOR gates G will become high so that none of the binary codes in the range 31 to 24, is generated and the transistors F will become conducting enabling a binary output received on the conductors 1 from one of the units U2, U3 and U4 to be passed to the output terminals The embodiment described can operate quickly to perform its function, not only because the time required to locate the leftmost '1 " bit is short as a consequence of the high speed of propagation of the low along the chain of transistors A1 to A8 until it reaches a transistor which is non- conducting because of the---1 " bit, but also because the input number is divided into several shorter groups of bits which are examined simultaneously for the leftmost '1- within the groups, so that each low has to propagate along only a short chain of transistors to locate the '1 " bit.

Although the invention has been described with reference to only one embodiment, it will be appa- 3 GB 2 173 617 A 3 rent that many modifications could be made to the embodiment without departing from the invention for example, the apparatus could be extended or restricted to receive numbers having a larger or smaller number of bits; there could be only a single group of bits, the number not being divided up as described above. Where the number is divided into several groups of bits, these need not have 8 bits but could have other convenient numbers of bits; in fact, the groups need not have the same number of bits.

The apparatus could alternatively be arranged to search forthe rightmost---1 " bit, with the low propagating leftwards along the chain of transistors.

The output indicating the location of the '1 " bit need not be in binary code but could be in another code such as a Gray code, and it could be presented in serial instead of parallel form.

The binary '1 " could represent "0" if the logic were inverted, and the apparatus used to detect and indicate the location of zeros in a number in any number system, the two binary digits representing zero and non-zero; the apparatus could therefore be of value in a multiplier.

Claims

1. Apparatus for locating and indicating the position of an end -1- bit of a number in a multi-bit number format including input terminals for respec tively receiving representations of the bits of an input number, a series chain of MOS transistor logic elements equal in number to the bits of the number format and having their gates respectively con nected to the input terminals, the logic elements and the representations being such that a logic element 100 is closed by the application of the representation of a 111 " bit to its gate, means for setting the inputs and outputs of the logic elements to a first reference potential, means for applying a second reference potential to an end of the series chain, so that a change from the first to the second reference potential is propagated along the chain until it reaches a logic element which is closed because the representation of a "ll " bit is applied to it, and logic circuits responsive respectively to the representa tions applied to the input terminals and to the signals at the outputs of the logic elements to which they are applied to produce an indication where the end "11 " bit of the input number occurs.

2. Apparatus according to claim 1 wherein the 115 setting means includes a plurality of MOS transistors having their source-drain paths connected from a conductor maintained at the first reference potential respectively to the junctions between the transistor elements of the series chain and to the start terminal of the series chain, and a connection for applying a precharge clock signal to the gates of the plurality of MOS transistors.

3. Apparatus according to claim 1 or 2 wherein the logic circuits are NOR gates, and first reference potential representing a "1", the second reference potential representing a "0", and the representations of the bits of the input number being inversions of the bits represented, so that the NOR gate at the position corresponding to the end "V bit of the input number produces a "1 " output, and all the other NOR gates produce a---Woutput.

4. Apparatus according to claim 1, 2 or3 including a binary coded logic array having column conductors respectively connected to the outputs of the logic elements and row conductors on which appear binary output signals representing the position of the end "11 " bit of the input number.

5. Apparatus according to claim 4 wherein the binary coded logic array includes an MOS transistor for each intersection of a column conductor and a row conductor where the binary output digit appearing on the particular row conductor of the output signals representing the particular column conduc- tor as the position of the end '1---bit of the input number is a "0", the source-drain path of the MOS transistor being connected from the particular row conductor to the second reference potential and the gate of the MOS transistor being connected to the particular column conductor, means being provided to precharge the row conductors to the first reference potential.

6. Apparatus according to claim 4 or5 having several units respectively responsive to groups of bits forming adjacent parts of the input number, each unit tending to produce binary output signals representing the position of an end---11 " bit in the particular group of bits to which it is responsive, the binary coded logic arrays of the units being coupled together so that the generation of binary output signals by a unit is inhibited if another unit produces binary output signals indicating a '1 " bit in the input number at a positon in a particular direction relative to the first-mentioned unit.

7. Apparatus according to any of claims 1 to 5 having several units respectively responsive to groups of bits forming adjacent parts of the input number, each unit tending to produce an indication of the position of an end "11 " bit in the group, and each unit including means responsive to the potential at the end of the series chain of MOS transistor logic elements remote from that to which the second reference potential is applied to produce an indication that no '1" bits occur in the group of bits applied to it, which indication enables the unit responsive to the next adjacent group of bits to produce an indication either of the position of an end "11 " bit in its group of bits or that its group contains no "1" bit.

8. Apparatus according to any preceding claim arranged to locate and indicate the position of the "11 " bit of greater significance in the input number

9. Apparatus according to any of claims 1 to 7 arranged to locate and indicate the position of the "11 " bit of least significance in the input number.

10. Apparatus for locating and indicating the position of an end "Y' bit of a number in a multi-bit numberformat substantially as described herein with reference to the single figure of the accompany- ing drawing or modified as herein described.

Printed in the UK for HMSO, D8818935,8186,7102. Published by The Patent Office, 25 Southampton Buildings, London, WC2A lAY, from which copies may be obtained.