GB2171221A

GB2171221A - Improvements in integrated circuits

Info

Publication number: GB2171221A
Application number: GB08504241A
Authority: GB
Inventors: Stephen Wilfrid Bland
Original assignee: STC PLC
Current assignee: STC PLC
Priority date: 1985-02-19
Filing date: 1985-02-19
Publication date: 1986-08-20
Also published as: GB8504241D0; GB2171221B

Abstract

A photolithographic mask is formed on a non-planar substrate by coating the substrate sequentially with a thick planarising photoresist layer, a thin dielectric transfer layer and a thin high definition patterned layer. The transfer layer is etched through the openings in the patterned layer and is then itself used as a mask for the planarising layer. The transfer layer has antireflection properties at a wavelength used to form the patterned layer but is transparent at an adjacent wavelength.

Description

SPECIFICATION Improvements in integrated circuits This invention relates to integrated circuits and in particularto photolithographictechniquesforfabricating such circuits.

As integrated circuit minimum feature sizes tend toward the submicron level, photolithographic requirements become increasingly complex. Fine line patterns must be delineated over non-planar surfaces of varying reflectivity. This occurrence of topographical features result in variations in the spin on photoresistthickness and in light scattering effects, while surfaces of high reflectivity lead to standing wave phenomena. These effects lead to varying exposure requirements resulting in serious degradation of linewidth control. Ideally the surface to which a photoresist pattern is to be applied should be optically absorbent. However this conflicts with the requirements that surface layers should be transparent to facilitate alignment in subsequent processing stages.

The object of the present invention is to minimise or to overcome this disadvantage.

According to the invention there is provided a method of forming a photolithographic mask on a non-planar semiconductor wafer, the method including applying to the substrate a first thick photoresist layer the upper surface of which is substantially planar, applying a dielectric transfer layer to the planar surface, applying a thin, photoresist layer to the transfer layer, exposing the thin layer to light to form a high definition pattern on the transfer layer, etching the transfer layer through the patterned layer to transfer the high definition pattern to the transfer layer, and etching the thick layer through the transfer layer to provide the photolithographic mask, wherein the transfer layer is such that it is optically absorbent at a first wavelength at which the patterned layer is formed but is optically transparent at an adjacent wavelength.

An embodiment of the invention will now be described with reference to the accompanying drawings in which Figures 1 to 3 illustrate successive stages in the fabrication of an integrated circuit; Figure 4 illustrates the relationship between the transmittance characteristic and the deposition conditions of silicon nitride films and Figures 5 and 6 illustrate the reflectance characteristic of silicon nitride films.

Referring to the drawings, the circuit is formed on a non-planar substrate the surface portion of which is shown at 11 in Figure 1.The substrate is provided with atrilevel photoresist structure comprising a first thick layer 12, which layer planarises the wafer topography, a thin layer 13 to allow definition of fine linewidth patterns, and a dielectric transfer layer 14 disposed between the layers 12 and 13. Pattern transfer may be performed by a two stage reactive ion etch process. In this process the transfer layer 14 is etched (Figure 2) using the layer 13 as a mask to transfer the high resolution pattern. The etched transfer layer is then used as a high definition mask for anisotropic dry etching of the thick layer 12 (Figure 3). Typically we employ an oxygen etch for this purpose.

Choice of a suitable material for the transfer layer 14 depends on a number of constraints. For high constrast it should not etch in an oxygen plasma. It should also be compatible with low temperature deposition and it should be transparent to facilitate alignment during processing. Suitable materials include, but are not limited to, plasma enhanced silicon nitride. Reactive ion etching of the transfer layer may be effected in a carbon tetrafluoride plasma.

The transfer layer is optically absorbent at the photolith exposure wavelength but is transparent at the alignment wavelength. Thus the need for optical transparency for alignment does not preclude the absorption of radiation by the transfer layer during the exposure process thereby preventing spurious reflection and consequent loss of definition. These optical properties may be imparted to the transfer layer by the deposition process employed. Thus, by control of the plasma enhanced deposition process the optical absorption edge of silicon nitride can be controlled between 1.8 to 5 eV (600 to 240 nm). By suitable choice of the deposition parameters am antireflection layer may be provided.

In general the deposition of the band edge corresponds to the silicon content of the layer. Increasing the silicon content shifts the absorption band edge to longer wavelengths.

The technique may be employed with a variety of semiconductive substrates but it is of particular use in the fabrication of high speed gallium arsenide circuits where the circuit dimensions are relatively small.

The variation of the transfer layer absorption cut off frequency with deposition conditions is illustrated in Figure 4 of the accompanying drawings. Optical transmission spectra are shown for films of differing depositions conditions, these being listed in Table 1 below. The layers were formed by plasma enhanced chemical vapour deposition.

The following example illustrates the invention: Example Tri-level photoresist structures were formed comprising a 1 micron thick lower layer of AZ1 430 photoresist, an intermediate silicon nitride layer, and an upper 0.4 micron thick layer of AZ1350 photoresist.

The lower layer was baked at 200 C for 300 minutes. Two structures were found in which the intermediate layer was of type 1 or type 6 as defined in Table 1 below. The reflectance spectra for these structures were determined, the results being illustrated in Figures Sand 6 respectively of the accompanying drawings. In Figure 5 (type 1 layer) interference effects are displayed from 250nm upwards whereas in Figure 6 (type 6 layer) the low reflectance region extends to 300nm with only a gradual increase up to about 400nm. Thus, in the latter case, exposure wavelengths below 400cm can be employed without the risk of loss of definition.

Tri-level photoresist structures as described above employing a type 6 transfer layer have been used successfully with both UV200 and UV300 exposure systems in the formation of photolithographic patterns.

Such structures have also been found to be sufficiently transparent at e.g. S7Snm to allow alignment to be performed.

TABLE 1 Flow (sccm) Film No. SiH4 NH3 N2 Power Pressure Time Temp PCI ; Iwl (motor) (mien) 1 50 200 200 25 410 3 100 2 100 100 100 25 322 3 100 3 200 100 100 25 391 3 100 4 200 50 50 25 314 3 100 5 5 200 25 25 25 350 3 100 6 200 5 5 25 350 3 100 7 200 0 0 25 350 3 100

Claims

1. A method of forming a photolithographic mask on a non-planar semiconductor wafer, the method including applying to the substrate a first thick photoresist layer the upper surface of which is substantially planar, applying a dielectric transfer layer to the planar surface, applying a thin, photoresist layer to the transfer layer, exposing the thin layer to light to form a high definition pattern on the transfer layer, etching the transfer layer through the patterned layer to transfer the high definition pattern to the transfer layer, and etching the thick layer through the transfer layer to provide the photolithographic mask, wherein the transfer layer is such that it is optically absorbent at a first wavelength at which the patterned layer is formed but is optically transparent at an adjacent wavelength.

2. A method as claimed in claim 1, wherein the transfer layer comprises PECVD silicon nitride.

3. A method as claimed in claim 2, wherein the transfer layer is formed by plasma enhanced chemical vapour deposition.

4. A method as claimed in claim 3, wherein the optical characteristics of the transfer layer is determined by control of the silicon content of said layer.

S. A method as claimed in claim 1,2,3 or 4, wherein the transfer layer is etched by reactive ion etching.

6. A method as claimed in any one of claims 1 to 5, wherein the thick layer is oxygen etched.

7. A method of photolithographic masking of a semiconductor wafer, which method is substantially as described herein with reference to the accompanying drawings.

8. An integrated circuit fabricated via a method as claimed in any one of claims 1 to 7.