GB2164214A - D.C.-D.C. converter circuit - Google Patents

Abstract

A d.c.-d.c. converter circuit comprises a transformer (3) an input winding (17) of which is connected with alternating polarity across a pair of input terminals (1, 2) via a choke (7) by means of a pair of switches (8, 9). In order to control the voltage across a pair of output terminals (4, 5) in spite of the constant-current property of the choke the output terminals are fed from the transformer via a peak rectifier circuit (6) and the switches are controlled by a switching signal generator (12) in such manner that the periods when each is closed overlap the periods when the other is closed by an amount which depends on the value of a control signal at a control signal input (13), the durations of the periods when only one switch is closed being kept equal to one half the period of the resonant frequency of the resonant circuit constituted by the input winding (17) and a capacitor (16). The connection from the choke (7) to the centre-tap (37) of the input winding may be instead to one end (32) of the input winding, provided that another choke connects the relevant input terminal (1) to the other end (33) of the input winding. <IMAGE>

Description

SPECIFICATION D.C.-D.C. Converter Circuit Arrangement This invention relates to a circuit arrangement comprising a pair of d.c. input terminals, a transformer, a pair of output terminals to which a winding of said transformer is coupled, first and second controllable switches which are each connected to form a series combination with a choke and at least part of a winding of said transformer in respective circuits which extend between said input terminals in such a sense that, when a d.c. voltage with a given polarity is applied between said input terminals and a given said switch is caused to conduct, a voltage will be set up across a winding of said transformer with the opposite polarity to that set up thereacross when the other said switch is caused to conduct, and a switching signal generator circuit which has a control input and is constructed to produce switch control signals at first and second outputs thereof, said first and second outputs being coupled to control inputs of said first and second switches respectively and said switch control signals being such as to control said switches to together repeatedly cycle through a succession of switching states consisting of a first state in which the first switch is conductive and the second switch is non-conductive, a second state, a third state in which the first switch is non-conductive and the second switch is conductive, and said second state, in that order, the duration of each said second state being dependent upon the value of a control signal applied to the generator circuit control input. Such an arrangement will be referred to hereinafter as "an arrangement of the kind set forth".

A known arrangement of the kind set forth is discussed in the book "Design of solid-state power supplies" by E. R. Hnatek (2nd edition) pages 466--477, and is in the form of an inverter; an a.c.

voltage appears at the output terminals in response to the application of a d.c. voltage to the input terminals. In this known arrangement the transformer has a primary winding to the two ends of which one of the input terminals is connected via respective ones of the (semiconductor) switches and to a centre-tap on which the other input terminal is connected via the choke and a second winding which is connected to the output terminals and which also has a capacitor connected across it.

The capacitor and the transformer secondary winding inductance together form a resonant circuit which is reflected to the primary side and is hence "seen" by the switches. (The capacitor could equally well be connected across the primary or even omitted altogether if the parasitic capacitance inevitably present has an appropriate value).The first switching states of the switches (first switch conductive and second switch non-conductive) recur, as in consequence do the third switching states (first switch non-conductive and second switch conductive) at a rate substantially equal to the resonant frequency of the resonant circuit seen by the switches and, if it is assumed for the moment that the durations of the aforesaid second switching states are infinitesimally small, this fact in conjunction with the constant-current property of the choke results in the resonant circuit ringing at its natural frequency and a sine-wave appearing at the output terminals (and across the primary winding).

This can be a useful feature as it is likely to result in the generation of much less electromagnetic interference than is liable to be produced by inverters employing square wave voltages.

Because of the presence of the choke, however, it is rather difficult to regulate the output voltage of such an arrangement, at least by the conventional method of adjusting the ratio of the "closed" time to the "open" time of each of the two switches between a minimum of 0:1 and a maximum of 1:1, if this ratio is less than 1:1 both switches will repeatedly be open at the same time (the "second switching state" in the known arrangements, resulting in the generation of very high voltages at the transformer end of the choke each time this occurs. In order to overcome this difficulty an auxiliary winding is provided on the choke in the known arrangement, this winding being connected across the input terminals via a diode which is poled to block the passage through it of current from the input terminals.The connection sense of the auxiliary winding is such that the voltage set up across this winding when current is being supplied to the transformer from the input terminals through the choke increases the reverse bias already present on the diode. However, when both switches are non-conductive this voltage changes sign, the diode in consequence conducts, and the energy stored in the choke is returned to the input supply through it, so that the aforesaid very high voltages no longer occur. Unfortunately, the fact that the supply of current to the transformer is still periodically broken means that spikes occur in the output voltage.

Moreover, very rapid changes still occur in the overall potential of the primary winding. Both of these features are liable to appreciably degrade the otherwise low interference generation properties of the arrangement, and it is an object of the invention to mitigate this disadvantage.

The invention provides a circuit arrangement of the kind set forth in the opening paragraph which is characterized in that the durations of each of said first and third states is substantially equal to one half the period of the resonant frequency of the resonant circuit including said transformer seen by said switches, in that said second state is one in which both the first and the second switches are conductive, and in that a peak rectifier circuit is included in the coupling from the transformer to said pair of output terminals so that said circuit arrangement constitutes a dc-dc converter circuit arrangement.

It has now been recognised that the peak voltage (but not the mean voltage) occurring across a winding of the transformer in a circuit arrangement of the kind set forth can be increased if it is arranged that there is a period when both switches are conductive between each period when only one switch is conductive. Provided that the duration of each period when only one switch is conductive is substantially equal to one half the period of the resonant frequency of the resonant circuit "seen" by the switches, the occurrence of rapid potential changes and voltage spikes in the arrangement can be substantially completely avoided. In general said peak voltage will be larger the longer are the durations of the periods when both switches are conductive.Thus, if the voltage across a winding of the transformer is peak-rectified, i.e. rectified by means of a circuit which does not include significant series inductance, the result will be a d.c. voltage which is controllable by varying said durations. The resulting arrangement can be useful in applications where it is inconvenient to provide a choke in the d.c. output circuit, for example in high-voltage supplies for cathode-ray tubes.

Each switch may be connected to form the corresponding series combination either with the same choke or with a different choke. In the latter case each choke should be coupled to both switches so that a current path between the input terminals exists through it when either switch is conductive.

(Otherwise once again the chokes would be liable to generate high voltages when the corresponding switches are rendered non-conductive).

Embodiments of the invention will now be described, by way of example, with reference to the accompanying diagrammatic drawings in which Fig. 1 is the circuit diagram, largely in blockschematic form, of a first embodiment, Fig. 2 shows some idealised waveforms which illustrate the operation of the embodiment of Fig. 1, Fig. 3 is the circuit diagram, largely in blockschematic form, of a second embodiment, and Fig. 4 shows a possible construction for part of the arrangements of Figs. 1 and 3 in more detail.

In Fig. 1 a d.c.-d.c. converter circuit arrangement comprises a pair of d.c. input terminals 1 and 2, a transformer 3, a pair of d.c. output terminals 4 and 5, a peak rectifier circuit 6, a choke 7, first and second controllable switches 8 and 9 respectively having control inputs 10 and 11 respectively, a switching signal generator circuit 12 having a control input 13 and first and second outputs 14 and 15 respectively, and a capacitor 16 which is connected between the ends 32 and 33 of the primary winding 17 of the transformer 3. The choke 7 connects input terminal 1 to a centre tap 34 on the primary winding 17 and, when conductive, the switches 8 and 9 connect input terminal 2 to the ends 32 and 33 respectively of the primary winding 17. The peak rectifier circuit 6 is included in a coupling from a secondary winding 18 of transformer 3 to output terminals 4 and 5.The outputs 14 and 15 of generator circuit 12 are connected to the control inputs 10 and 11 respectively of switches 8 and 9 respectively. It will be noted that when a d.c. voltage of a given polarity is applied between input terminals 1 and 2 and, for example, switch 8 is caused to conduct, a current will flow through the series combination of switch 8, choke 7 and the relevant half of the winding 17 in such a sense that the resulting voltage produced across winding 18 (and winding 17) will be of the opposite polarity to that set up thereacross when switch 9 is caused to conduct and current flows through the series combination of switch 9, choke 7 and the other half of primary winding 17.

Switching signal generator 12 produces switch control signals at its outputs 14 and 15 examples of which signals are illustrated at 20 and 21 respectively in the time diagrams of Fig. 2(a), 22 and 23 respectively in the time diagrams of Fig. 2(b) and 24 and 25 respectively in the time diagrams of Fig.

2(c), respectively, "high" levels of each signal corresponding to a closed or conductive state of the relevant switch and "low" levels of each signal corresponding to an open or non-conductive state of the relevant switch. The diagrams of Figs. 2(a), 2(b) and 2(c) relate to different values of a control signal applied to generator control input 13 in Fig. 1.

Referring for example to Fig. 2(a) it will be seen that the control signals 20 and 21 are such that the switches 8 and 9 of Fig. 1 together repeatedly cycle through a succession of switching states consisting of a first state of duration T1 in which switch 8 is conductive and switch 9 is non-conductive, a second state of du ration T2 in which both switches are conductive, a third state of duration T1 in which switch 8 is non-conductive and switch 9 is conductive, and the second state of duration T2 in which both switches are conductive, in that order.

Each duration T1 is arranged to be substantially one half the period of the resonant frequency of the resonant circuit including the transformer 17 of Fig.

1 "seen" by the switches 8 and 9, which resonant circuit will, in the circuit of Fig. 1, consistin the main of the inductance of primary winding 17 in parallel with capacitor 16. In the example of Fig. 2(a) the durations T2 of the second switching states are each equal to one-half of T1. The result is that the voltage on the centre-tap 34 of primary winding 17 varies as shown (not to scale) at 26 in Fig. 2(a) (assuming for convenience that the d.c. supply fed to input terminals 1 and 2 is such that terminal 2 is at zero volts and terminal 1 is positive relative thereto). It consists of half-sines of duration T1 and amplitude V alternating with dwell periods of duration T2 at zero volts. Its mean value Vm is equal to the supply voltage.The corresponding voltage variation across secondary winding 18 is shown (not to scale) at 27 in Fig. 2(a). It consists of a succession of half-sines having alternating signs, durations T1 and peak values Vp between which again occur dwell periods of duration T2 at zero volts. The quantity Vp/V is equal to the ratio of the number of turns on the secondary winding 18 to one half the number of turns on the primary winding 17.

The waveforms 22, 23,28 and 29 of Fig. 2(b) correspond to the waveforms 20,21,26 and 27 respectively of Fig. 2(a). In Fig. 2(b) the durations of the times when only one of the switches 8 and 9 is closed are again each equal to T1, i.e. substantially one half the period of the resonantfrequencyofthe resonant circuit including transformer 3 "seen" by the.switches, but now the control signal applied to generator control input 13 is such that the durations of the times when both switches 8 and 9 are closed, and hence of the zero voltage dwell times of the voltage at the centre-tap 34 of the transformer primary winding 17, are each equal to T3, where T3 is one quarter of T1.The mean value Vm of the voltage at the centre tap is still equal to the supply voltage so that, because of the reduced zero-voltage dwell times, the amplitude of the half-sines of duration T1 occurring at the centre tap is now only 5V/6. Consequently the peak values of the half-sines occurring in the waveform 29 appearing across the transformer secondary winding 18 are now +5Vp/6 and -5Vp16 respectively.

Fig. 2(c), in which waveforms 24, 25, 30 and 31 correspond to waveforms 20, 21,26 and 27 respectively in Fig. 2(a), illustrates the limit situation in which the control signal applied to generator control input 13 in Fig. 1 is such that the durations of the periods when both switches are conductive have been reduced to zero. (The durations of the periods when a given switch is conductive are the same as before, i.e. T1). The mean level Vm of the voltage waveform 30 at the center-tap 34 of primary winding 17 is still equal to the supply voltage, so that the amplitude of the half-sines making up this waveform is now 2V/3.In consequence the peak value of each half-sine occurring in the waveform 31 appearing across secondary winding 18 is now either +2Vp/3 or -2Vp/3. Waveform 31 is in this particular case actually sinusoidal.

Peak rectifier circuit 6 (which may be half-wave, full-wave, or possibly even of the multiplier type) therefore supplies d.c. voltages in the ratio of 1.5:1.25:1 to output terminals 4 and 5 in the situations illustrated in Figs. 2(a), 2(b) and 2(c) respectively. It should be noted that, because the means values of the waveforms 27, 29 and 31 are all the same, replacement of peak rectifier circuit 6 by a mean rectifier circuit, i.e. one including a series choke, would result in loss of the d.c. output voltage control facility.

It will be evident that the arrangement of Fig. 1 may be modified by transferring the choke 7, the inductance of which is preferably at least five times that of one half of the primary winding 17, to a position in the common connection from input terminal 2 to the switches 8 and 9, or the requisite inductance may be distributed between the position shown and this other position.If the resonant frequency of the resonant circuit including transformer 3 "seen" by the switches 8 and 9 is required to be, for example, approximately 60 kHz, the inductance of one half of the primary winding 17 may be arranged to be approximately 7.51lH (inductance of the whole primary winding 30 uH) and the capacitance of capacitor 16 may be approximately 220 nF. With these values the inductance of choke 7 may be approximately 100 uH. It will also be evident that capacitor 16 may be transferred to across the secondary winding 18, suitably adjusting its value if the inductance of secondary winding 18 is different from that of primary winding 17, or be replaced by a pair of capacitors, one across each of the switches 8 and 9.

If desired, the two halves of primary winding 17 may be replaced by two completely separate (but interconnected) windings. Another possibility is to dispense with the secondary winding 18 and feed the peak rectifier circuit 6 instead from suitable points on the primary winding 17 (which points may, if desired, be further from the centre-tap than those to which the switches 8 and 9 are connected).

The switching signal generator 12 may be selfoscillating (in which case the correct time relationships between the leading and trailing edges of the switching pulses at its two outputs will all have to be determined by suitably chosen internal time constants in conjunction with the control signal applied to its input 13) or be provided with a feedback signal path from the transformer 3. The control signal applied to its control input 13 may, if desired, be in the form of an error signal derived in a manner known per se by comparing a voltage derived from output terminals 4 and 5 with a reference voltage.

Fig. 3, in which corresponding components have been given the same reference numerals as their counterparts in Fig. 1, shows a possible alternative configuration to that of Fig. 1 which enabies the centre tap 34 on the primary winding 17 to be dispensed with. The only difference between the configuration of Fig. 3 and that of Fig. 1 is that the connection in Fig. 1 from inputterminal 1 to the centre tap 34 of primary winding 17 via choke 7 has been replaced by a first connection from terminal 1 to one end 32 of winding 17 via a first choke 7A, and a second connection from terminal 1 to the other end 33 of winding 17 via a second choke 7B.Thus, whereas in Fig. 1 choke 7 is common to both the series combination across terminals 1 and 2 in which switch 8 is included (items 8, half of 17, and 7) and the series combination across terminals 1 and 2 in which switch 9 is included (items 9, the other half of 17, and 7) in Fig. 3 the corresponding series combinations include different chokes, i.e. chokes 7A and 7B respectively. It should be noted however that each of these chokes is coupled to both switches 8 and 9 (directly and through winding 17 respectively) so that a current path between terminals 1 and 2 exists through it when either switch is closed; otherwise the circuit through it would be broken when the corresponding switch opens, giving rise to high voltage transients. This would be the case if the chokes 7A and 7B had, for example, been included instead directly in series with the switches 8 and 9 respectively.

The arrangement of Fig. 3 operates in an analogous manner to that of Fig. 1. When in the arrangement of Fig. 1 both switches are closed the centre tap 34 of winding 17, and hence the righthand end of choke 7, is effectively connected to terminal 2. In the corresponding situation with the arrangement of Fig. 3 the right-hand ends of the chokes 7A and 7B are connected to terminal 2 directly.

Fig. 4 shows a possible practical construction for the switching signal generator circuit 12 and switches 8 and 9 of Figs. 1 and 3. The circuit includes an astable multivibrator or flip-flop 35 available under the type number HEF4047 the complementary outputs of which pins 10 and 11) drive the gates of power MOSFETs 36 and 37 respectively via ORgates 38 and 39 respectively and pairs of complementary transistors 40 and 41, and 42 and 43, respectively. The power MOSFETs 36 and 37 constitute the controllable switches 9 and 8 respectively of Figs. 1 and 3, their drains being connected to the ends 33 and 32 respectively of transformer primary winding 17 and their sources and substrates being connected to ground (terminal 2 in Figs. 1 and 3). NPN transistors 40 and 42 have their collectors connected to a positive supply voltage of, for example, 10 volts.PNP transistors 41 and 43 have their collectors connected to ground.

The emitters of transistors 40 and 41 are commoned and connected to the gate of transistor 36, and the emitters oftransistors 42 and 43 are commoned and connected to the gate of transistor 37. The outputs of OR-gates 38 and 39 are connected to the commoned bases of transistors 40 and 41 and to the commoned bases of transistors 42 and 43 respectively.

Astable multivibrator 35 includes in conventional manner a timing capacitor 44 connected between pin 1 and a timing resistor 45 the other end of which is connected to pin 2. However, instead of being connected directly to pin 3, tme common point of capacitor 44 and resistor 45 is connected to one input of a two-input OR-gate 46 the output of which is connected to pin 3. In consequence changeover of multivibrator35, conventionally triggered by the voltage across capacitor 44 reaching a predetermined value, can be forced to occur earlier by means of a low-to-high transition in the logic level on the other input of OR-gate 46. This other input is fed with a signal derived from the ends 32 and 33 of the primary winding 17.More particularly winding end 32 is coupled to one input of a two-input NOR-gate 47 via the series combination of a diode 48 and a resistor 49, and winding end 33 is coupled to the other end of NOR-gate 47 viathe series combination of a diode 50 and a resistor 51, the diode cathodes being connected to the terminals 32 and 33 respectively. The two inputs of NOR-gate 47 are also connected to the positive supply via puli-up resistors 52 and 53 respectively. The output of NOR-gate 47 is connected to the second input of OR-gate 46 via the series combination of a capacitor 55 and a resistor 56, the common point of capacitor 55 and resistor 56 being connected to ground via a resistor 57.

The part of the arrangement of Fig. 4 described so far operates as follows. The values of the timing capacitor 44 and resistor 45 are chosen so that, when the astable multivibrator35 is free-running, each half-period of its output signal is substantially longer than, for example twice, one-half the period T1 of the resonant frequency of the resonant circuit including transformer 3 "seen" by transistor switches 36 and 37. Thus, at switch-on, multivibrator 35 starts to oscillate at a frequency which is substantially lower than this resonant frequency. The first change in its output turns one of the transistors 36 and 37 on and the other off, clamping one end 32 or 33 of the primary winding 17 to ground potential and the corresponding input of NOR-gate 47 to logic "0".The resonant circuit executes one half of an oscillation at its resonant frequency, at the end of which the other end of the primary winding 17 returns from a positive value to ground potential. When this occurs the other input of NOR-gate 47 returns two logic "0" so that a logic "1" pulse is applied to capacitor 55. This pulse is differentiated by means of the combination of capacitor 55 and resistor 57 and the result applied to one input of OR-gate 46. The other input of OR-gate 46 is at logic "0" potential at this time (because of the values chosen for timing resistor 45 and timing capacitor 44) so that the output of gate 46 goes to logic "1" and triggers multivibrator 35 to change over, turning off that one of transistors 36 and 37 which was on, and turning on the other transistor.

The resonant circuit therefore now executes another half-cycle, at the end of which multivibrator 35 is forced to change over again, and so on. Thus the arrangement produces the waveforms illustrated in Fig. 2c.

In addition to being applied to one input of OR-gates 38 and 39 respectively, the complementary output signals appearing at pins 10 and 11 of multivibrator 35 are applied to trigger inputs of respective monostable multivibrators 58 and 59. Multivibrators 58 and 59 are constituted by respective halves of an integrated circuit available under the type number HEF 4528, their (logic high to logic low transistion sensitive) trigger inputs being constituted by pins 11 and 5 respectively and their (positive pulse) outputs being constituted by pins 10 and 6 respectively. These outputs are connected to the other inputs of the OR-gates 38 and 39 respectively. The multivibrators 58 and 59 include timing capacitor/resistor combinations 60/61 and 62/63 respectively, capacitors 60 and 62 being connected between pins 14 and 15 and between pins 1 and 2 respectively.Resistors 61 and 63 connect control input 13 to pins 14 and 2 respectively. The values of resistors 61 and 63 are identical, as are those of capacitors 60 and 62, and all are chosen so that, when the voltage at control input 13 is high, for example +10 volts, the durations of the output pulses of the monostable multivibrators are very short compared with the period of the resonant frequency of the resonant circuit comprising primary winding 17 and capacitor 16 (Figs. 1 and 3) but as the voltage at control input 13 is reduced towards ground potential these durations increase to become comparable with said period.

Each of the monostable multivibrators 58 and 59 is triggered by the end of each drive pulse appearing at the corresponding output of multivibrator 35, so that each drive pulse, as it appears at the output of the corresponding OR-gate 38 or 39 is extended by the duration of the resulting output pulse from the corresponding monostable 58 or 59.If this duration is extremely short compared with one period of the aforesaid resonant frequency the presence of the multivibrators has negligible effect, but when it is increased by reducing the potential on control input 13 the waveforms occurring in the arrangement become, for example, as illustrated in Fig. 2a. The time for which each drive pulse is present at the outputs of the gates 38 and 39 is extended increasingly into the period when the next drive pulse is present at the output of the other of these gates (the start of which is determined by changeover of the multivibrator 35 which, in turn, occurs a time T1 after the preceding trailing edge occurred at the output of said other of these gates).

The various gates, diodes and transistors of Fig.

4 may have, for example, the following type numbers.

Transistors 36, 37 BUZ 10 Transistors 40, 42 BC 337 Transistors 41, 43 BC 327 OR-gates 38, 39, 46 1/4xHEF 4071 NOR-gate 47 1/4 > cHEF 4001 Diodes 48, 50 BYW 96D.

If the resonsant frequency of the resonant circuit formed by capacitor 16 and primary winding 17 in Figs. 1 and 3 is, for example, 60 kHz (the capacitance of capacitor 16 being, for example, 220 nF and the inductance of winding 17 being, for example, 30 pH) the values of the resistors and capacitors in the arrangement of Fig. 4 may be, for example, as follows.

Resistors 52, 53 22 K ohms Resistors 49, 51 10 K ohms Resistor 57 7.5 K ohms Resistor 56 1Kohm Resistor 45 47 K ohms Resistors 61,63 82 K ohms Capacitor44 180pF Capacitor 55 100 pF Capacitors 60,62 10 pF

Claims (4)

1. A circuit arrangement comprising a pair of d.c.

input terminals, a transformer, a pair of output terminals to which a winding of said transformer is coupled, first and second controllable switches which are each connected to form a series combination with a choke and at least part of a winding of said transformer in respective circuits which extend between said input terminals in such a sense that, when a d.c. voltage with a given polarity is applied between said input terminals and a given said switch is caused to conduct, a voltage will be set up across a winding of said transformer with the opposite polarity to that set up thereacross when the other said switch is caused to conduct, and a switching signal generator circuit which has a control input and is constructed to produce switch control signals at first and second outputs thereof, said first and second outputs being coupled to control inputs of said first and second switches respectively and said switch control signals being such as to control said switches to together repeatedly cycle through a succession of switching states consisting of a first state in which the first switch is conductive and the second switch is non-conductive, a second state, a third state in which the first switch is non-conductive and the second switch is conductive, and said second state, in that order, the duration of each said second state being dependent upon the value of a control signal applied to the generator circuit control input, characterized in that the duration of each of said first and third states is substantially equal to one half the period of the resonant frequency of the resonant circuit including said transformer seen by said switches, in that said second state is one in which both the first and the second switches are conductive, and in that a peak rectifier circuit is included in the coupling from the transformer to said pair of output terminals so that said circuit arrangement constitutes a d.c.-d.c. converter circuit arrangement.

2. An arrangement as claimed in Claim 1, characterized in that each switch is connected to form the corresponding series combination with the same choke.

3. An arrangement as claimed in Claim 1, characterized in that each switch is connected to form the corresponding series combination with a different choke, each said choke being coupled to both switches so that a current path between the input terminals exists through it when either switch is conductive.

4. A d.c.-d.c. converter circuit arrangement substantially as described herein with reference to Fig. 1, Fig. 3, Figs. 1 and 4 or Figs. 3 and 4 of the drawings.