GB2160355A - Annealing semiconductor devices - Google Patents
Annealing semiconductor devices Download PDFInfo
- Publication number
- GB2160355A GB2160355A GB08412491A GB8412491A GB2160355A GB 2160355 A GB2160355 A GB 2160355A GB 08412491 A GB08412491 A GB 08412491A GB 8412491 A GB8412491 A GB 8412491A GB 2160355 A GB2160355 A GB 2160355A
- Authority
- GB
- United Kingdom
- Prior art keywords
- semiconductor body
- layer
- thermal
- wafer
- annealing process
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 32
- 238000000137 annealing Methods 0.000 title claims abstract description 22
- 238000000034 method Methods 0.000 claims abstract description 22
- 238000010438 heat treatment Methods 0.000 claims abstract description 20
- 239000002019 doping agent Substances 0.000 claims abstract description 11
- 230000001052 transient effect Effects 0.000 claims abstract description 9
- 230000005855 radiation Effects 0.000 claims abstract description 8
- 230000008646 thermal stress Effects 0.000 claims abstract description 4
- 230000003213 activating effect Effects 0.000 claims abstract 2
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 230000001427 coherent effect Effects 0.000 abstract 1
- 235000012431 wafers Nutrition 0.000 description 36
- 239000000463 material Substances 0.000 description 11
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 10
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 230000002093 peripheral effect Effects 0.000 description 4
- 238000001816 cooling Methods 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 241000465531 Annea Species 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 description 1
- 229910052790 beryllium Inorganic materials 0.000 description 1
- ATBAMAFKBVZNFJ-UHFFFAOYSA-N beryllium atom Chemical compound [Be] ATBAMAFKBVZNFJ-UHFFFAOYSA-N 0.000 description 1
- 230000003749 cleanliness Effects 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910002804 graphite Inorganic materials 0.000 description 1
- 239000010439 graphite Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000010348 incorporation Methods 0.000 description 1
- 229910052749 magnesium Inorganic materials 0.000 description 1
- 239000011777 magnesium Substances 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000035882 stress Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B31/00—Diffusion or doping processes for single crystals or homogeneous polycrystalline material with defined structure; Apparatus therefor
- C30B31/20—Doping by irradiation with electromagnetic waves or by particle radiation
- C30B31/22—Doping by irradiation with electromagnetic waves or by particle radiation by ion-implantation
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B33/00—After-treatment of single crystals or homogeneous polycrystalline material with defined structure
Landscapes
- Chemical & Material Sciences (AREA)
- Engineering & Computer Science (AREA)
- Organic Chemistry (AREA)
- Physics & Mathematics (AREA)
- Metallurgy (AREA)
- Materials Engineering (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
Abstract
In a transient annealing process for activating implanted dopants in a layer of semiconductor body (1), in which the implanted layer is heated very rapidly by coherent light radiation heating or the equivalent thereof and held at a high temperature for a short period after which the layer is cooled rapidly, the semiconductor body (1) is supported throughout on a support structure (2) and is closely surrounded over at least the major part of its periphery by a thermal guard structure (5) which is adapted to reduce the thermal stresses set up across the supported semiconductor body during the annealing process. <IMAGE>
Description
SPECIFICATION
Improvements relating to semiconductor devices
This invention relates to the manufacture of semiconductor devices and relates more specifically to manufacturing techniques involving ion implantation of dopants for producing active semiconductor layers for incorporation in gallium arsenide and other semiconductor devices.
After ion implantation of dopants into the layer of semiconductor material concerned (e.g. gallium arsenide) the semiconductor layer must be annealed in orderto restorethecrystal perfection ofthe implanted layer and to activate the implanted dopants.
Traditionally, the annealing of the implanted semiconductor has been achieved by heating the imlanted layer in a furnace for between 10-30 minutes at a temperature of between 800 C-900 C. However, this somewhat protracted heating of the implanted semiconductor layer can result in the egress of dopants from andlor diffusion of the dopants within the layer andlorthe ingress of adventitious impurities into the layer thereby giving rise to degraded dopant profiles andlor inferior electrical properties.
In orderto overcome these annealing problems, so-called transient annealing techniques have recently been developed in which the implanted semiconductor layer is heated very rapidly (i.e. in a few seconds) to about 9000C say and held there for a short period (i.e. up to 20 seconds) after which the layer is cooled rapidly. It is nowwell establishedthattransient annealing can activate implanted dopants in semicon ductorswhilst largely maintaining sharp dopant profiles by reducing dopantdiffusion during the annealing process.
However,forthe purpose of achieving sufficiently rapid and intense heating ofthe implanted semiconductor layer graphite strip heaters have been used, as have electron beam-heating, laser beam-heating and incoherent light radiation heating techniques. Incoherent light radiation heating (i.e.so-called flash lamp annealing) has many advantages such as cleanliness, speed and ease of operation, overthe other heating techniques referred to. Nevertheless, a major problem with the incoherent light radiation or other rapid heating is that after transient annealing of the implanted semiconductor material the material displays evidence ofthe undesirable phenomenon known as crystallographic slip to which gallium arsenide appears to be particularly vulnerable.This slip is believed to resultfrom the thermal gradients and stresses which are set up across the semiconduc torlayerduringtheannealing process.
The present invention accordingly provides a tran
sientannealing process using incoherent light radia
tion heating orthe equivalent thereof, in which the
implanted semiconductor body is supported on a
support structure and is closely surrounded over at
least the major part of its periphery by a thermal guard structure or equivalent which is adapted to reduce the thermal stresses set up across the supported semiconductor body during the annealing step.
In carrying out the present invention the implanted semiconductor body will usually comprise a circular wafer in which case the thermal guard structure conveniently comprises a guard ring having a slightly larger inner diameterthanthe diameterofthe semiconductor wafer.
Ideally, the material of the thermal guard structure should be the same as or have the same thermal properties as the wafer being annealed but the fragility of certain materials (e.g. gallium arsenide) precludes this ideal arrangement. However, for practical purposes it has been found that silicon may be used forthe material of the thermal guard structure.
By way ofexamplethe present invention will now be described with reference to the accompanying drawing in which:
Figure 1 shows a cross-sectional view of an implanted semiconductorwafersuitablysupported during a transient annealing process utilising incoherent light radiation heating means; Figure 2 shows a viewsimilarto that of Figure 1 but utilising a thermal guard structure in accordance with the present invention; and,
Figure 3 shows a plan view of the semiconductor wafer surrounded by the thermal guard structure.
Referring to Figure 1 of the drawing, the implanted semiconductorwafer 1 may, for example, comprise gallium arsenide implanted with silicon, beryllium or magnesium and in orderto activate the implanted dopantwhilst preserving the dopant profile, as implanted, the wafer 1 is subjected to transient annealing whilst it is supported on a support wafer 2 which may be of silicon or quartz. The rapid heating of the implanted wafer 1 to 900"C, say, injustafew seconds is provided by an array of incoherent light radiation heating lamps 3 located above and below the supported wafer 1 and reflectors 4 serve to concentrate the radiated heat on to the semiconductor wafer 1 and the support wafer 2.
The semiconductorwafer 1 is heated for a short period of unto 20 seconds afterwhich the wafer is cooled rapidly. However, using this known technique of transient a nnealing, the annea led semiconductor wafer 1 usually suffers from crystallographic slip and gallium arsenide appears to be particularly prone to such slip. This slip is believed to result from thermal gradients which occur between the outer periphery and the central region ofthe semiconductorwafer 1 during the heating and cooling steps of the annealing process.
When the lamps 3 are switched on to commence the transient annealing process, both of the wafers 1 and 2 are rapidly heated up to about 900'C However, since the radiant energy at all points on the semiconductor and support wafer assembly is substantially equal, the rate of heating of the wafer assembly at any point thereon is inversely proportional to the thermal mass atthat point. The thermal mass ofthe gallium arsenide wafer 1 togetherwith the support wafer 2, exceeds thatofthesupportwaferalone. Consequently, that partofthe support wafer 2 which is not covered bythe gallium arsenide wafer 1 will heat up more rapidly than the part of the wafer 2which is overlaid by the wafer 1 and combines with itto define a higher thermal mass than the support wafer alone.
This will result in a thermal gradient at the periphery of the semiconductorwafer 1 where thermal conduction from the hotter uncovered part of the support wafer 2 will cause the peripheral edge region ofthe wafer 1 to reach a higher temperature than the centre of the wafer 1.
Moreover, duringthe cooling step ofthe annealing process the uncovered part of the supportwafer 2 surrounding the periphery ofthewafer 1 will cool down fasterthan the rest of the wafer assembly so that once again thermal conduction will cause the periphery of the wafer 1 to be at a different temperature from the centre region of the wafer. Such thermal stresses give rise to slip. Since in most instances the slip has proved to be confined to a peripheral region within one centimetre of the wafer periphery, it is reasonable to assume that the temperature gradient responsiblefortheslip occurs across this region ofthe wafer 1.
The present invention as illustrated in Figures 2 and 3 seeks to eliminate or at least alleviate this major problem of slip by preventing the occurrence of high thermal gradients in the semiconductorwafer 1 during the annealing process. In order to achieve this a thermal guard ring 5 is positioned on the support wafer 2 so that it surrounds the semiconductor wafer 1 leaving a small gap of about 1 mm between the periphery of the semiconductor wafer 1 and the inner periphery ofthe guard ring 5. Ideally, the width ofthe guard ring should be at least 1cm and its thickness approximately the same as the semiconductorwafer 1.
As previously mentioned, this guard ring 5 should ideally have identical properties to and thus be the same material asthewafer 1 which is to be annealed.
However, the fragility of such semiconductor materials (e.g. gallium arsenide) frequently precludesthe use of an ideal material butforpractical purposes silicon mayforexample be used as the material ofthe guard ring instead of gallium arsenide.
By providing thethermal guard ring 5 which, in effect, serves to extend the peripheral region of the semiconductorwafer 1 outwardly by a distance of about icy, the highthermal gradients occurring during heating and cooling ofthe annealing process will be generated largely acrossthe guard ring 5 instead of acrossthe outer peripheral region of the semiconductorwafer 1. Consequently, the wafer 1 will, at worst, be subjected to much lowertemperature gradientsthan if a guard ring 5were not present and this serves to eliminate or at least reduce slip.
Itwill be understoodthatthe guard structure
provided according to the present invention could
also be used tc advantage when less desirable forms
of rapid heating (e.g. laser beam heating) are used in the transient annealing process. Moreover,the princi
ple of providing a thermal guard ring in cases where the wafer of semiconductor material to be annealed was of non-circularform would still apply provided the inner periphery of the guard ring conformed to the outer configuration ofthe semiconductor wafer.
Claims (4)
1. Atransient annealing process for activating implanted dopants in a layer of a semiconductor body, in which the implanted layer is heated very rapidly by incoherent light radiation heating orthe equivalent thereof and held at a high temperature for a short period afterwhich the layer is cooled rapidly, in which the semiconductor body is supported throughout on a support structure and is closely surrounded over at leastthe major part of its periphery by a thermal guard structure or equivalent which is adapted to reduce the thermal stresses set up across the supported semiconductor body during the annealing process.
2. Atransientannealing process as claimed in claim 1, in which the semiconductor body comprises a circularwaferwhich is surrounded by a thermal guard ring of slightly larger diameterthan the diameter of the semiconductorwafer.
3. A transient annealing process as claimed in claim 1 orclaim 2, in which the thermal guard structure comprises silicon.
4. Atransientannealing process substantially as hereinbefore described with reference to the accompanying drawings.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB08412491A GB2160355B (en) | 1984-05-16 | 1984-05-16 | Annealing semiconductor devices |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB08412491A GB2160355B (en) | 1984-05-16 | 1984-05-16 | Annealing semiconductor devices |
Publications (3)
Publication Number | Publication Date |
---|---|
GB8412491D0 GB8412491D0 (en) | 1984-06-20 |
GB2160355A true GB2160355A (en) | 1985-12-18 |
GB2160355B GB2160355B (en) | 1988-01-13 |
Family
ID=10561041
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB08412491A Expired GB2160355B (en) | 1984-05-16 | 1984-05-16 | Annealing semiconductor devices |
Country Status (1)
Country | Link |
---|---|
GB (1) | GB2160355B (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0307608A1 (en) * | 1987-09-16 | 1989-03-22 | Siemens Aktiengesellschaft | Apparatus and process for annealing semiconductor wafers |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0027712A1 (en) * | 1979-10-17 | 1981-04-29 | Itt Industries, Inc. | Semiconductor annealing |
GB2060998A (en) * | 1979-10-17 | 1981-05-07 | Itt Ind Ltd | Semiconductor annealing |
GB2081008A (en) * | 1980-07-29 | 1982-02-10 | Itt Ind Ltd | Semiconductor annealing |
-
1984
- 1984-05-16 GB GB08412491A patent/GB2160355B/en not_active Expired
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0027712A1 (en) * | 1979-10-17 | 1981-04-29 | Itt Industries, Inc. | Semiconductor annealing |
GB2060998A (en) * | 1979-10-17 | 1981-05-07 | Itt Ind Ltd | Semiconductor annealing |
GB2081008A (en) * | 1980-07-29 | 1982-02-10 | Itt Ind Ltd | Semiconductor annealing |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0307608A1 (en) * | 1987-09-16 | 1989-03-22 | Siemens Aktiengesellschaft | Apparatus and process for annealing semiconductor wafers |
US5057668A (en) * | 1987-09-16 | 1991-10-15 | Siemens Aktiengesellschaft | Device for the implementation of a curing process at a semiconductor wafer and method for curing a semiconductor wafer |
Also Published As
Publication number | Publication date |
---|---|
GB2160355B (en) | 1988-01-13 |
GB8412491D0 (en) | 1984-06-20 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
732 | Registration of transactions, instruments or events in the register (sect. 32/1977) | ||
PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 19920516 |