GB2153588A - Isolation of input and output in an integrated injection logic device - Google Patents

Isolation of input and output in an integrated injection logic device Download PDF

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Publication number
GB2153588A
GB2153588A GB08402551A GB8402551A GB2153588A GB 2153588 A GB2153588 A GB 2153588A GB 08402551 A GB08402551 A GB 08402551A GB 8402551 A GB8402551 A GB 8402551A GB 2153588 A GB2153588 A GB 2153588A
Authority
GB
United Kingdom
Prior art keywords
land
switching
output
input
polysilicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GB08402551A
Other versions
GB8402551D0 (en
Inventor
Peter John Ward
Peter Charles Hunt
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Plessey Co Ltd
Original Assignee
Plessey Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Plessey Co Ltd filed Critical Plessey Co Ltd
Priority to GB08402551A priority Critical patent/GB2153588A/en
Publication of GB8402551D0 publication Critical patent/GB8402551D0/en
Priority to DE19853503067 priority patent/DE3503067A1/en
Priority to NL8500259A priority patent/NL8500259A/en
Priority to JP60017695A priority patent/JPS60187051A/en
Publication of GB2153588A publication Critical patent/GB2153588A/en
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0214—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L
    • H01L27/0229—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L of bipolar structures
    • H01L27/0233—Integrated injection logic structures [I2L]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H01L21/2257—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer being silicon or silicide or SIPOS, e.g. polysilicon, porous silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1004—Base region of bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/732—Vertical transistors
    • H01L29/7327—Inverse vertical transistors

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Bipolar Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)

Abstract

The device comprises contiguous input and output regions 16, 17 diffused into a semiconductor switching land 3, overlaid with a layer of polysilicon 6 doped to produce contiguous areas 13, 14 of opposite type conductivities. The dopant is diffused into the switching land during heat treatment so that underlying regions of land accept dopant from the doped areas of polysilicon to provide input and output regions electrically isolated from each other by the p-n junction defined in the polysilicon layer. <IMAGE>

Description

SPECIFICATION Improvements relating to semiconductor devices This invention relates to semiconductor devices and relates more particularly to devices which may form part of injection logic (e.g. 12L) devices.
Known integrated injection logic (12L) devices comprise vertical multi-collector transistors which are arranged to be supplied with injection current from appertaining lateral current source transistors.
The vertical multi-collector transistor of each device may consist of a p+ input diffused into a rectangular p-type switching land (base), a row of n+ outputs (collectors) diffused into the switching land at regular intervals there-along and an n-type layer (emitter) into which the p-type switching land is itself diffused.
To provide the necessary electrical isolation between the p+ input and the n+ outputs of such known multi-collector transistors the spacing between the input and outputs needs to be such that the speed of operation of the transistor which is governed to a large extent by the area ratio between the lateral active area of the switching land and the lateral area of each output is impaired.
According to the present invention an improvement in the speed of operation of a semiconductor switching device in an injection logic device including an input and at least one output is produced by applying to the surface of a switching land of one type conductivity a layer of polysilicon doped to provide contiguous area with opposite type conductivities whereby the dopant is diffused into the switching land so that underlying regions of said land accept dopant from the doped areas of polysilicon but the input and output of the switching device are electrically isolated from each other by the pn junction defined in the polysilicon layer.
By enabling the input and output (s) of the switching device to be located adjacent to or in much closer proximity with one another the crosssectional active area of the switching land is substantially reduced thereby improving the speed performance of the switching device.
The present invention is especially applicable to the improved integrated injection logic devices forming the subject of our co-pending Patent Application No.
By way of example the present invention will now be described with reference to the accompanying drawings in which: Figures 1 and 2 show diagrammatic part-plan and cross-sectional views of a known form of switching transistor forming part of an integrated injection logic device; and Figures 3 and 4 show views corresponding to Figures 1 and 2 of a switching transistor constructed in accordance with the present invention.
Referring to Figures 1 and 2 of the drawings a bipolar switching transistor (e.g. silicon) is shown which comprises a p+ input region 1 and an n+ output region (collector) 2 diffused into a rectangular p-type switching land (base) 3 which is itself diffused into an n-type layer (emitter) 4 carried by an n+ substrate 5.
The upper surface of the switching transistor is overlaid with dielectric material 6 (e.g. silicon dioxide) as shown and electrical connections (not shown) will be made to the input and output regions 1 and 2 through windows 7 and 8 in the dielectric material.
In the example illustrated the switching transistor is arranged to be supplied with injection current from a lateral p-n-p injection transistor the p+ injector of which is shown at 9 to which an electrical connection will be made through window 10 in the dielectric material 6.
The speed of operation of the switching transistor is largely dependent upon the ratio between the active cross-sectional area of the switching land 3 which is determined by the spacing of the output region 2 from the input region 1 along the switching land 3 and the corresponding area of the output region 2. An improvement in the speed of operation of the transistor can be achieved by reducing the active cross-sectional area of the switching land 3 relative to the area of the output region 2.
The present invention achieves such a reduction in the active area of the switching land 3 by the construction shown in Figures 3 and 4. In this construction a layer of polysilicon 12 having n+ and p+ doped contiguous regions 13 and 14 which defined a pn junction 15 between them is applied during manufacture of the device to the p-type switching land 3 so that p+ and n+ dopants diffuse into the switching land 3 as shown at 16 and 17 during heat treatment. As will readily be apparent from the drawings the active area of the switching land 3 is very much reduced whilst electrical isolation between the p+ input 13 and the n+ output 14 is provided by the pn junction in the poly- silicon layer and consequently the speed of operation of the switching transistor is significantly improved.
The polysilicon layer 12 may in practice be provided by interdigitated L-shaped nt and p+ doped areas and a multiplicity of such interdigitated areas doped with opposite type conductivities dopants may be provided in the case of multi-output transistors which may form part of integrated injection logic devices.

Claims (5)

1. A semiconductor switching device comprising contiguous input and output regions diffused into a semiconductor switching land, in which the switching land which is one type conductivity is overlaid with a layer of polysilicon doped to produce contiguous areas of opposite type conductivities with the dopant being diffused into the switching land during heat treatment so that underlying regions of said land accept dopant from the doped areas of polysilicon to provide said input and output regions but these regions being electrically isolated from each other by the p-n junction defined in the polysilicon layer.
2. A multi-output transistor, including a semiconductor switching device as claimed in claim 1.
3. An integrated injection logic device according to our co-pending Patent Application No. 8402477, comprising a multi-output transistor as claimed in claim 2.
4. A switching transistor or integrated injection logic device as claimed in any of the preceding claims, in which the polysilicon layer is provided by interdigitated L-shaped n+ and p+ doped areas.
5. A switching transistor substantially as hereinbefore described with reference to Figures 3 and 4 of the accompanying drawings.
GB08402551A 1984-01-31 1984-01-31 Isolation of input and output in an integrated injection logic device Withdrawn GB2153588A (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
GB08402551A GB2153588A (en) 1984-01-31 1984-01-31 Isolation of input and output in an integrated injection logic device
DE19853503067 DE3503067A1 (en) 1984-01-31 1985-01-30 SEMICONDUCTOR SWITCHING ELEMENT
NL8500259A NL8500259A (en) 1984-01-31 1985-01-30 SEMICONDUCTOR DEVICE.
JP60017695A JPS60187051A (en) 1984-01-31 1985-01-31 Semiconductor switching element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB08402551A GB2153588A (en) 1984-01-31 1984-01-31 Isolation of input and output in an integrated injection logic device

Publications (2)

Publication Number Publication Date
GB8402551D0 GB8402551D0 (en) 1984-03-07
GB2153588A true GB2153588A (en) 1985-08-21

Family

ID=10555834

Family Applications (1)

Application Number Title Priority Date Filing Date
GB08402551A Withdrawn GB2153588A (en) 1984-01-31 1984-01-31 Isolation of input and output in an integrated injection logic device

Country Status (4)

Country Link
JP (1) JPS60187051A (en)
DE (1) DE3503067A1 (en)
GB (1) GB2153588A (en)
NL (1) NL8500259A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3841777C2 (en) * 1988-12-12 1994-06-23 Telefunken Microelectron Semiconductor device with vertical npn planar transistor

Also Published As

Publication number Publication date
JPS60187051A (en) 1985-09-24
NL8500259A (en) 1985-08-16
DE3503067A1 (en) 1985-08-08
GB8402551D0 (en) 1984-03-07

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