GB2149618A - Telecommunication line circuit and associated voltage converter - Google Patents

Abstract

A telecommunication line circuit includes line amplifiers LOAO and 1 which are connected to respective conductors TP and RG of a telecommunication line via feed resistances (R0, R1, Figure 1). A loop current measuring circuit SENC is coupled with the feed resistances and supplier signals to a resistance synthesis circuit LADC and impedance synthesis circuit LAAC the outputs of which are coupled back to the inputs of the line amplifiers. The resistance synthesis circuit is supplied with a signal VEET representative of line current by a circuit FDC (Figure 3) which has a controlled amplifier (OA4) and a resistance capacitance low-pass filter (R8, C1). The filter couples the measuring circuit to the controlled amplifier. Transistors (T3-T6) comprise a regulator which prevents sudden changes in the sensed line current from causing overshoot in the control signal (VEET) due to the time constant of the RC filter, by bypassing the resistor (R8) when the sensed current suddenly increases, and by short circuiting the capacitor when it suddenly decreases. <IMAGE>

Description

SPECIFICATION Telecommunication line circuit and associated voltage converter The present invention relates to a telecommunication line circuit including line amplifiers coupled to respective line conductors of a telecommunication line via feed resistances, a loop current measuring circuit which is coupled with said feed resistances, a resistance synthesis circuit including said loop current measuring circuit whose output is coupled back to inputs of said amplifiers and which includes at least controlled means to adapt the characteristics of the signals applied thereat, and an impedance synthesis circuit which also includes said loop current measuring circuit whose output is coupled back to inputs of said amplifiers via at least a DC blocking capacitor.

Such a telecommunication line circuit is already known from Belgian patent No. 894422 (R.C.W. CHEA et al 8-7-5-2-5-2-). When the controlled means are preceded by a resistance/capacitance lowpass filter and the gain provided by these means is suddenly decreased, e.g. when hooking off the telephone, a steep signal increase may be produced at the output of the loop current measuring circuit because the resistance synthesis circuit is not able to follow this gain change immediately due to the presence of the filter capacitance. This steep signal is applied via the DC blocking capacitor to the impedance synthesis circuit which may therefore become inoperative, e.g. by saturation of the amplifiers, and temporarily inhibit the transmission of signals.

The present invention according to one aspect seeks to provide a telecommunication line circuit of the above type, but which minimises the above drawback.

According to one aspect of the invention there is provided a telecommunication line circuit including line amplifiers coupled to respective line conductors of a telecommunication line via feed resistances, a loop current measuring circuit which is coupled with the feed resistances, a resistance synthesis circuit including the loop current measuring circuit whose output is coupled back to inputs of the amplifiers and which includes at least controlled means to adapt to the characteristics of the signals applied thereat, and an impedance synthesis circuit which also includes the loop current measuring circuit whose output is coupled back to inputs of the amplifiers via at least a d.c. blocking capacitor, characterised in that regulating means is associated with the controlled means which comprises a controlled amplifier, a resistance-capacitance lowpass filter coupling the measuring circuit to the controlled amplifier to effect a change of charge on the capacitance when the gain of the controlled amplifier is changed by a predetermined value.

Due to the fact that regulating means are associated with the controlled means which are constituted by a controlled amplifier, and that a resistance-capacitance lowpass filter couples the measuring circuit to the controlled amplifier and give rise to a change of the charge on the capacitance when the gain of the controlled amplifier is changed by a predetermined value.

In this way the charge on the filter capacitance is rapidly adapted to the new gain so that no signal jump will be produced at the output of the loop current measuring circuit.

A second aspect of the present invention also relates to a voltage converter with an input and an output and adapted to convert an input voltage at said input into an output voltage at said output.

Such a voltage converter circuit is generally known in the art. However according to this second aspect there is provided a voltage converter with an input and an output and adapted to convert an input voltage at the input into an output voltage at the output, characterised in that it includes two reference voltages connected by corresponding impedances to a common junction point which is coupled to the output via a buffer, and filter means allowing only variations of the input voltage to be followed by the output voltage and preventing variations of the reference voltages from having an influence on the output voltage.This arrangement includes two reference voltages connected by corresponding impedances to a common junction point which is coupled to the output via a buffer, and filter means allowing only variations of input voltage to be followed by the output voltage and preventing variations of the reference voltages from having an influence on the output voltage.

Such a voltage converter is particularly, but not exclusively, useful in a telecommunication line circuit to derive from a general exchange ground (the input voltage) a fault free output voltage which follows all variations of the general ground, as is required because all exchange voltages are referred to this general ground. This output voltage has a value which is for instance located between those of the two reference voltages and may be used in the line circuit for instance for biasing operational amplifiers which are fed between these two reference voltages.

In order that the invention and its various other preferred features may be understood more easily, an embodiment thereof will now be described, by way of example only, with reference to the drawings, in which: Figure 1 is a schematic view of telephone circuitry including a telecommunication line circuit SLIC and an associated voltage constructed in accordance with the invention, Figure 2 is a schematic block diagram of the telecommunication line circuit SLIC of Figure 1, Figure 3 is a detailed schematic block diagram of the filter and drive circuit FDC of Figure 2, Figure 4 is a more detailed schematic block diagram of the switch hook detection circuit SHDC of Figure 2, Figure 5 is a more detailed schematic block diagram of the current limiting circuit CLC of Figure 2, and Figure 6 is a detailed circuit diagram of the grounding circuit GRC shown in Figure 1.

The telephone circuitry shown operates with the following supply voltages: V which is at ground potential; V- which is equal to -48 or -60 Volts; VAUX which is an auxiliary voltage 15 Volts above V-; VAG which is 7.5 Volts above V-; B1 and B2 which are bias voltages provided by constant current sources and which when applied to transistors produce therein constant currents; V1 to V10 which are further supply voltages.

This telephone circuitry includes a line circuit LC which is connected in cascade with a switch circuit HVC between a telephone line with conductors Ll0 and Ll1, connected to a telephone subset TSS, and a telephone switching network SNW. Line circuit LC includes the cascade connection of a subscriber line interface circuit SLIC, a digital signal processor DSP, a transcoder and filter circuit TCF and a dual processor terminal controller DPTC.

Subscriber subset TSS includes a normally open hook switch HS connected between the line conductors Liy and Ll1.

HVC is for instance of the type disclosed in the Belgian patent application No. 260 208 filed on September 19,1983 and entitled "Contacts Blectroniques et dispositifs associés". It includes 4 pairs of switch contacts sw00, swOl to sw30, swazi and has line terminals LO and L1 connected to line conductors Ll0 and Ll1 respectively, test terminal TO and T1 connected to a test circuit TC, ringing terminals RG0 and RG1 connected to a ringing circuit RC, tip and ring terminals TP and RG connected to the like named outputs of line amplifiers LOA0 and LOA1 in the SLIC respectively and terminals STA, STB, SRA, SRB connected to like named terminals of the SLIC.In switch circuit HVC the line terminals LO and L1 are connected to TP and RG via the series connection of sw00 or swot, a 50 ohms line feed resistor RO and R1 and switch swi 0 or sw 1 respectively. The respective junction points STB and SRA of sw00 and R0 and of swOl and R1 are connected to TC via sw20 and sw21 respectively, whilstthejunction points point STA and SRB or RO and sw10 and R1 and swill are connected to RC via sw30 and sw31 respectively. Switch contacts sw00, swO1, sw10 and swill are normally closed, whereas the other switch contacts are normally open.These switch contacts are controlled by the SLIC so that HVC is able to establish a connection between TSS, on the one hand, and SLIC, TC or RC on the other hand, as well as between TC and SLIC. The function of TC is to test the line to TSS and to the SLIC and that of RC is to apply a ringing signal to this line.

The subscriber line interface circuit S LIC is a two-terminal circuit on the side of the subscriber subset TSS and is a four-wire one towards SNW. It has a speech receiving input terminal Rx (with VAG providing the ground return) and a speech transmitting ouput Tx (again with VAG providing the ground return), Rx and Tx being connected to DSP. The SLIC further has a 12 kHz or 16 kHz metering signal input terminal MTCF connected to TCF, data input and output terminals DSP1 and DSP2 connected to DSP and the above-mentioned terminals STA, STB, SRA, SRB, TP and RG connected to HVC.

The digital signal processor DSP converts a digital speech signal received from TCF into an analog version at speech input terminal Rx of the SLIC. Conversely it converts an analog speech signal at speech output terminal Tx into a digital version which is applied to TCF. DSP also includes a two wire four wire converter to avoid singing.

The following drive bits are transmitted by DSP to data input terminal DSP1 of the SLIC: BR1: a polarity reversal bit to indicate that the polarity on RG has to be made high (1) or low (0); BRO: a polarity reversal bit to indicate that the polarity on TP has to be made high (1) or low (0); FR: a feed characteristic bit to indicate that the synthesized line feed resistance should be high ohmic (1) or low ohmic (0). The meaning of synthesized feed resistance will be explained later; TB: a trunk bit to indicate that the SLIC is coupled to a trunk line (1) or not (0). The use of the bit is not explained in the present application.

CTi and CT0: current limit bits to indicate four possible maximum line current conditions; BV: a battery bit to indicate that the exchange battery V- is -48 Volts (0) or -60 Volts (1); SPMI: a metering signal bit to indicate that a metering signal applied to SLIC byTCF has to be admitted in the SLIC (0) or not (1).

Finally, the DSP also receives on its data output terminal DSP2 control data bits transmitted by the SLIC. As will be explained later, these are the same bits as those transmitted at DSP1 except that the four bits FR, TB, CTi and CT0 are respectively replaced by: SHD: a switch hook detection bit SHD,to indicate that the line loop between SLIC and TSS is open (0) or closed (1); RT: a ring trip bit to indicate that subsequent to the transmission of a ringing signal from TC to TSS the hook switch HS therein has been closed (1) or not (0); OC: an overtemperature bit to indicate that the temperature of LOA0 and!or LOA1 is above (1 ) or below (0) a predetermined value; VPA: an individual line conductor sense bit to indicate that a ground has been connected in TSS to at least one of the line conductors L10 and Ll1 (1) or not (0); To be noted that whereas HVC, SLIC and DSP are individually associated to the telephone line, the circuits TCF and DPTC are provided in common for a number of such lines, e.g. 8 lines, as indicated by the multipling arrows.

The above-mentioned terminals TP, RG, STA, STB, SRA, SRB, Rx, MTCF, DSP1, Tx and DSP2 are connected as follows in the SLIC which is represented in detail in Figure 2.

Tip and ring output terminals TP and RG constitute the outputs of line operational amplifiers LOA0 and LOA1 respectively, each of which may for instance be of the type disclosed in European patent application filed on August 1983 and entitled "Electronic power overload protection circuit" - No. 83201226.4 (L.BIENSTMAN 1/2).

These amplifiers are fed between V- and the regulated voltage VEET provided at the like named output VEET of a filter and drive circuit FDC (Figure 3) which will be described in detail later. The output TP of LOA0 is connected to the inverting input TAC thereof via feedback resistor R2 and a similar connection through resistor R3 exists between the output RG of LOA1 and the inverting input RAC thereof. These inverting inputs TAC and RAC are connected to the like named output terminals of a line amplifier AC control circuit LAAC and the non-inverting inputs TDC and RDC of LOA0 and LOA1 are connected via resistors R4 and R5 to the output terminals VTI and VRI of a line amplifier DC control circuit LADC which is also associated to a polarity reversal circuit BRC.LAAC and LADC, BRC are disclosed in the Belgian patent applications entitled "Voltage-to-current converter and impedance synthesis circuit using same" and "Telecommunication line circuit and associated polarity reversal circuit" which are filed together with the present Belgian patent application (Patents Nos. 898052 and 898 051).

LADC has output terminals VTI and VRI, as already mentioned, as well as VX which is connected to FDC (Figure 3), X which is connected to LAAC and BR11 to BR33 which are connected to BRC which is controlled by the above control bits BRO and BR1. Moreover, LADC has input terminal VRG connected to the output of a circuit VSC which provides a temperature independent reference voltage VRG at its like named output, input terminal VEET connected to the like named output terminal VEET of FDC, and a metering signal input terminal MS which is connected to the output of a unity gain operational amplifier OAl. The non-inverting input of OAl is connected to the commoned drain electrodes of PMOS transistor PMO and NMOS transistor NMO which further have gate electrodes both connected to a control terminal SPMI controlled by the above-mentioned like named control bit SPMI. The source electrode of NMO is connected to VAG and that of PMO is connected to the output of a high-pass filter HPF1 with input terminal VAG and input terminal MTCF to which a 12 kHz or 16 kHz metering signal may be applied by TCF.This signal is gated to input terminal MS via the gate PMO, NMO which is enabled when bit SPMI = 0 as PMO is then conductive and NMO blocked and which is disabled when SPMI = 1 as NMO is then conductive and PMO blocked.

As described in the second of the above-mentioned Belgian patent applications, in response to MS, VEET and VRG, LADC generates bias voltages VH' = (V+) - 2 AV and VL' = VEET at its outputs VTI and VRI respectively wherein AV is equal to the sum of a fixed voltage on VRG-VAG and a variable voltage VE-VAG where VG is equal to the envelope of MS. It also provides bias voltage VH' at its output terminal VX and moreover a metering signal dependent DC current I at its output terminal X connected to LAAC.

LAAC has output terminals TAC, RAC and input terminal X, as already mentioned above, and further has an input terminal VFB, to which there is applied a sensed speech/metering signal VFB, as well as an input terminal SMI to which an input speech/metering signal SMI is applied. An input speech signal received from DSP is applied between speech input terminal Rx and VAG of a high-pass filter HPF2 whose output is connected to the input terminal SMI of LAAC via the series connection of unity gain operational amplifier OA2 having an isolating function and a resistor R6. The above-mentioned metering signal MS is applied to the same input terminal SM via resistor R7. To input terminal VFB there is applied a speech/metering signal VFB obtained by sensing the line Ll0, Ll1.

As described in the first of the above-mentioned Belgian patent applications, in response to the input and sensed speech/metering signals applied to SMI and VFB and of the above-mentioned mirrored DC current I, the LAAC applies balanced currents I-i and l+i to the inverting inputs TAC and RAC of LOA0 and LOA1 respectively, i being an AC current which is function of the sensed and input speech/metering signals. As a consequence and depending on the bits BRO, BR1 the DC voltages VH = (Vt (V-) - V and VL = VEET + AV may appear at the outputs TP and RG of LOA0 and LOA1 respectively.

Finally, amplifiers LOA0 and LOA1 also have terminals TP1, TP2 and3, TP4 connected to a common amplifier protection circuit ATPC which has overtemperature output terminal OC on which appears control bit OC and is of the type disclosed in the above-mentioned patent application.

Input terminals STA, STB, SRA and SRB of the SLIC constitute the input terminals of a current measuring circuit SENC which has output terminals CO1 and JO to J3 and which is described in the Belgian patent No.

898050 which was filed together with the present Belgain patent application and entitled "Coupling circuit and assoicated current measuring devices". Output terminal CO1 is connected to the above mentioned filter and drive circuit FDC via the cascade connection of low-pass filter LP1 and a full wave rectifier circuit AV, the output terminal VEET of FDC being connected to the like named feed terminals of LOAO and LOA1 and to LADC, as already mentioned. The output of AV is also connected to a switchook detection circuit SHDC, a ringtrip detection circuit RTDC and a current limiting circuit CLC. SHDC, RTDC and CLC have output terminals SHD, RT andCL respectively on which appear the like named control bits SHD, RT and CL respectively.

Output terminals JO to J3 of SENC are connected to like named terminals of an individual line conductor sensing circuit ILCSC which has output terminal VPA on which appears control bit VPA, ILCSC is also disclosed in the last mentioned Belgian patent application.

A sensed speech/metering signal appearing at the output C01 of SENC is applied via DC blocking capacitor C and amplifier stage AS, on the one hand to input terminal VFB of LAAC and on the other hand to the speech output terminals Tx and VAG via low-pass filter LPF2, notch filter NF, buffer circuit BUF and high-pass filter HPF3. LPF2 is an anti-aliasing filter and NF ensures a full rejection of the metering signal without attenuating the speech signal. The buffer circuit BUF is used to isolate NF from HPF3 which serves to remove all DC from the signal applied to it.

The above-mentioned data input and output terminals DSP1 and DSP2 are connected to the input and output of a shift register SR used to store the above-mentioned bits which are used in the SLIC in the following way: BR1 and BRO are used to control ILCSC and BRC; FR and FR are used to control FDC; CTi and CTO are used to control CLC; BV and BV are used to control FDC; SPMI is used to control the gate PMO, NMO; The inverse of the control bits are provided by an obvious inverting circuit (not shown).

To be noted that also the bit CL provided at the output CL of CLC is used to control FDC which is further controlled through output terminal VX of LADC on which a voltage VH' = (Vt)- 2 XV is generated.

The control of the magnitude of the DC line feed current supplied to the telephone line LlO, Lli is performed by synthesizing a predetermined feed resistance, for instance 200 ohms to 20 kilo-ohms, from the 50 ohms feed resistors RO and Ri. This is done by regulating VEET by means of the servo control loop including feed resistors RO, R1, sensing circuit SEN C, low-pass filter LPF1, rectifier AV, feed and drive circuit FDC and the feed inputs VEET of the line operational amplifiers LOAO and LOA1 whose outputs TP and RG are coupled to ROandRi.

SENC provides at its output CO1 a voltage signal which is function of the line current, i.e. of the DC feed current as well as of the speech/metering current flowing through the feed resistors Ro and R1. LPF1 removes the metering signal from the output signal of SENC; AV realises a full wave rectification of the AC signal applied to it; and FDC has a loop stabilising function through its filter and realises a wanted amplification. As shown in Figure 3, it has an input terminal AV which is connected to the output terminal of the rectifier circuit AV, control input terminals FR, FR, BV, BV and CL controlled by the like named control bits, and input terminal VX connected to like named output terminal of LADC on which appears a voltage VH' = (Vt) - AVis already mentioned.Input terminal AV is connected to the non-inverting input of an isolating unity gain operational amplifier OA3 via a filter circuit comprising a series resistor R8 and a shunt capacitor Clothe junction point of R8 and C1 being clamped to V- via diode Di. The purpose of this filter is to stabilise the DC regulating loop of which it forms part and that of OA3 is to isolate capacitor C1 from the rest of the circuit. The output VS of OA3 is connected via a voltage divider comprising resistors R9, R10 to the non-inverting input of an operational amplifier OA4 which serves to establish a predetermined gain G.Thus, the output VA of OA4 is VA G.VS i+R9 RiO The voltage VAG is connected to the inverting input of OA4 through bias resistor R11 and the output of OA4 is coupled to this inverting input via feedback resistor R12 in series with the source-to-drain path of PMOS switch transistor PM1 which is controlled by control bit FR. VAG is also connected to the inverting input of OA4 through bias resistor R13 in series with the source-to-drain path of PMOS transistor PM2 which is controlled by control bit FR and the output of OA4 is also connected to this inverting input via feedback resistors R14 and R1 and PM2 in series, resistor Tri 5 being shunted by the source-to-drain path of PMOS transistor PM3 which is controlled by control bit BV.

Finally, the source to drain path of PMOS switch transistor PM4 which is controlled by control bit CL is connected across the ends of the resistors R11 and R13 which are not connected to VAG.

The output VA of OA4 is connected through resistor Tri 6 to the non-inverting input of an output operational amplifier OA5 to the inverting input of which the output VB of a unity gain operational amplifier OA6 is connected via resistor R17. The values of R16 and R17 are equal e.g. to 30 kilo-ohms. The non-inverting input of OA6 is connected to the reference voltages V1 and V2, with V1 larger than V2, via PMOS switch transistors PM5 and PM6 respectively, the gate electrodes of PM5 and PM6 being controlled by the control bits BV and BV respectively.

The inverting input of OA5 s connected via resistor R18 to output terminal VEET which is constituted by the emitter of PNP transistor T2. Transistor T2 is connected in Darlington configuration with PN P transistor T1 whose base is connected to the output of OA5. The non-inverting input of OA5 is connected to output terminal VX of LADC via resistor R19 having a value equal to that of R18 e.g. 450 kilo-ohms. As mentioned above a voltage VX = (V+) - 2 AVis present at terminal VX. As a consequence the output voltage VEET is substantially equal to VEET = (VA - VB).G1 (V) AV with R18 VB > VA and G1 = R17 Due to the factor - 2 AV, VEET does take into account the DC biasing V of each of the line amplifiers. The last relation may be written as follows, when taking the previous value of VA into account: VEET =(V+)- 2AV - VB.G1 t R9 It Since VEET is the voltage feedback to the line amplifiers a wanted feed resistance may be synthesized from the feed resistors by modifying VEET by means of either one or more of the parameters G, G1 and VB.

More particularly, the gain G of OA4 may be modified under the control of the bits FR, BV and CL, to realise the following resistance values of the feed resistances: - a low resistance value, when FR = 0. G is then equal to 1 + (R12)/R11, as the resistors R11 and R12 are then effectively connected to OA4; - a higher resistance value, when FR = 0 and BV = 0. As the resistors R13 and R14 are then effectively connected to OA4 the gain G is equal to 1 + (R14)/R13 with (R14)/R13 > (R12)/R11; - a still higher resistance value, when FR = 0 and BV = 1, as the resistors R13, R14 and R15 are then effectively connected to OA4.

Furthermore, a current limit condition is realised when CL = 0, due to the resistors R11 and R13 being then connected in parallel.

The feed resistance may also be modified by changing VB in function of the value of the exchange battery which is either at -48 Volts or -60 Volts. This is done under the control of the bit BV. Indeed, depending on BV being 0 (-48 Volts) or 1 (-60 Volts) V1 or V2 appears at the output VB of OA6 and is applied to the inverting input of OA5. This means for instance that for an exchange battery of -48 Volts (BV = 0) VEET is smaller so that a smaller feed resistance is synthesized as required.

FDC also includes means intervening when the synthesized feed resistance is abruptly changed from a high value (FR = 1) to a low value (FR = 0) or vice-versa. Such a change for instance occurs when the telephone handset is hooked off and on respectively. Typical examples of such resistance values are 200 ohms and 20 kilo-ohms. When the feed resistance is high, the gain of OA4 and the value of VEET are both relatively high and the DC current flowing in the line is relatively small so that capacitor C1 is only slightly charged, due to which the output voltage VS of OA3 is relatively small. On the contrary, when the feed resistance is low the gain of OA4 and the value of VEET are both relatively low and the DC current flowing in the line is relatively high.The capacitor C1 is fully charged, so that the output voltage VS of OA3 being then relatively large.

In case the feed resistance is changed from a relatively high value to a relatively low value, the gain G of OA4 is suddenly decreased but the output voltage VS remains low since capacitor C1 cannot immediately follow such a change. As a consequence the value of VEET which is function of G.VS suddenly considerably decreases to a very low value due to which a relatively very high DC current starts flowing in the line. Due to this a considerable voltage jump is produced at the output of the sensing circuit SENC and applied via capacitor C to the impedance synthesis circuit including AS, LAAC, SENC. As a result this synthesis circuit will saturate and therefore temporarily inhibit the transmission of signals by the line amplifiers. An example of such signals are the dial frequency signals.

In case the feed resistance is changed from a relatively low value to a relatively high value, the gain of OA4 is suddenly increased but the output voltage VS remains high since capacitor C1 cannot immediately follow such a charge. As a consequence the value of VEET suddenly considerably increases due to which a relatively very low DC current starts flowing in the line. Because the telephone handset is hooked-on this has no effect. But when the handset is again hooked-off during this transient time it is clear that the voltage jump will then be produced at the output of SENC will be still much larger than in normal circumstances.

For all these reasons and to remove such disturbances, FDC is provided with a correction circuit which includes transistors T3 to T6. The emitter and base of NPN transistor T3 are connected to the terminals A and B of filter resistor R8 and its collector is connected to VAUX. Terminal A of resistor R8 and which also constitutes the junction point of R8 and C1 is connected to VAG via the collector-to-emitter path of NPN transistor T4 and the output VA of OA4 is connected to VAG via the series connection of the emitter-to-collector path of PNP transistor T5, the collector-to-emitter path of diode connected N PN transistor T6 and resistor R20, transistor T6 being connected in current mirror configuration with T4. The base of T5 is connected to the junction point of resistor R21 and R22 of a potentiometer connected in series between VAUX and VAG.

The operation of this circuit is as follows: - when the feed resistance is suddenly changed from a high to a low value by a corresponding decrease of the gain G of OA4, the input signal AV also suddenly increases without the capacitor C1 being normally able to follow this increase. However, when the increase of signal AV reaches a sufficient level transistor T3 becomes conductive so that R8 is then bypassed by the conductive base-to-emitter junction of T3. As a consequence capacitor C1 is then rapidly charged from AV so that VEET is brought back to the wanted value; - when the feed resistance is suddenly changed from a low to a high value by a corresponding increase of the gain, capacitor C1 cannot normally follow the resulting decrease of the input signal AV.By the high gain of OA4 and the high value of VS the output voltage VA of OA4 increases. When this increase reaches a sufficient level transistorT5 becomes conductive and a current flows to VAG via T5, T6 and R20 in series.

This current is reflected in T4 which becomes conductive and discharges capacitor C1.

The switch hook detection circuit SHDC shown in Figure 4 has input terminal AV and control terminals BV and FR which are controlled by the control bits BV and FR respectively. Input terminal AV is connected to the non-inverting input of an operational amplifier OA7 to the inverting input of which reference voltages V3, V4 and V5 are connected via PMOS transistors PM7, PM8 and PM9 respectively. The junction point VS of the source-to-drain path of PMOS transistor PM 1 and resistor R23 is connected to this inverting input via PMOS transistor PM10. R23 is connected in series with resistor R24, and the source electrode of PM11 and the free end of R24 being connected to VAUX and VAG respectively. R24 is shunted by the drain-to-source path of NMOS transistor NM1 whose gate electrode is connected to the output SHD of OA7.The gate electrode of PM 1 is connected to bias terminal B2 and these of PM7 to PM 10 are connected to the outputs SH1 to SH4 of a decoder circuit DEC1 which is adapted to translate a two-bit code constituted by bits BV and FR into a four-bit code constituted by bits SH1 to SH4, according to the following table: BV FR SH1 SH2 SH3 SH4 0 0 1 1 0 1 0 1 0 1 1 1 1 0 1 0 1 1 1 1 1 1 1 0 Because of the bias voltage B2 being continuously applied to PM11, when the SLIC is operative, a constant current then continuously flows from VAUX to VAG via PM11, R23 and R24 so as to establish a reference voltage VS as the like named junction point of PM11 and R23.Depending on the conditions of BV and FR, the transistor among PM7 to PM10 of which the gate electrode is on 0 is conductive. It thus connects its source or threshold voltage V3, V4, V5 or V6 to the inverting input of OA7. When subsequently to the handset having been hooked off in TSS the incoming signal on AV exceeds this threshold, the output of OA7 switches to 1 and thus indicates at its output terminal SHD that the handset has been hooked-off. This bit SHD is stored in the shift register SR. When subsequently to a handset having been hooked on in TSS the incoming voltage decreases below the corresponding threshold level V3, V4 or V5 the bit SHD again becomes 0. This means that in these cases the comparator OA7 works without hysteresis.However, this is not so when the threshold voltage is VS which is equal to the constant current in PM11 multiplied by R23 + R24. Indeed, when the incoming signal becomes larger than this threshold VS and the output SHD of OA7 becomes 1, NM1 is made conductive and thus substantially short-circuits R24. As a consequence the theshold voltage VS is lowered to a value equal to the constant current in PM11 multiplied by R23, so that in order that the output of comparator OA7 should become 0 the incoming signal should decrease below a lower level than the level above which it has to increase to make the comparator output SHD equal to 1. This means that the comparator OA7 then operates with hysteresis.Such a hysteresis is only required when the exchange battery is -48 Volts (BV = 1) and when the feed resistance is high (FR = 1).

The current limiting circuit CLC shown in Figure 5 has an input AV connected to the like named output of the rectifier circuit AV, control input terminals CTO and CTi controlled by bits CTO and CTi and an output terminal CL which is constituted by the output of an operational amplifier OA8. The input terminal AV is connected to the inverting input of OA8 whose non-inverting input is connected to reference voltages V6 to V9 via PMOS transistors PMi2 to PM 5 respectively.The gate electrodes of PMi2 to PM15 are controlled by the outputs S1 to S4 of a decoder circuit DEC2 having the input terminals CTO and CTi to which the bits CTO and CTi are applied respectively. In DEC2 the two-bit code formed by CTO and CTi is translated into a four-bit code comprising bits S1 to S4 according to the following table: CTO CTi S4 53 S2 S1 1 1 1 1 1 1 1 0 1 0 1 1 0 1 1 1 0 1 O 0 1 1 1 0 From this table it follows that depending on the values of CTO and CTi a single one of the outputs S1 to S4 is on 0.The corresponding one among the transistors PM12 to PM15 is then conductive, so that one of the reference voltages V6 to V9 is then applied to the non-inverting input of OA8. When due to too high a line current the output voltage of AV increases above this reference voltage, the output CL of OA8 becomes 0. As already explained in connection with operational amplifier OA4 of FDC (Figure 3) the gain of OA4 is then increased to decrease the line current.

Reference is now made to Figure 6 showing a grounding circuit GRC. This circuit is in fact a voltage converter able to convert the input voltage which is constituted by the general ground in the exchange and is present at terminal GT into an output voltage VAG which has a value between two reference voltages VAUX and V- and in such a way that VAG only follows variations of the general ground at GT and is not influenced by variations of VAUX and VAG. To this end the general ground which is connected to various other circuits of the exchange as indicated by the multipling arrow is connected via a capacitor C2 to the junction point of two equal resistors R25 and R26 which are connected between VAUX and V-. VAUX is equal to V- + 15 Volts and V- is equal to -48 or -60 Volts.As mentioned above, the values of R25 and R26 are for instance 150 kilo-ohms and that of C2 is 220 nano-Farads, so that the junction point is at 7.5 Volts above V-. This junction point is coupled to the output terminal VAG via unity gain amplifier OA9 which is used as an isolation buffer between VAG on the one hand and R25, R26, C2 on the other hand. This latter circuit constitutes a high-pass filter when considered from GT towards VAG and a low-pass filter when considered from VAUX or V- towards GT. Indeed, capacitor C2 blocks DC signals possibly applied via GT so that VAG is decoupled from GTfrom a DC point of view. From an AC viewpoint it follows the variations of GT as is required because in the exchange all signals are referred to this ground. On the other hand spurious AC signals on VAUX or V- do not affect the potential of the junction point of R25 and R26 because they are grounded in GTvia C2.

Claims (18)

1. Atelecommunication line circuit including line amplifiers coupled to respective line conductors of a telecommunication line via feed resistances, a loop current measuring circuit which is coupled with the feed resistances, a resistance synthesis circuit including the loop current measuring circuit whose output is coupled back to inputs of the amplifiers and which includes at least controlled means to adapt to the characteristics of the signals applied thereat, and an impedance synthesis circuit which also includes the loop current measuring circuit whose output is coupled back to inputs of the amplifiers via at least a d.c.

blocking capacitor, characterised in that regulating means (T3-T6) is associated with the controlled means which comprises a controlled amplifier (OA4), a resistance-capacitance low-pass filter (R8, C1) coupling the measuring circuit (SENC, LPF1, AV) to the controlled amplifier (OA4) to effect a change of charge on the capacitance when the gain of the controlled amplifier (OA4) is changed by a predetermined value.

2. A telecommunication line circuit as claimed in claim 1, characterised in that the regulating means (T3-T6) is adapted to detect a predetermined increase of the output signal (VA) and of the controlled amplifier of the filter input signal (AV) which are the result of a change of the gain, and to accordingly give rise to the discharge and charge of the filter capacitance (C1) respectively.

3. A telecommunication line circuit as claimed in claim 2, characterised in that the regulating means (T3-T6) include a first transistor (T3) whose base-to-emitter path is connected across the filter resistance (R8) which is connected to the filter input and whose collector is connected to a fixed DC voltage (VAUX), all in such a way that the first transistor (T3) becomes conductive upon the occurrence of a predetermined increase of input signal (AV).

4. Atelecommunication line circuit as claimed in claim 3, characterised in that the first transistor (T3) is an NPN transistor whose base is connected to the filter input (AV).

5. Atelecommunication line circuit as claimed in claim 3 or 4, characterised in that the regulating means (T3-T6) also include a second transistor (T5) whose base is connected to a fixed bias voltage and whose emitter-to-collector path is coupled via a current mirror circuit (T6) to the base of a third transistor (T4) the collector-to-emitter path of which is connected in parallel with the capacitance (C1 ) all in such a way that the third transistor (T4) becomes conductive upon the occurrence of the predetermined increase of said output signal (VA).

6. A telecommunication line circuit as claimed in any one of the preceding claims, characterised in that the controlled amplifier is a first differential amplifier (OA4) to the non-inverting input of which the filter (R8, Ci) is coupled via at least one buffer (OA3) and whose inverting input is coupled with a controlled resistance switching network (R1 1/15, PM 1/4) used to change the gain of the first amplifier (OA4).

7. A telecommunication line circuit as claimed is claim 6, characterised in that the resistance switching network (R11/15, PM114) includes switching means (PM1/4) controlled by a first control bit (BV), by a second control bit (FR) which is a function of the resistance produced by the resistance synthesis circuit (SEN C, LPF1, AV) and by a third bit (CL) which is a function of the limit value of the line current.

8. A telecommunication line circuit as claimed in any one of the preceding claims, characterised in that the output of the controlled amplifier (OA4) is coupled to the non-inverting input of a second differential amplifier (OA5) whose output (VEET) is coupled on the one hand to a supply input (VEET) of the line amplifiers and on the other hand via a negative feedback resistance to its inverting input, the inverting input being further coupled via another resistance (R19) to a voltage equal to (vet) - 2 XV wherein V+ is connected to another supply input of the line amplifiers and AVis the bias voltage of these amplifiers.

9. A telecommunication line circuit as claimed in claim 8, characterised in that AVis proportional to the envelope (VE) of a metering signal (MS) transmitted by the line amplifiers.

10. A telecommunication line circuit as claimed in claims 8 or 9, characterised in that predetermined voltages (V1,V2) are coupled to the inverting input of the second differential amplifier (OA5) via corresponding switching means (PM5, PM6) controlled by the first bit (BV) and the inverse (BV) thereof.

11. A telecommunication line circuit as claimed in claim 7, characterised in that the output (CO1) of the loop current measuring circuit (SENC, LPF1, AV) is coupled via rectifier means (AV) to the non-inverting input of a third differential amplifier (OA7) whose inverting input is coupled to a plurality of first reference voltages (V3/5, VS) via respective first switches (PM7/10) controlled via via a first decoder means (DEC1) by the first (BV) and second (FR) bits, and that at least one (VS) of the first reference voltages is connected to a tapping point of a potentiometer (R23, R24) of which a resistance (R24) is shunted by a second switch (NMi) controlled by the output of the third amplifier (OA7) indicating the condition of the hookswitch in a subset which is coupled to the line circuit via the telecommunication line.

12. A telecommunication line circuit as claimed in claim 7, characterised in that the output (CO1) of said loop current measuring circuit (SENC, LPF1, AV) is coupled via rectifier means (AV) to the non-inverting input of a fourth differential amplifier (OA8) whose inverting input is coupled to a plurality of second reference voltages (V6/9) via respective third switches (PM 12/15) controlled via a second decoder circuit (DEC2) by current limiting bits (CTO, Cut1 ), the third bit (CL) being provided at the output of the fourth amplifier (OA8).

13. A telecommunication line circuit substantially as described herein with reference to the drawings.

14. A voltage converter with an input and an output and adapted to convert an input voltage at the input into an output voltage at the output, characterised in that it includes two reference voltages (VAUX, V-) connected by corresponding impedances (R25, R26) to a common junction point which is coupled to the output via a buffer (OA9), and filter means (R25, R26, C2) allowing only variations of the input voltage to be followed by the output voltage (VAG) and preventing variations of the reference voltages from having an influence on the output voltage (VAG).

15. A voltage converter as claimed in claim 14, characterised in that the input is connected to the junction point via a capacitance (C2) and the filter means are constituted by the capacitance (C2) and by the impedances which are resistances (R25, R26).

16. A voltage converter as claimed in claim 14 or 15, characterised in that the buffer is a unity gain operational amplifier (OA9).

17. A voltage converter as claimed in claim 14, 15 or 16, characterised in that said input voltage is a general ground in a telecommunication exchange.

18. A voltage converter substantially as described herein with reference to the drawings.