GB2149575A

GB2149575A - Semiconductor device

Info

Publication number: GB2149575A
Application number: GB08428941A
Authority: GB
Inventors: Isao Shimizu
Original assignee: Hitachi Ltd
Current assignee: Hitachi Ltd
Priority date: 1980-12-12
Filing date: 1984-11-15
Publication date: 1985-06-12
Also published as: JPH0133954B2; HK71587A; HK70187A; IT1140324B; MY8700615A; GB2089564A; GB8428941D0; JPS5799771A; GB2149575B; SG36387G; IT8125510A0; DE3148323A1; US4639757A; GB2089564B

Description

1 GB 2 149 575 A 1

SPECIFICATION

Semiconductor device This invention relates to a semiconductor device, and more particularly to a power transistor adapted to a high power semiconductor integrated circuit device (hereinafter referred to as a "power In the power transistor in a power IC for use in 75 an audio output circuit or the like, it is a customary practice to divide an emitter region into a plurality of regions and arrange them in one base region in order to obtain a high output current. In such a power transistor, a ballast resistance is inserted 80 between each emitter region and the single emitter input terminal so that the emitter current flows uniformly through the plurality of divided emitter regions. As a method of forming this ballast resist ance, it is conceivable in principle to form a resist85 ance region with one end continuous with the emitter regions and the other end connected to the emitter input electrode, so as to reduce the occu pation area of the power transistor as a whole, but according to the results of experiments carried out 90 for such a construction by the inventor of the pres ent invention, it was found that the input electrode side of the resistance region and the resistance re gion function as transistors. The transistor formed by the emitter regions of the originally intended transistor and the parasitic transistor due to the re sistance region come to be co-present so that cur rent locally concentrates in the parasitic transistor due to the ballast resistance region, thus breaking down the transistor.

Accordingly, there is a need to improve the breakdown strength and to increase the area of safe operation of a power transistor which uses a part of its emitter regions as a ballast resistance.

According to the present invention there is provided a semiconductor device including a bipolar transistor and a parasitic transistor, said semiconductor device comprising:

a first semiconductor region of a first conductiv- ity type to serve as a collector region of the bipolar 110 and parasitic transistors; a second semiconductor region of a second conductivity type to serve as a base region for the bipolar and parasitic transistors, the second semiconductor region being formed adjacent to the first semiconductor region; and a third semiconductor region of the first conductivity type to serve as an emitter region for the bipolar and parasitic transistors, the third semiconductor region being formed adjacent to the second semiconductor region, wherein the third semiconductor region comprises an operating portion for forming the emitter of the bipolar transistor, and a ballast resistance portion and a terminal portion which form the emitter of the parasitic transistor, and further wherein the impurity concentration of the base region of the parasitic transistor is higher than that of the bipolar transistor base region in the base re- gion portion of said parasitic transistor adjacent to the terminal portion of said third semiconductor layer to reduce the current gain of said parasitic transistor, and wherein the higher impurity concentration base region of the parasitic transistor is in the second semiconductor region and underlies the terminal portion of the emitter but does not underlie the operation portion of the emitter, and wherein the higher impurity concentration base region of the parasitic transistor does not directly contact the first semiconductor region.

The accompanying drawings illustrate some preferred embodiments of the present invention, wherein:- Figure 1 is a plan view showing the power transistor portion of a power IC; Figure 2 is a partial sectional view on the line 11-11 of Figure 1; Figure 3 is an equivalent circuit diagram of the power transistor; Figure 4 is a schematic sectional view useful for explaining the structure of Figure 2; Figure 5 is a sectional view of the power transistor portion in another embodiment of the present invention; and Figures 6A and 6B are sectional views showing the principal steps in fabricating the power transisto r.

Figures 1 and 2 depict the structure of the first embodiment of power transistor. This embodiment illustrates a power transistor formed as a part of a power IC. In Figures 1 and 2, the power transistor is formed in a part of a silicon semiconductor wafer 100 consisting of a P-type substrate 1 and an type epitaxial layer 3 formed on the substrate by epitaxial techniques. The portion (island region) in which the power transistor is to be formed is encompassed by an isolation region 4 and is electrically isolated from other circuit elements not shown that are to be formed on other portions of the semiconductor wafer 100.

The power transistor will be described in further detail in the following paragraphs.

In the epitaxial layer 3 encompassed by a P- isolation region 4, an annular N' diffusion layer 5 is formed, with a deeply extending collector electrode that reaches a buried layer 2. P base regions 6 are formed inside the diffusion layer 5 by known diffusion techniques. As shown in the plan view of Fig- ure 1, four base regions 6 are formed in one island region 3 and adjacent pairs of base regions 6 are encompassed by the abovementioned annular Nregion 5. A pair of upper and lower N- emitter regions 7 is formed in each base region 6, as can be seen clearly from Figure 1.

Each emitter region 7 consists of an emitter portion 7a to perform the main transmitter operation, a resistance portion 7b serving as the ballast resistance and an electrode extension portion 7c with which an aluminum electrode 8 serving as an emitter input terminal comes into contact. The electrode extension portion 7c contacts the electrode 8 through a contact hole 18 in a silicon oxide film 10. As schematically represented by the dot and chain line in Figure 1, this electrode 8 is connected in 2 GB 2 149 575 A 2 common with each emitter region via the contact holes 18, thereby forming the emitter input termi nal. An aluminum emitter electrode 9 is in contact with the emitter portion 7a of the transistor opera tion portion via a contact hole 17. A separate emit ter electrode 9 is provided for each emitter portion, independently of the others. An aluminium base electrode 14 contacts the base region 6 between a pair of emitter regions 6 via a contact hole 16. As schematically represented by the dot and chain line in Figure 1, the base electrode 14 is disposed so as to connect the base contact regions in com mon, thereby forming the base input terminal. The collector 5 contacts on collector electrode 15.

Figure 3 is an equivalent circuit diagram of a 80 transistor formed for one emitter region 7 of the abovementioned power transistor. Symbol Trj represents a transistor formed by the emitter portion 7a and is originally intended while Tr, rep resents an undesirable parasitic transistor which is formed by the electrode extension portion 7c in contact with the emitter electrodes 8 as shown in Figure 2. Symbol R represents a ballast resistance formed by the resistance portion 7b.

Of specific importance here is that the region 6a of the base region 6 below the ballast resistance portion 7b and electrode extension portion 7c is formed so as to protrude downwardly, and the effective base width of the parasitic transistor Tr, is increased in comparison with the width of the other portions. Referring to Figure 4, if the original base width d, is about 1 jim, for instance the width d2 by which the base portion 6a protrudes downwardly may be about 1 jim and this depth of protrusion may be such as to provide a withstand voltage.

As described above, the current gain h,E of the parasitic transistor Tr, can be reduced by increasing its base width. Accordingly, current concentra- tion on that portion during the transistor operation can effectively be prevented and it becomes possible to flow current through the original transistor Tr, Moreover, since the original transistor Tr, has an ordinary base width, its characteristics are not deteriorated. The emitter ballast resistance prevents current concentration in the specific emitter region or regions 7a and the current is uniformly distributed to the emitters of the divided emitter regions. Accordingly, the break-down strength of the transistor as a whole or as a power transistor can be markedly improved and the characteristics of the original transistor can be maintained satisfactorily due to the existence of the expanded base width portion 6a.

This expanded base width portion 6a may be formed longitudinally as a whole with respect to one base region 6 in Figure 1. Alternatively, separate expanded base width portions may be disposed so as to correspond to each emitter region of a pair of transistors formed inside one base region 6. The expanded base width portion 6a may be formed by forming a pregion in advance at a position corresponding to the expanded base width portion 6a by a diffusion technique or an ion-im plantation technique and then performing the base diffusion. This p- region can be formed simultaneously with the formation of a p- region in a lateral PNP transistor or a zener diode else where in the I.C.

Figures 5, 6A and 613 illustrate another embodi ment in accordance with the present invention, in which the same reference numerals are used to identify the same constituents as in the above em bodiment and explanation of such constituents will not be repeated.

In this embodiment, the base width is uniform for both transistors Tr, and Tr,, as shown in Figure 5. However, a P- region 6b of a relatively higher concentration than the other base regions is formed in a part of the base region 6 associated with the parasitic transistor Tr, To improve the collector-to-base withstand voltage, it is preferred that this P- region 6b be disposed to an intermediate depth in the base region 6 so that it does not come into contact with the collector region 3, though it does contact the emitter region 7.

The P. region 6b can be formed in the following manner. First, as shown in Figure 6A, the base region 6 is formed by the diffusion technique and a part of the SiO, film 10 is removed by etching. A P type impurity such as boron ion 12 is then implanted into a region corresponding to the parasitic transistor through the aperture 11 thus defined, in a dose of about 5 x 1013-14CM-2, for example. Next, after forming a window for impurity introduction in the Si02 film 10, an impurity diffusion is effected in order to form the ordinary emitter region 7, as shown in Figure 6B. Simultaneously with the diffusion of this emitter region, the P type impurity in the ion implantation region 13 is pushed below the emitter region 7. Thus, the P- type region 6b which is expanded locally within the base region 6 is formed immediately below the resistance portion 7b and contact portion 7c of the emitter region and around their periphery. This P- type region 6b has a higher concentration than that of the original base region 6 and has a seat resistance of up to 200f1C, for instance, but the resistance is smaller than that of the other base regions.

In the abovementioned manner, if the high concentration region 6b is disposed inside the base region of the parasitic transistor, h,, of the parasitic transistor can be reduced so that the current concentration can be prevented and the breakdown strength can be improved. Since the P- type region 6b does not affect the other base regions, the characteristics of the original transistor are not deteriorated. Further, since P- type region 6b is formed after passing through the albovementined ion implantantation process, its impurity concentration has a higher concentration peak on the side closer to the emitter side than the other base regions. As the result of this, the region 6b contributes to reduce h, of the parasitic transistor.

Though the present invention has thus been described with reference to the preferred embodiments thereof, the embodiments can be further modified on the basis of the technical concept of the present invention. For example, the position, shape and size of each of the expanded base width 3 GB 2 149 575 A 3 portion 6a or the high concentration region may be changed in various manners, as may the methods of forming them. The current gain can also be controlled by increasing the impurity concentration of the expanded portion 6a. Furthermore, another region or regions or means for reducing the current gain may be formed on the base of the parasitic transistor. Additionally, the present invention can be applied to form a PNP transistor by changing the semiconductivity type of each of the abovementioned semiconductor regions.

As described in the foregoing, since current gain is reduced by greater base width or higher impurity concentration of the base region, of the para- sitic transistor it becomes possible to prevent current concentration in the parasitic transistor and to improve the breakdown strength of the transistor as a whole so the transistor can operate in a satisfactory manner without deteriorating the char- acteristics of the originally intended transistor. Thus, it is possible to provide a semiconductor device which is extremely useful especially as a power transistor.

Claims

1. A semiconductor device including a bipolar transistor and a parasitic transistor, said semiconductor device comprising:

a first semiconductor region of a first conductivity type to serve as a collector region of the bipolar and parasitic transistors; a second semiconductor region of a second conductivity type to serve as a base region for the bi- polar and parasitic transistors, the second semiconductor region being formed adjacent to the first semiconductor region; and a third semiconductor region of the first conductivity type to serve as an emitter region for the bi- polar and parasitic transistors, the third semiconductor region being formed adjacent to the second semiconductor region, wherein the third semiconductor region cornprises an operating portion for forming the emitter of the bipolar transistor, and a ballast resistance portion and a terminal portion which form the emitter of the parasitic transistor, and further wherein the impurity concentration of the base region of the parasitic transistor is higher than that of the bi- polar transistor base region in the base region portion of said parasitic transistor adjacent to the terminal portion of said third semiconductor layer to reduce the current gain of said parasitic transistor, and wherein the higher impurity concentration base region of the parasitic transistor is in the second semiconductor region and underlies the terminal portion of the emitter but does not underlie the operation portion of the emitter, and wherein the higher impurity concentration base region of the parasitic transistor does not directly contact the first semiconductor region.

2. A semiconductor device according to claim 1 wherein the third semiconductor region is within the second semiconductor region, and the second semiconductor region is within the first semiconductor region.

Printed in the UK for HMSO, D8818935, 4185, 7102. Published by The Patent Office, 25 Southampton Buildings, London, WC2A lAY, from which copies may be obtained.