GB2149517A - Coupling circuit and associated current measuring devices - Google Patents

Abstract

A coupling circuit for sources of current which each have first and second poles. Each of the first (J1, J2) and second (J0, J3) poles of each of the sources (R6J1J10, R7J2J3) are connected to respective ones of a pair of associated constant current sources (CS1, CS2, CS0, CS3) and also to respective ones of a pair of associated inputs of a linear current combining circuit. The combining circuit produces at its first (PM2, PM3) and second (PM 1, PM4) outputs, first (2I-i1-i2) and second (2I+i1+i2) output currents which are linear functions of the sum of the currents (i1,i2) of the two sources and of the constant currents (I). <IMAGE>

Description

SPECIFICATION Coupling circuit and associated current measuring devices The present invention relates to a coupling circuit for two sources of current each having first and second poles and to a loop current measuring device using such a coupling circuit.

The present invention seeks to provide a coupling circuit of the above type which is particularly, but not exclusively, adapted to be used in such a loop current measuring device.

According to the invention there is provided a coupling circuit for sources of current each having first and second poles wherein the first and second poles of each of the sources are connected to respective ones of a pair of associated constant current sources and to respective ones of a pair of associated inputs of a linear current combining circuit producing at its first and second outputs, first and second output currents which are linear functions of the sum of the currents of the two sources and of the constant currents.

A loop current measuring device using such a coupling circuit is characterised in that it is adapted to measure the current in a loop having two legs each of which is coupled with a circuit to measure the corresponding leg current and to provide a corresponding one of the source currents which are proportional to the leg currents, both the sources of these currents forming part of the coupling circuits.

In this way and by a suitable choice of the above linear functions the output currents of the linear current combining circuit are linear functions of the sum of the leg currents, so that common mode portions of these currents are absent in these output currents. For this reason the present loop current measuring device is particularly useful in a telecommunication line loop where such common mode or longitudinal currents may be induced in the line conductors. A further advantage of this known current measuring device is that its operation is independent of the direction of current flow in the loop.

The present invention also relates to a current measuring device including at least one voltage-tocurrent converter able to convert a voltage across a first impedance incorporated in a conductor of a two-conductor telecommunication line coupled between a line circuit and a station into a current flowing in a corresponding second impedance from a first to a second end.

Such a device is already known from Figure 2 of UK patent application 2,100,949 wherein the voltage-to-current converter comprises an operational amplifier whose non-inverting input is connected to a second end of the first impedance which is constituted by a first resistance and whose output is connected to the base electrode of a PNP transistor. The collector electrode of this transistor is connected to the second impedance which is constituted by a second resistance and the inverting input of the amplifier is connected to the junction point of the emitter electrode of the PNP transistor and a third resistance which is connected to the first end of the first resistance. A drawback of the known device is that it is relatively inaccurate because current is drawn from the first end of the first resistance and because the base current of the transistor is not negligible.Moreover it is only able to measure the current flowing from the first to the second ends of the first resistance.

The present invention may provide a current measuring device of the above type, but which does not present these drawbacks.

According to this aspect of the present invention there is provided a current measuring device including a voltage to current converter able to convert a voltage across a first impedance incorporated in a conductor of a two-conductor telecommunication line coupled between a line circuit and a station into a current flowing in a corresponding second impedance from a first to a second end which includes first and second operational amplifiers whose non-inverting inputs are coupled to first and second ends of the first impedance, whose inverting inputs are interconnected through the second impedance and whose outputs are connected to the gate electrodes of respective first and second MOS transistors the source-todrain paths of which are connected between the first and second ends of the second impedance and a respective first and second converter output, the first and second ends being each connected to a constant current source.

Due to the high input impedance of the operational amplifier and the negligible gate current of the MOS transistor the voltage across the first impedance is accurately converted in a current in the second impedance.

In order that the invention and its various other preferred features may be understood more easily, some embodiments thereof will now be described, by way of example only with reference to the drawings, in which: Figure 1 is a schematic block diagram of telephone circuitry including current measuring devices SENC and ILCSC constructed in accordance with the invention, SENC using a coupling circuit in accordance with the invention, Figure 2 is a schematic block diagram of the current measuring device SENC of Figure 1, and Figure 3 is a schematic block diagram of the current measuring device ILCSC of Figure 1.

The telephone circuitry shown in Figure 1 includes a line circuit LC which is connected in cascade with a switch circuit HVC between a telephone line with conductors LIO and Ll1, connected to a telephone subset TSS, and a telephone switching network SNW, Line circuit LC includes the cascade connection of a subscriber line interface circuit SLIC, a digital signal processor DSP, a transcoder and filter circuit TCF and a dual processor terminal controller DPTC.

Telephone subset TSS includes a normally open hook switch HS connected between the line conductors LIO and Ll1, and schematically represented switching means S1 and S2 to connect one or both conductors to a voltage V+.

The switch circuit HVC is for instance of the type disclosed in Belgian patent No. 897 772 filed on September 19, 1983 and entitled "Contacts electroniques et dispositifs associes". It includes 4 pairs of switch contacts sw00, swOl to sw30, sw31 and has line terminals LO and L1 connected to line conductors Llo and Ll1 respectively, test terminals TO and T1 connected to a test circuit TC, ringing terminals RGO and RG1 connected to a ringing circuit RC, and terminals TP, RG and STA, STB, SRA, SRB connected to the like named terminals of the SLIC. In HVC the line terminals LO and L1 are connected to TP and RG via the series connection of swOO, a 50 ohms line feed resistor RO and swlO and swOl, a 50 ohm line feed resistor RI and swill respectively.The respective junction points STB and SRA of swOO and RO and of swOl and R1 are connected to TC via sw20 and sw21 respectively, whilst the respective junction points STA and SRB of RO and sw10 and of R1 and swill are connected to RC via sw30 and sw31 respectively. Switch contacts swOO, swOl, sw10 and swill are normally closed, whereas the other switch contacts are normally open. These switch contacts are controlled by the SLIC so that HVC is able to establish a connection between TSS, on the one hand, and SLIC, TC or RC on the other hand, as well as between TC and SLIC. The function of TC is to test the line to TSS and to the SLIC and that of RC is to apply a ringing signal to this line.

The subscriber line interface circuit SLIC is a two-terminal circuit on the side of the subscriber subset TSS and is a four-wire one towards SNW. It has a speech receiving input terminal Rx (with ground return) and a speech transmitting output Tx (again with ground return), Rx and Tx being connected to the digital signal processor DSP. The SLIC includes line operational amplifiers LOAo and LOA1 with inputs TDC, TAC, RDC, RAC and outputs connected to the above terminals TP and RG of the switch circuit HVC, a loop current measuring or sensing circuit SENC having input terminals STA, STB, SRA, SRB connected to the like named terminals of HVC and output terminals JO to J3 connected to an individual line conductor current measuring or sensing circuit ILCSC with output VPA.

The DSP is able to convert a digital speech signal received from the transcoder and filter circuit TCF into an analog version at speech input terminal Rx of the SLIC. Conversely a speed signal at speech output terminal Tx is converted into a digital version which is supplied to TCF. The DSP also includes a two wire/four wire converter.

The TCF is able to perform a transcoding operation on digital signals received from the DSP and from the dual processor terminal controller DPTC and is also adapted to supply a metering signal to the SLIC, as described in Belgian patent applications No. 2 60207 (Patent No. 897 771) and No. 2 60209 (Patent No. 897 773) both filed on September 19, 1983.

Finally, the DPTC is able to realise the generai control of the SLIC.

The current measuring circuits SENC and ILCSC which will now be described in detail operate with the following supply voltages V+ which is at ground potential; V- which is equal to -48 or -60 Volts; VAUX which is an auxiliary voltage 15 Volts above V-; VAG which is a voltage 7.5 Volts above V-; B1 which is a bias voltage provided by a constant current source and ensuring the flow of a constant current in the transistor to which it is ap plied; V1 which is a further supply voltage.

The ILCSC is further controlled by the following control signals which are received from DSP BRO : a polarity reversal bit to indicate that the polarity on TP is high (1) or low (0), BR1: a polarity reversal bit to indicate that the polarity on RG is high (1) or low (0).

More particularly, a polarity reversal circuit forming part of the SLIC is able to connect a high voltage close to V or a low voltage close to V- to TP or to RG depending on the value of the bits BRO and BR1 received and the ILCSC may also operate when BRO and BR1 are both 1. This polarity reversal circuit is described in the Belgian patent application filed together with the present Belgian patent application entitled "Telecommunication line circuit and associated polarity reversal circuit" (Patent No. 898 051).

First reference is made to Figure 2 which shows circuit SENC able to measure the current in the loop comprising line conductors LIO and Lil and subset TSS. The terminals SRA, SRB and STA, STB of the SENC shown are coupled to the inputs SC1, SCO and SC2, SC3 of two identical voltage-to-current converters via respective protection resistors R4, R5, R2, R3 and conductors which are each clamped between the voltages V and V- corresponding protecting diodes D1, D2; D3, D4; D5, D6; and D7, D8 respectively. Each of these converters is of the type disclosed in the Belgian patent No. 898 052 of the same date entitled "Voltage-tocurrent converter and impedance synthesis circuit using same".Each of these converters comprises a corresponding pair of operational amplifiers OA 1/2 and OA 3/4, a corresponding pair of PMOS transistors PM 1/2 and PM 3/4 and a corresponding pair of constant current sources CSOl1 and CS2/3. The converter inputs SCO/3 are constituted by the noninverting inputs of OA1i4 whose inverting inputs are connected to the source electrodes of PMOS transistors PM 1/4. The outputs of OA 1/4 are connected to the gate electrodes PM 1/4. The inverting inputs JO and J1 of OA1 and OA2 are interconnected by resistor R6 and V+ is connected to these inputs via constant current sources CSO and CS1 respectively. Similarly, the inverting inputs J2 and J3 of OA3 and OA4 are interconnected by resistor R7 and V+ is connected to them via constant current sources CS2 and CS3. The drain electrodes of PM1 and PM4 are commoned and further connected to V- via a diode connected NPN transistor TO which is coupled in current mirror configuration with NPN transistor T1 whose collector-to-em itter path is connected between the inverting input of an operational amplifier OA5 and V-. Likewise, the drain electrodes of PM2 and PM3 are commoned and connected to V- via a diode connected NPN transistor T2 which is coupled in current mirror configuration with NPN transistor T3 whose collector-to-emitter path is connected between the non-inverting input of OA5 and V-. The latter noninverting input is also connected to VAG via bias resistor R8. The output of amplifier OA5 is connected on the one hand to the inverting amplifier input via feedback resistor R9 and on the other hand to output terminal C01 through resistor R10.

The operation of the circuit SENC is as follows, it being supposed that a loop current flows in the line loop from TP to RG via HS in TSS and that a longitudinal or common mode current flowing towards the SLIC is superposed on this loop current.

To be noted however that the operation of SENC is independent of the flow direction of the loop or common mode current.

Due to the presence of the operational amplifiers OAl to OA4 which have a high input impedance, the voltages present at the sense terminals SRA, SRB and STA, STB of the feed resistors R1 and RO are also present at the inputs J1, JO and J2, J3 of the voltage-to-current converters just described. As a consequence a current ii = i + i', wherein i and are proportional to the above mentioned loop current and longitudinal current respectively, flows in resistor R6 from J1 to JO, R6 being much larger than R1. Because the constant current sources CSO and CS1 provide a same current I and the gate currents of PM1 and PM2 are negligible, the currents flowing in the drain electrodes of these transistors are equal to I + il and I-il respectively.The same is true for the current i2 i-i' flowing through R7 which is much larger than RO so that currents l-i2 and l+i2 flow in the drain electrode of PM3 and PM4 respectively.

The drain electrodes of PM 1/4 are connected to a first linear current combining circuit wherein the drain electrodes of PM1 and PM4 as well as those of PM2 and PM3 are interconnected. Thus the output currents of this combining circuit are linear functions of the constant current I and the sum 1 + i2, i.e. 21 + i + 2 and 21-i,-i2 or 21 + 2i and 21 - 2i so that the common mode currents i' are absent in these output currents.

To eliminate the constant current I from these output currents use is made of a second linear current combining circuit comprising transistors TO/3 and amplifier OA5. Indeed, the last mentioned output currents 21 + 2i and 21 - 2i are mirrored via transistors TO and T2 in the transistors T1 and T3 so that currents 21 + 2i and 21 - 2i are derived from the inverting and non-inverting inputs of the summing amplifier OA5 respectively. As a consequence the output voltage of OA5 is directly proportional to the current i only and therefore only to the loop current. The latter has thus been accurately measured by the measuring circuit SENC.

Also, this measurement is independent of the direction of current flow in the loop.

To measure the current in a line conductor Llo or Ll1 one could use a voltage-to-current converter of the type described above and connect it in the same way across the corresponding feed resistor RO or R1. However, in this case additional protec ticn resistors and diodes, comparable to R2/5 and Di/8 would be required. For this reason the ILCSC is coupled with the resistors R6 and R7 so that it is protected by the same elements as the SENC.

Principally referring to Figure 3, the input terminals JO to J3 of ILCSC (Figure 3) are connected to the like named terminals of SENC (Figure 2). The input terminals JO and J1 constitute the inputs of a circuit C1 and the same is true for J2 and J3 with respect to a circuit C2 which is identical to Cl and which is therefore not shown in detail. The outputs of these circuits C1 and C2 are connected via respective diodes D17 and D18, constituting a wired OR-gate, and a common resistor R11 to VAG. A reference voltage V1 is also connected to VAG via diode D19 and resistor R12 in series.The non-inverting input of an operational amplifier OAE operating as a comparator is connected to the junction point of D17, D18 and R11 and its inverting input is connected to the junction point of D19 and R12. The output of OA6 is connected to the gate electrode of NMOS transistor NM1 whose source electrode is connected to V- and to the drain electrode of which VAUX is connected via the series connection of the source-to-drain and drain-to-source paths of PMOS transistor PM5 and NMOS transistors NM2 and NM3 respectively.The gate electrode of PM5 is controlled by the above mentioned bias voltage B1 so that a constant current flows through this transistor, whilst the gate electrodes of NM2 and NM3 are controlled by the above mentioned bits BRO and BR1 respectively. The junction point of PM5 and NM2 constitutes the output terminal VPA of the circuit ILCSC.

In the circuit C1 the high ohmic input terminals JO and J1 are connected to the gate electrodes of PMOS transistors PM6 and PM7 so that the circuit C1 does not constitute a load for SENC. The source electrodes of PM6 and PM7 are interconnected by resistor R13 and VAUX is connected to V- via the source to-drain paths of PMOS transistors PM8 and PM9, the source-to-drain path of a respective one of PM6 and PM7 and the drain-to-source path of a respective one of diode-connected NMOS transisotrs NM4 and NM5. Because the gate electrodes of PM8 and PM9 are controlled by the above bias voltage B1 they constitute constant current sources providing equal constant drain currents, say 11. The transistors NM4 and NM5 are connected in current mirror configuration with NMOS transistor NM6 and NM7 respectively. The inverting and non-inverting inputs of an operational amplifier OA7 with feedback resistor R14 are connected to V- via the drain-to-source paths of NM6 and NM7 respectively, this non-inverting input being moreover biased to VAG through resistor R15.

The operation of the ILCSC is described hereinafter.

When either BRO or BR1 is at 0, NM2 or NM3 is blocked. VPA is then at 1 because VAUX is then connected to VPA via the conductive PM5. On the contrary, when both BRO and BR1 are at 1, VAUX is connected to the drain electrode of NM1 which may therefore become conductive when a suitable voltage is applied to its gate electrode, VPA is then connected to V- so that a signal VPA = 0 appears thereon. Due to both BRO and BR1 being 1 a polar ity reversal circuit in the SLIC also connects a low voltage close to V- to the conductors LID and Ll1.

It is supposed that in TSS, the voltage V+ is ap plied to line conductor Ll1 via the switch S2 so that current flows through R1 from SRA to SRB (Figure 1). As a consequence the voltage at J1 is higher than that at JO so that the drain current of PM7 is lower that that of PM6. Because PM8 and PM9 supply a same current 11 to PM6 and PM7 a difference current, say i3 flows through R13 from left to right. The source currents of PM6 and PM7 are therefore equal to il + i3 and 11 - i3 respectively.

To eliminate 11 the last mentioned currents are combined. More particularly, they are mirrored and inverted by NM4, NM6 and NM5, NM7 so that the current 11 + i3 flows from the output of OA7 to Vvia R14 whilst the current ll-i3 flows from VAG to V-via R15. Thus, the effect of 11 is eliminated and the output voltage of OA7 is proportional to i3.

When this voltage is sufficiently high diode D17 becomes conductive and a current flows from OA7 to VAG via D17 and resistor R11 and develops therein a voltage which is applied to the non-inverting input of OA6. When this voltage overcomes that applied to the inverting input of OA6 the output thereof becomes 1. Due to this NM1 becomes conductive as a consequence of which VPA becomes 0.

Due to the presence of the diodes D17 and D19 the comparator OA6 compares the output voltage of OA7 less the voltage across D17 with V1 less the voltage across D19 which is equal to that across D17. Because the diodes D17 and D18 are connected in a wired-OR configuration the highest one of the output signals of Cl and C2 will be applied to OA6.

Claims (17)

1. A coupling circuit for sources of current each having first and second poles, characterised in that the first (J1, J2) and second (JO, J3) poles of each of the sources (R6J1JO, R7J2J3) are connected to respective ones of a pair of associated constant current sources (CS1, CS2, CSO, CS3) and to respective ones of a pair of associated inputs of a linear current combining circuit producing at its first (PM2, PM3) and second (cm1, PM4) outputs, first (21 -1l - i2) and second (21+i1+i2) output currents which are linear functions of the sum of the currents (il, i2) of the two sources and of the constant currents (I).

2. A coupling circuit as claimed in claim 1, characterised in that the first (PM2, PM3) and second (PM1, PM4) outputs of the linear current combining circuit are connected to respective inputs of a second linear current combining circuit (TD/3, OA5) producing at its output (C01) a third linear function of the sum of currents (i1 + i2) only.

3. A coupling circuit as claimed in claim 1 or 2, characterised in that the values of the currents of the constant current sources are equal (I).

4. A coupling circuit as claimed in claims 1, 2 or 3, characterised in that said first and second linear functions are equal to 21-(il +i2) and 21+(il tri2) wherein I is the constant current and il and i2 are the source currents.

5. A coupling circuit substantially as described herein with reference to the drawings.

6. A loop current measuring device using a coupling circuit as claimed in any qne of claims 1 to 5, characterised in that it is adapted to meausre the current in a loop having two legs (LIO, Ll1) each of which is coupled with a circuit to measure the corresponding leg current and to provide a corresponding one of the source currents which are proportional to the leg currents, both the sources of these currents forming part of the coupling circuit.

7. A loop current measuring device as claimed in claim 6, characterised in that each of the legs incorporates a first impedance (R1, RO) through which the corresponding leg current flows and that the measuring circuit comprises a voltage-to-current converter (OA1/2, OA3/4) for converting the voltage across the first impedance (R1, RO) into the corresponding source current flowing in a corresponding second impedance (R6, R7) having the first (J1, J2) and second (Jo, J3) poles and from the first to the second pole.

8. A loop current measuring device as claimed in claim 7, characterised in that the converter includes first (OA2, OA3) and second (OAl, OA4) operational amplifiers whose non-inverting inputs (SC1, SCO; SC2, SC3) are connected to respective ends (SRA, SRB;STA, STB) of the first impedance (R1, RO), whose inverting inputs are interconnected by said second impedance (R6, R7) and whose outputs are connected to the gate electrodes of respective first (PM2, PM3) and second (PM1, PM4) MOS transistors the source-to-drain paths of which are connected between respective ones of the first (J1, J2) and second (JO, J2) poles and respective first (PM2, PM3) and second (PM1, PM4) inputs of the associated pair of inputs of the first linear current combining circuit.

9. A loop current measuring device as claimed in claim 8, characterised in that, in the first linear current combining circuit, the first (PM2, PM3) and second (PM1, PM4) inputs of each of the associated pairs of inputs are connected to first and second outputs of this circuit respectively so as to produce thereon the first (21-il-i2) and second (21+it +i2) linear functions respectively.

10. A loop current measuring device as claimed in claim 9, characterised in that the outputs of the first linear current combining circuit are coupled to the inputs of a summing operational amplifier (OA5) constituting said second linear current combining circuit.

11. A loop current measuring device as claimed in claim 10, characterised in that the first and second outputs of the first linear current combining circuit are coupled to the summing operational amplifier (OA5) via corresponding current mirror circuits (T2, T3; TO, T1).

12. A loop current measuring device as claimed in any one of claims 6 to 11, characterised in that the loop is a telecommunication line loop whose conductors constitute the legs.

13. A current measuring device including at least one voltage-to-current converter able to convert a voltage across a first impedance incorporated in a conductor of a two-conductor telecommunication line coupled between a line circuit and a station into a current flowing in a corresponding second impedance from a first to a second end, characterised in that the converter includes first (OA2, OAl) and second (OA3, OA4) operational amplifiers whose non-inverting inputs (SC1, SCO;; SC2, SC3) are coupled to first (SRA, STA) and second (SRB, STB) ends of the first impedance (R1, RO), whose inverting inputs are interconnected through the second impedance (R6, R7) and whose outputs are connected to the gate electrodes of respective first (PM2, PM3) and second (PM1, PM4) MOS transistors the source-todrain paths of which are connected between the first (J1, J2) and second (JO, J3) ends of the second impedance (R6, R7) and a respective first (PM2, PM3) and second (PM1, PM4) converter output, the first (J1, J2) and second (JO, J3) ends being each connected to a constant current source (CSl, CS2; CSO, CS3).

14. Current measuring device as claimed in claim 13, characterised in that it includes two of the converters which are coupled to corresponding first impedances (R1, RO) incorporated in corresponding conductors of the telecommunication line, and that the first and second outputs of the converters are coupled to first and second inputs of a first summing amplifier (OA5) respectively.

15. A current measuring device as claimed in claim 13, characterised in that the first (J1) and second (JO) ends of the second impedance (R6) included in the converter are connected to the gate electrodes of third (PM7) and fourth (PM6) transistors forming part of a second voltage-to-current converter and having source-to-drain paths connected between first and second ends of a third impedance (R13) and corresponding first and second outputs of the second converter, the first and second ends of the third impedance (R13) being connected to respective constant current sources (PM8, PM9) and being coupled to first and second inputs of a second summing amplifier (OA7).

16. A current measuring device as claimed in claim 15, characterised in that the station (TSS) and the line circuit (SLIC) include means to connect first (Vt) and second (VL) DC voltages to corresponding ends of the conductor.

17. A current measuring device substantially as described herein with reference to the drawings.

17. A current measuring device as claimed in claim 14 or 16, characterised in that the first mentioned converters are coupled to corresponding second converters and that the outputs of the second summing amplifiers (OA7) thereof are connected through an OR-gate to one input of a comparator operational amplifier (OA6) whose other input is coupled to a third DC voltage (V1) and those output is connected to a signal output (VPA) via gating means (NM1/3) which are also controlled by signals indicating that said second DC voltages (VL) have been connected in said line circuit).