GB2146147B - Microprocessor - Google Patents

Microprocessor

Info

Publication number
GB2146147B
GB2146147B GB8408830A GB8408830A GB2146147B GB 2146147 B GB2146147 B GB 2146147B GB 8408830 A GB8408830 A GB 8408830A GB 8408830 A GB8408830 A GB 8408830A GB 2146147 B GB2146147 B GB 2146147B
Authority
GB
United Kingdom
Prior art keywords
information
register
bus
microprocessor system
alu
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB8408830A
Other versions
GB2146147A (en
GB8408830D0 (en
Inventor
Yeshayahu Mor
Gary R Burke
Allan M Schiffmann
Dan Wilnai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fairchild Semiconductor Corp
Original Assignee
Fairchild Camera and Instrument Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fairchild Camera and Instrument Corp filed Critical Fairchild Camera and Instrument Corp
Publication of GB8408830D0 publication Critical patent/GB8408830D0/en
Publication of GB2146147A publication Critical patent/GB2146147A/en
Application granted granted Critical
Publication of GB2146147B publication Critical patent/GB2146147B/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30032—Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/2236—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • G06F13/364—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control using independent requests or grants, e.g. using separated request and grant lines
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7828—Architectures of general purpose stored program computers comprising a single central processing unit without memory
    • G06F15/7832—Architectures of general purpose stored program computers comprising a single central processing unit without memory on one IC chip (single chip microprocessors)
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/3001—Arithmetic instructions
    • G06F9/30014—Arithmetic instructions with variable precision
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30101—Special purpose registers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30105—Register structure
    • G06F9/30109—Register structure having multiple operands in a single register
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/72—Indexing scheme relating to groups G06F7/72 - G06F7/729
    • G06F2207/7219—Countermeasures against side channel or fault attacks

Abstract

A microprocessor system has a central processing unit which includes an independent address data path 106 and an independent arithmetic logic unit (ALU) data path 104. Each. is capable of simultaneous operation during a clock cycle. The data paths have a shared input multiplexer 116 connected to receive information from an information bus 102. A shared bus register 120 is connected to receive the information from the input multiplexer, and the shared output multiplexer 158 is connected to receive information from the bus register and other units in the data paths to supply the information to the information bus. The ALU data path has a register file 166 incorporating at least one bi-directional shift register linked to another register in the register file. An internal counter 162 forms a portion of the ALU data path and supplies information both to the register file and to the ALU 110. The bus register is split into at least two one-byte registers to allow fast execution of byte instructions. A control unit 200 for the microprocessor system includes a programmable logic array (PLA) 206 having at least one routine for testing operation of the microprocessor system, together with a control line connected to a console of a system including the microprocessor system, to allow the user to initiate system tests from the console. Data and programs in the microprocessor system are protected against access or modification by an unauthorized user through an ABORT function. <IMAGE>
GB8408830A 1980-05-30 1984-04-05 Microprocessor Expired GB2146147B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15514180A 1980-05-30 1980-05-30
US15583180A 1980-05-30 1980-05-30

Publications (3)

Publication Number Publication Date
GB8408830D0 GB8408830D0 (en) 1984-05-16
GB2146147A GB2146147A (en) 1985-04-11
GB2146147B true GB2146147B (en) 1985-09-25

Family

ID=26852042

Family Applications (3)

Application Number Title Priority Date Filing Date
GB8115281A Expired GB2077009B (en) 1980-05-30 1981-05-19 Microprocessor
GB8408829A Expired GB2146146B (en) 1980-05-30 1984-04-05 Microprocessor
GB8408830A Expired GB2146147B (en) 1980-05-30 1984-04-05 Microprocessor

Family Applications Before (2)

Application Number Title Priority Date Filing Date
GB8115281A Expired GB2077009B (en) 1980-05-30 1981-05-19 Microprocessor
GB8408829A Expired GB2146146B (en) 1980-05-30 1984-04-05 Microprocessor

Country Status (1)

Country Link
GB (3) GB2077009B (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4482953A (en) * 1980-05-30 1984-11-13 Fairchild Camera & Instrument Corporation Computer with console addressable PLA storing control microcode and microinstructions for self-test of internal registers and ALU
US4996661A (en) * 1988-10-05 1991-02-26 United Technologies Corporation Single chip complex floating point numeric processor
GB9419246D0 (en) * 1994-09-23 1994-11-09 Cambridge Consultants Data processing circuits and interfaces

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3389380A (en) * 1965-10-05 1968-06-18 Sperry Rand Corp Signal responsive apparatus
GB1218656A (en) * 1968-03-27 1971-01-06 Int Computers Ltd Improvements in or relating to computer system
DE2222195A1 (en) * 1972-05-05 1973-11-22 Siemens Ag ARRANGEMENT FOR PROCESSING OPERANDS OF PROGRAMS
US3828316A (en) * 1973-05-30 1974-08-06 Sperry Rand Corp Character addressing in a word oriented computer system
DE2348196B2 (en) * 1973-09-25 1977-08-04 Siemens AG, 1000 Berlin und 8000 München CIRCUIT ARRANGEMENT AND PROCEDURE FOR BYTE SELECTION IN A SEMICONDUCTOR MEMORY
US4363091A (en) * 1978-01-31 1982-12-07 Intel Corporation Extended address, single and multiple bit microprocessor

Also Published As

Publication number Publication date
GB2077009A (en) 1981-12-09
GB2146146B (en) 1985-09-11
GB8408829D0 (en) 1984-05-16
GB2146147A (en) 1985-04-11
GB2146146A (en) 1985-04-11
GB2077009B (en) 1985-04-17
GB8408830D0 (en) 1984-05-16

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Legal Events

Date Code Title Description
PCNP Patent ceased through non-payment of renewal fee