GB2144580A - Interconnection system for integrated circuits - Google Patents

Abstract

A high-density integrated circuit employing insulated gate field effect transistors comprises at least three stacked wiring layers, the lowest layer being formed of polycrystalline silicon and including silicon gates of the transistors, one of the upper layers being formed of doped polycrystalline silicon (211) and used for feeding a power supply to some of the transistors being connected to at least one region (220) in which transistors are formed and making with that region a leaky PN junction, and the other of the upper layers (209, 210) being formed of high conductivity metal. <IMAGE>

Description

SPECIFICATION Improvements in or relating to integrated circuits This invention relates to integrated circuits.

CMOS circuits have been widely used because of their low power consumption, in which P type and N type field effect transistors are employed. In general, a CMOS circuit arrangement is formed on a semiconductor substrate of a first conductivity type provided with well regions of a second conductivity type, opposite to the first conductivity type, formed therein in order to arrange both P and N channel transistors on the same semiconductor chip. In this arrangement, it is required to provide the substrate and the well region with ohmic contacts for potential sources (Vcc potential and Vss potential).

In a CMOS circuit, however, as is well known, a current triggered by an external noise voltage or the like flows through the substrate or the well region, and a voltage drop due to this current acts as a dominant factor in deciding the degree of occurrence of a parasitic thyristor effect, a so-called latch-up phenomenon caused in the CMOS structure.

Accordingly, methods for preventing occurrence of this latch-up phenomenon have been devised such that a part of the well region or the substrate is made a low resistance layer by increasing the impurity concentration thereof, or the supplying of potential for the well region or the substrate is effected by performing the connection with a metal having a low sheet-resistance such as aluminium with a width as large as possible in layout.

However, with the recent increases in the memory capacity and in the density of semiconductor memory circuit arrangements, it has been necessary to employ fine patterning techniques and/or bi-layers or stacked layers of polycrystalline silicon structures and the like. The above situation is also the same for CMOS memory circuit arrangements, and particularly according to the layout of the group of memory cells, an extensive variation of chip size is caused. That is, although the mask pattern used for fabricating the circuit arrangement is subject to fine patterning, the contact area between a power source wiring and the well region or the substrate cannot be simply reduced in view of the latch-up phenomenon.In addition, in the bi-layer polycrystalline silicon structure, where the upper polycrystalline silicon layer containing N type impurities is used as wiring for supplying the Vss power source, a direct ohmic electrical connection of the N-type layer to a P-type well region or a P-type substrate is impossible, so that it is necessary that the N-type polycrystalline silicon layer is connected with a metal such as aluminium, which is in turn connected with the P type well or the P type substrate.As a result, although the bi-layer polycrystalline silicon structure is incorporated for the purpose of effecting a high density of integration, the expected high density cannot be attained in a specified pattern, for instance a group of memory cells, because of the above mentioned indirect connection between the power source wiring and the well the bilayer polycrystalline silicon structure is incorporated for the purpose of effecting a high density of integration, the expected high density cannot be attained in a specified pattern, for instance, a group of memory cells because of the above mentioned indirect connection between the power source wiring and the well region or the substrate.

It is an object of the present invention to provide an integrated circuit having a highdensity of circuit structure, which may be a semiconductor memory device provided with a large memory capacity.

The circuit may be a CMOS circuit having a high integration and operable without causing latch-up phenomena due to stray thyristor effect, suitably a CMOS type semiconductor memory device of a high-density and operable with a low power consumption.

According to the invention there is provided an integrated circuit device comprising a semiconductor region of one conductivity type, at least one insulated gate field effect transistor formed in said semiconductor region and having source and drain regions of the opposite conductivity type, and a wiring layer made of polycrystalline silicon doped with impurities of said opposite conductivity type and having a first portion connected to one of said source and drain regions of said transistor with an ohmic contact and a second portion connected to said semiconductor region with a leaky P-N junction formed between said wiring layer and said semiconductor region.

In embodiments of the invention, the polycrystalline silicon forming the uppermost of the two upper layers is doped with an impurity of the first conductivity type so that good ohmic contact is obtained between an impurity region formed in the impurity-doped region and the polycrystalline silicon. This polycrystalline silicon as the one of upper layer is connected to the impurity doped region through a PN junction biased in the reverse-direction formed therebetween, and hence it may be conceived that the impuritydoped region cannot be biased by the power supply through the reverse-direction PN junction, according to the prima-facie concept of the skilled in the art.However, such PN junction is favorably formed by contacting the highly doped polycrystalline silicon and the highly doped contact region in the impurity doped region, and hence the PN junction is very leaky, like a resistor. Therefore, the impurity-doped region can be well biased by the leakage current of the PN junction so that the latch-up phenomena may be effectively prevented.

It is possible to obtain a CMOS memory circuit arrangement in which a polycrystalline silicon used for a power source wiring and a well region or a substrate, which contains impurity of conductivity type opposite to that contained in the polycrystalline silicon, are connected with each other in a junction state under the notice that the latch-up phenomenon is comparatively hardly caused in the memory cell matrix.

The invention will now be described, by way of example, with reference to the accompanying drawings, in which: Figure 1 is a circuit diagram illustrating a memory cell of CMOS static RAM; Figure 2 is a plan view showing a conventional layout of a part of a memory cell matrix; Figure 3 is a plan view showing a part of a memory matrix according to one embodiment of the present invention; Figure 4 is a cross sectional view corresponding to a line a-a' of Fig. 4; Figures 5A to 5C are plan views respectively showing detailed layout patterns of Fig.

1; and Figures 6A to 6D are plan views respectively showing detailed layout patterns.

First, with reference to Fig. 1, a general circuit structure of a CMOS type memory cell will be briefly explained.

In Fig. 1, a memory cell is composed of Nchannel field effect transistors Q, to (14 and Pchannel field effect transistors Q5 and Q6. The transistors Q3 and Q5 form a first inverter while the transistors Q4 and Q6 form a second inverter. An output of the first inverter and an input of the second inverter are commonly connected at a node N,. An output of the second inverter and an input of the first inverter are commonly connected at a node N2.The transistors Qi and Q2 respectively connected between a true digit line D and the node N, and between a complement digit line D and the node N2 operate as transfer gate in response to a logic level of a word line WL In the following, the present invention will be explained by referring to accompanied drawings in comparison with the conventional technique, for example, in the situation where the Vss power wiring is formed of the polycrystalline silicon doped with the N type impurity and the substrate is of N type as well as the well region is of P type.

Fig. 2 shows a conventional layout of a memory cell matrix with respect to two memory cells A and B neighboring with each other. In this layout, one word line is formed of a laterally extended polycrystalline silicon 107. Portions 101 and 102 of the polycrystalline silicon 107 act as gates of the transfer gate transistors Q, and Q2 in Fig. 1 for the memory cell A. Similarly, portions 103 and 104 of another word line 108 act as gates of the transfer gate transistors in the memory cell B. Layouts of flip-flop circuits formed of the mentioned first and second inverters in the cells A and B are indicated by reference numerals 105 and 106 respectively. A true and complement digit lines D and D are formed of alminium wirings 109 and 110 respectively. Next, a V55 power wiring is formed of alminium wiring 111.A high impurity-concentration P type diffusion region 112 is employed for electrically connecting the P type well regions 120 with the V55 power wiring 111 through an opening provided on which region an ohmic contact is effected with the V55 power wiring 111.

In the above conventional layout, it is impossible to reduce the pattern size of the memory elements because of the limit of space in the aluminum wirings of the V55 power wiring 111 and the digit lines 109 and 110. For removing this difficulty, it may be thought that the bilayer polycrystalline silicon structure is incorporated to the memory matrix and the upper layer of polycrystalline silicon of which is used for the V55 power wiring.

However, it has been conventionally regarded as impossible to perform the connection for the P type well region with other than such a metal as aluminum or a polycrystalline silicon containing the P type impurity, because of the required function of suppression of the latchup phenomenon.

In contrast thereto, according to embodiments of the invention, the above conventional concept is cleared away, and, under the notice that the latch-up pheomenon is comparatively hardly caused in the memory cell matrix, the polycrystalline silicon used for the V55 power wiring doped with N type impurity is directly connected to the above mentioned P type well region in the junction state, whereby the latch-up phenomenon can be endured, and further the wiring limit caused by aluminum is removed, as well as the area occupied by the memory element can be reduced. As a result, the high density thereof can be attained.

With reference to Figs. 3 and 4, an embodiment of the present invention will be described.

A P-type well region 220 for forming Nchannel transistors is formed within an N-type semiconductor substrate 221. As is similar in Fig. 2, transfer gate transistors Q, and Q2 of Fig. 1 are formed by the N-type polycrystalline silicon 207 as the word line, N type regions 216 and 217 as the nodes N, and N2 of Fig. 1, and N type regions 218 and 219.

To the regions 218 and 219 true and complement digit lines 209 and 210 formed of aluminum are connected through contact holes. The Vcc wirings 222 are formed by Ptype region extended to drains of the transistors Q5 and Qe of Fig. 1.

In this figure, the V55 wirings 211 are formed of a polycrystalline silicon which is formed on the layer above the silicon layer forming the word lines 207 and 208 and doped with N-type impurity. The digit line 211 is connected to an N type regions 213 and 214 coupled to the sources of the transistors Q3 and (14 through contact holes 215, this connection is performed by a ohmic contact between the same conductivity (N) type silicon layer 211 and region 214. In other words, the conductivity type of the silicon 211 is determined so as to provide a current between the regions 213 and 214 and the V55 wiring 211. The polycrystalline silicon wiring 211 is also directly connected to a contact region 212 formed in the P type well region 220 through a contact hole.The polycrystalline silicon wiring 211 is admitted to be superposed on a part of the digit line wirings 210 and 209 formed of aluminum.

Thus, continuous and simple wirings are provided from the starting point to the ending point of the memory cell matrix, and further an aluminum wiring for the ohmic contact with the P type diffusion layer can be avoided. The polycrystalline silicon wirings 211 so that the wiring limit caused by the aluminum V55 wiring can be removed, whereby the pattern area occupied by each memory cells can be reduced. Under this circumstance, it can be regarded equivalently that a diode 213 is inserted between the P type well 220 and the V55 power wiring 211 with a forward-direction from the P type well towards the V55 power wiring 211.

In other words, in view of supplying the V55 power to the well region 220, the diodes 213 operate in a reverse-direction to block the current to the well region 220 and hence biasing of the well region 220 is not performed due to the prima-facie concept. However, condition of PN junction of the diodes 213 is not in essentially ideal in view of PN function but is rather leaky like resistors. This seems to be caused by the junction between the highly doped N type polycrystalline silicon (211) and the highly doped P+ region 212.

Therefore, the P-type well region 220 can be sufficiently biased by the diode 213.

Furthermore, in the case that these diode are employed only for the memory cell matrix where the latch-up phenomenon is comparatively hardly caused, even if these diodes have insufficient current performance, many of similar diodes are connected in parallel in the memory cell matrix, any difficulty is scarcely caused in a state of practical use.

As is apparent from the above, according to an embodiment of the present invention, the high density integration of the CMOS memory circuit arrangement, particularly, inside the memory cell matrix thereof can be attained.

Next, with reference to Figs. 5 and 6, a description will be given of a detailed layout example and effect of an embodiment in comparison with the conventional layout.

In the following explanation, the same layout rule is applied to the layouts of Figs. 5 and 6, where each contact holes formed with a rectangular share of 2.4 um X 2.8 #m and aluminum wirings have their width of 3.7 ism A polycrystalline silicon wirings as the word lines and interconnection in the flipflop circuits are of 3.3 jim width. In Figs. 5 and 6, the same reference numerals and codes are utilized to indicate portions as those of Figs. 1 to 4 for better understanding.

Throughout Figs. 5A to 5C which show the conventional technique corresponding to Fig.

2, marks '' +" are used to indicate reference points for layout aligning.

The P well region 120 and the respective P and N type impurity-doped regions are shown in Fig. 5A, with respect to neighboring two memory cells. Areas denoted by Q, to Q6 are channel regions corresponding to the transistors Q, to Q6 of Fig. 1. Fig. 5B shows a layout pattern of the first level polycrystalline silicon with which the word lines 107 and 108 and interconnections 131 and 132 for forming the flip-flop circuit are formed. Fig. 5C shows a layout of aluminum wirings 109 and 110 as the digit lines D and D and the V55 lines 111.

Wirings 141 and 142 are to connect the polycrystalline silicon wiring 131 and 132 to the P type and N type regions with ohmic contacts.

As shown in Fig. 5C, in the conventional layout of the memory cell matrix corresponding to Fig. 2, each of the memory cells is arranged in a rectangular region having a length of 37 um and a width of 41.4,um. In this layout, wirings 151 and 152 forming circuit connections as well as gates of the transistors Q3 to Q6 are made of the same level of polycrystalline silicon of N-type as the word lines 107 and 108.

With reference to Figs. 6A to 6D, the detailed layout patterns of the respective layers in an embodiment of the invention will be described.

The layout of the P well region 220 and the respective impurity regions are shown in Fig.

6A.

The regions denoted by the reference codes Q, to Q6 are the channel regions conesponding the transistors Q, to Q6 of Fig. 1. The P type region 222 is used to feed the Vss power supply to the memory cells.

Fig. 6B shows a layout of the first level of the poycryst alline silicon forming the word lines 207 and 208, and the interconnection wirings 231 and 232 forming the flip-flop circuit of the memory cell.

Fig. 6C shows a layout of the aluminum wirings. The wirings 209 and 210 form the word lines D and D. The wirings 241 and 242 are contact connection between the wirings 231, 232 and the impurity regions.

Fig. 6D shows the second level of porycrys talline silicon introduced in the present embodiment. In this example, for reducing a resistance, the polycrystalline silicon 211 is formed in a mesh-like manner along the peripheral edge of the respective memory cells.

Through the contact 215. the polycrystalline silicon 211 is connected to the N type region 214 while through the contact 216, the polycrystalline silicon 211 is also directly connected to the PP contact region in the D well region 220.

As shown throughout Figs. 6A to SD, especially in Fig. 6D in the layout according to the embodiment of the present invention, each of the memory cells is formed on a relatively small region having a length of 37 ym and a width of 32.5 ym. In this layout, the wirings 251 and 252 for connecting the transistors Q3 to Qa are formed of the same level of polycrystalline silicon as those for the word lines 207 and 208. As described above, according to the present invention, about 22% of reduction in size can be achieved in the memory cell matrix without loosing the latchup phenomena suppression function.

Although the above embodiment is described regarding the situation where the V55 power wiring formed of the polycrystalline silicon with the N type impurity, the N type substrate and the P type well regions are employed, the matter can be similarly effected by connecting the P-type polycrystalline silicon with the N type diffusion layer forming a part of the N type well even in the situation where the V55 power wiring formed of the polycrystalline silicon doped with the P type impurity, the P type substrate and the N type well regions are employed on the contrary.

Claims (6)

1. An integrated circuit device comprising a semiconductor region of one conductivity type, at least one insulated gate field effect transistor formed in said semiconductor region and having source and drain regions of the opposite conductivity type, and a wiring layer made of polycrystalline silicon doped with impurities of said opposite conductivity type and having a first portion connected to one of said source and drain regions of said transistor with an ohmic contact and a second portion connected to said semiconductor region with a leaky P-N junction formed between said wiring layer and said semiconductor region.

2. The device as claimed in claim 1, further comprising a semiconductor substrate of said opposite conductivity type, said semiconductor region being formed in said semiconductor substrate.

3. The device as claimed in claim 1, further comprising another polycrystalline silicon layer including a silicon gate of said transistor, and a metal wiring layer.

4. The device as claimed in claim 2, further comprising at least one first channel type insulated gate field effect transistors formed in said semiconductor region, a plurality of second channel type insulated gate field effect transistors formed in said semiconductor substrate, and another polycrystalline silicon layer including silicon gates of said first and second channel type transistors.

5. The device as claimed in claim 2, further comprising at least one additional insu lated gate field effect transistor formed in said semiconductor region, and a first additional wiring layer made of polycrystalline silicon and including silicon gates of said transistor and said additional transistor formed in said semiconductor region.

6. An integrated circuit device as claimed in claim 1, the device being constructed, arranged and adapted to operate substantially as hereinbefore described with reference to the accompanying drawings.