GB2140600A - Computing device for fast fourier transform - Google Patents

Abstract

A computing device for fast Fourier transform capable of shortening operation time so much that the operation time may be regarded as real time. Input data A, B are classified into first two types which do not require multiplication by a phase rotation factor W<s> and second two types which require the multiplication. Paying attention to the periodical appearance of a phase rotation factor, the system sequentially predicts phase rotation factors to thereby effectively perform butterfly operations, A+BW<s>. <IMAGE>

Description

SPECIFICATION Computing device for fast Fourier transform The present invention relates to a computing deviceforfast Fourier transform and, more particu Iarly,to a fast Fouriertransform computing device which achieves the purposewith a lowerfrequency of multiplication than prior art fast Fourier transform computing devices and, thereby shortens the operationtime to such a degree that even visually it appears as real time.

As well known in the art, the frequency spectrum of an analog signalwaveform is produced by subjecting the analog signal waveform to Fourier transform and, therefore, frequency analysis and the like of an analog signal are attainable by effecting such Fourier transform and inverse Fouriertransform using an electronic computer. It is also knownthat a signal can be filtered by multiplying a Fouriertransform output by the transferfunction of a filter and, then, performing inverse Fourier transform on the product. Traditionally,the Fourier transform and other associated operations were quite time-consuming even with use of an electronic computer.Since Cooley and Tukey have presented in i965thefastFouriertransform (FFT) which has been an eminent improvement on the time problem inherent in the Fouriertransform, the FFThas been extensively used in variousfields such as for frequency analysis, recognition and synthesis of speech signals, digital filtering, picture data processing, medical tomography and optical measurements.

FFT has been dealt with in numerous documants such as E. O. Brigham "Fast FourierTransform", Prentice-Hall, 1974,and details thereofwill not be described herein. Briefly, FFT is elaborated to avoid tremendous repetition of the same multiplication in the following equations which define discrete Fourier transform (DFT) and inverse discrete Fouriertransform (IDFT):

wherew=exp{(-j2n)/N} (3) N is a number of data.

That is, FFT is an algorithm for effecting DFT of a long series by dividing it into short blocks so as to reduce the frequency of multiplication and, thereby, the operation time. In the equations (1) and (2),xp is is a sampling value sequence ofthetime function, Xk is a sampling value sequence ofthefrequency spectrum, and p and kare integers within the range of "0" to "N-1". Substituting sforpkin the equations (1) to (3), W# expressed as: Wpk = = cos { ( 2 Toe 5 ) / N } ; -jsin((2ns)/N) (4) In the equation (4), WSis a variable generally referred to as a phase rotation factor.

To work the equation (1 ) directly, since W is a complex number, and p and kvarywithin the range of "O" to "N-1", N2 times of multiplication of complex numbers and N(N-1 times of addition of complex numbers are required. Concerning FFT, on the other hand, it requires a number of times of multiplication represented by a product of N/2, which is half the number of data N of an input data array and log 2 N, which is a number of stages (number of computation arrays), and a frequency of addition of complex numbers which is double the frequency of multiplication. Thus, assuming thatthe operation time is proportional to the frequency of multiplication, the FFT is far shorter in required operation time than the direct computation.

As discussed above, the FFT is truly effective to realize a remarkable cut-down in operation time.

Nevertheless, difficulty has been experienced in shortening the operation time with the FFTto such an extentthat, to the humaneyesight, data actually produced by FFTappearson real time basis as an image on a display.

It is therefore an object of the present inventionto provide a computing device for FFTwhich reduces the required frequency of multiplication than the prior art FFT computing devices and, thereby, renders the operation time short enough to be visually recognized as real time.

It is another object of the present invention to provide a generally improved computing device for FFT.

In one aspect ofthe present invention, there is provided a computing device for fast Fourier transform which generates a fast Fouriertransformed data array by sequentially performing on input data a butterfly computation by use of a phase rotation factor. The computing device comprises a first adderisubtractor and second adderisubtractor each being supplied with, among first and second input data,a real number portion of at leastthefirst input data, a third adder/subtractor and a fourth adder/ subtractor each being supplied with at least an imaginary number portion ofthefirst input data, a firstmultiplierandasecondmultipliereach being suppliedwith a real number portion ofthe second input data, a third multiplier and a fourth multiplier each being supplied with an imaginery number portion of the second input data, and a switching circuit for delivering to the first to fourth adder/ subtractora real number portion and an imaginary number portion of the second input data without causing the first to fourth multipliers to multiplythe real number portion and the imaginary number portion by the phase rotation factorwhen the value of the phase rotation factor is 1 and-j, and delivering to the first to fourth adder/subtractors a result of multiplication of a real number portion and an imaginary number portion of the second input data bythe phase rotation factor caused by the first to fourth multipliers when the value of the phase rotation factor has values otherthan 1 and j.

In another aspect ofthe present invention, there is provided a computing device for fast Fourier trans- form which generates a fast Fouriertransformed data array by sequentially performing on input data a butterfly computation by use of a phase rotation factor. The computing devicecomprisesafirst switching circuit for switchingly delivering the input data in response to a value of the phase rotation factor, afirst computation circuit and a second computation circuftsupplied by the first switching means with input data to be subjected to butterfly computation with the phase rotation factor when the value ofthe phase rotation factor is 1 and-j, athird computation circuit switchingly supplied by the first switching circuit with input data to be subjected to butterfly computation with a phase rotation factor having a real number portion and an imaginary numberportion which are common in absolute value, a fourth computation circuit supplied by the first switching circuit with input data to be subjected to butterfly computation with a phase rotation factor having other values, a coefficient store for applying to the fourth computationcircuit in a predetermined sequence multiplication coefficients which are stored in the store, and a second switching circuit for switchingly delivering data output from the first to fourth computation circuits in a predeterminedsequ- ence and by dividing the data into real number portions and imaginary number portions.

The above and other objects, features and advantages of the present invention will become apparent from the following detailed descriptiontaken with the accompanying drawings.

Fig. 1 is a diagram representative of an exemplary signal flow in FFT: Fig. 2 is a diagram illustrative of butterfly computation; Figs. 3 and 5 individually show relationships between variables, numbers of stages and integer portions; Fig. 4 shows a relationship between thevalue of an integer portion and an angle in a phase rotation factor; Fig. 6 is a block diagram of an FFTcomputing device embodying the present invention; Fig. 7 is a graph representative of afrequency of multiplication particulartoa prior art FFT device and one in accordance with the present invention; Fig. 8 is a block diagram of another embodiment of the present invention; Figs. 9A-9D are diagrams representative respectively of various essential portions ofthe device shown in Fig. 8;; Figs. 1 0A and 10B are diagrams showing respectively alternatives to the constructions of Figs. 9B and 9A; and Fig. 11 is a graph showing a frequency of multiplication assigned to a prior art FFT device and one in accordance with the present invention in a contrastive manner with respect to a sampling number.

While the computing device for fast Fourier transform ofthe present invention is susceptible of numerous physical embodiments, depending upon the environment and requirements of use, substan tial numbers ofthe herein shown and described embodiments have been made, tested and used, and all have performed in an eminently satisfactory manner.

The present invention contemplates to perform butterfly operations or computations efficiently by classifying input data into firsttwo types (type land type 11) which do not require multiplication by phase rotation factors WS, variables on a signal fow diagram in FFT, and secondtwotypes (typelll and type IV) which require it, and by paying attention to the periodical appearanceofsuchtypes.

Using such a signal flow diagram as one shown in Fig. 1, the calculation necessaryforthe FFTalgorithm can be simply expressed. Fig. 1 is a signal flow diagram in which the numberofdata N inthe sampledvaluesequencexpofthetimefunction in the equation (1) is assumed to be "8". Adataarray made up of dataxO-x7 is represented by the leftmost, or first, node array in Fig. 1;the second, third andfourth node arrayswiltbereferredto herein asstages 1,2 and 3 although they are usually called computation arrays.

In a signa#ffowdiagram, two lines merge into each node in a calculation array (stage) to represent transmission paths from preceding nodes. One ofthe transmission pathstransmitsto a node in a certain array a numerical value outputfrom a node in the immediately preceding array after multiplying it by a phase rotation factorWs. That is, as shown in Fig. 2 representative of four adjacent nodes of Fig. 1. a pair of data A and B inputtotwo nodes are transmitted to the following nodes as data C and D and, in this case, the data C is produced by calculation A + BWS, and the data D by calculation A- BWS.

The output data are expressed respectively by: C=A+BWS (5) D = (6) These fundamental operations are referred to as butterfly operations or computations, as well known in the art. The Butterfly operations proceed in the order of stage 1, stage 2 and stage 3.

The frequency of butterfly operations is the product of N/2 indicativeofone halfthe numberof input data and log 2 N indicativeofthe number of stages (number of computation arrays); it is "12" in the exampleshown in Fig. 1 becauseNis"8".ltwillbe seen from Fig. 1 that in any ofthe stages there aretwo nodes which transmission paths from the same one pair of nodes in the preceding stage enter (such two nodes are referred to as a dual node pair). The distance between two nodes in a dual node pair in a stage! is N/21 It is generally accepted that a real number portion and an imaginary number portion of the phase rotation factor at one node and those,atthe other node in a dual pair arecommon in absolute values, respectively, and differently only in sign and, therefore, a single multpilication oftwo complex numbers suffices for obtaining values of the dual node pair.

Regarding a certain node, the values in the phase rotation factorWsto be multipliedto data at a node one array before is produced bythefollowing procedure. Referring the suffixes "0" to "7" of the data Xo-X7 to as "variables", the corresponding nodes in each array are expressed in terms of the variables and these variables are respectively expressed by binary numbers ofthe minimum number of bits y which can indicate the maximum value ofthe variables. The binary number is shifted to the right by a value produced by subtracting a stage number I from y,then "O"s are added to the left-hand side (y-1) bits, and then the bit sequence ofthe binary number is inverted.In this manner, to obtain the value s, it is necessarytoshiftthey-bitbinary number indicative of a variable (y-l) bits to the right. To practice it in a computing process, as well known in the art, the bit ,sequence inversion has to be performed on an integer portion (represented by P hereinafter) which results from division of the variable (represented by n hereinafter) by (2Y-1). Consequently, in the example shown in Fig. 1,thevaluesisoneof"0", "2","1" and "3".

The relationship between the variables n, stages and integer portions P described above may be presented as shown in Fig. 3, taking the case of Fig. 1 for example. In Fig. 3, the mark "X" indicates, oftwo nodes contituting a dual node pair, the node which does not require multiplication. Meanwhile, the value represented by a stage number Panda variable n indicates a value of the integer portion P. For example, where the stage number is "1 " and the variable is one of"0" to "3", the integer portion P is "0" because is 1, y is 3, and n is one of 0-3; where the stage number is "2" and the variable n is "4"or"5", the integer portion P is "2" because I is "2", y is "3", andnis"4"or"5".

Fig. 4 shows a relationship between thevalues of the integer portion P and angles 6 in the phase rotation factorWs(where 6 is 2nsIN in the equation (4)). In the case of Fig. 1 the integer portion P is any one of "0", "2", "4" and "6", as also understood from Fig. 3. When P is"0",6 is zero degree; when "2", 62 (=90 degrees); when "4", 64 (=45 degrees); and when "6", 06 (=135 degrees).

Where the number of data in an input data array is 256 (=28) byway of example, employing the same principle as in Fig. 3,the relationship between the number of variables, 256, the number of stages, 8 (=log 2256), and the values of the integer portion P may be represented by the diagram shown in Fig. 5. In Fig. 5,the integer P may be any even number not smallerthan 8 and not largerthan 254 in addition to the above-mentioned "0", "2", "4" and "6". Where the integer portion P is "8", "10", "12" or "14", the angle 6 is represented by an angle defined by a line 0 and a line 8,10,l2 or l4 shown in Fig.4.

Now, assuming thatthe inputdata Aand B shown in Fig. 2 are expressed respectively as:

A = Ar + jAi ..................................................(7) ........................................ (7) B = Br + iBi then, from the equations (4) - (7), C = A + BWS = = (Ar + Br- cos6 + Bi sin6) + j (Ai + Bi cos6 - Br sin6) =Ar+Tr+j(Ai+Ti) (8) D = A- BWS = Ar-Tr + j (Ai-Ti) (9) The equation (8) teaches that two times of multiplication are necessary for producing Tr, and two times of multiplication for obtaining Ti. Consequently, four times of com putation are required in order two obtain C (this is true also for D).It will be noted that concerning Tr and Ti, they may be stored in a memory when C is produced, in orderto eliminate the need for computing them again in the event of producing D.

As seen from Fig. 4, when the integer portion P is "0", the angle 6 is zero degree and cos 6 = 1 and sin 6 = O so that ws is obtained from the equation (4) as "1". Therefore, from the equations (8) and (9), there holdC=A+BandD=A-BimplyingthatCandD can be generated by simple butterfly operations which are not more than addition and subtraction.

Moreover, concerning the butterfly operations at the stage 1, all the input data are real numbers and not imaginary ones so that, when the integersection P is "O", an equation Ai = Bi = 0 holds in the equation (7) and, therefore, C isAr + Br and D is Ar- Br; computation of real number portions only results output data in real numbers only. Therefore, when the integer portion P is "0", both the input data and the phase rotationfactorto be subjected to butterfly operation consist of real numbers only even atthe stage 2 and onward, thereby eliminating the need for computation with imaginary numbers.Where the integer portion P is "2", the angle 6 is 90 degrees and, therefore, Wsis j. In this case, too, C and D can be generated solely by addition and subtraction despite the presence of a real numberand an imaginary number in the output data.

Wherethe integer portion P is "4" or larger, butterfly operations with four timers of multiplication is performed according to the equations (8) and (9).

In accordance with a first embodiment of the present invention, particular attension is paid to the fact that multiplication of W is needless for the type I in which the integer portion P is "0" and the type 11 in which P is "2", and it has to be performed fourtimes as in the prior art practiceforthe othertypes in which P is "4" or larger and the type IV in which P is "8" or larger. Thus, the types land II are distinguished from the othertypes. Forthetypes land II, a switch is actuated so that only the required addition and subtraction may be performed with data outputfrom the input side of a multiplier while, forthe other types, the required butterfly operations may be performed.

Such a procedure particular to the present invention will attain the butterfly operations with a lower frequency of multiplication than the prior art FFT procedure.

Referring to Fig. 6, a computing device in accordance with the present invention shown in a block diagram. In Fig. 6, inputterminals 10 and 12 are respectively supplied with data Ar representative of a real number portion of a first data A and data Ai representative of an imaginary number portion of the same data A. Input terminals 14 and 16 are supplied respectivelywith data By of representative of a real number portion of a second input data B and data Br representative of an imaginary number portion of the same data B. The data Ar, Ai, Br and Bi are individually read out of a store 18 whose capacity is largerthan one sufficientfor storing the same numer of real number data asthe number of data N and "N" imaginary number data.

The data Ar is applied to an adder/subtractor (strictly, adder) and an adder!subtractor22,whilethe data Ai is applied to an adderlsubtractors 24 and 26.

The data Br is routed to multipliers 28 and 30 to be multiplied by imaginary number data sin 8 and real number data cos 6 of a phase rotation factorWs, which are read out of a coefficient memory 32. The products outputfrom the multipliers 28 and 30 are fed to contacts34a and 36a of switches 34 and 36, respectively. The switch 34 has three contacts 34a34c and the switch 36, three contacts 36a-36c. The contacts 34b and 36b are commonly supplied with the real number data Brwhile the contacts 34c and 36e are connected to ground.

Meanwhile, the imaginary number data Bi is applied to multipliers38 and 40to be multiplied by the imaginary number data sin 8 and real number data cos 6 ofthe phase rotation factorWs. The outputs of the multipliers 38 and 40 are applied to contacts 42a and 44a of switches 42 and 44, respectively. The switch 42, like the switch 34 or 36, has three contacts 42a-42c and the switch 44, contacts 44a-44c. The contacts 42b and 44b are supplied with the data Bi directly via the inputterminal 16, while the contacts 42c and 44c are connected to ground. The switches 34,36,42 and 44 are controlled independently of each other by switching pulses outputfrom a switching pulse generator (not shown).

The adder/subtractor20 sums the real number data from the inputterminal 10 and the data from the switches 36 and 42, generating real number data Cr (= Ar + Br cos 6 + Bi sine) of first output data C. The data Cr is applied to an outputterminal 46. The adder/subtractor24sumsthe imaginary number data Ai from the inputterminal 12 and data from the switch 44 while subtracting data from the switch 34, generating imaginary number data Ci (= Ai + Bi cos 6 -Br sin 0) of the first output data C. The data Ci is applied to an outputterminal 48. The adderisubtractor 22 subtracts the output data of the switches 36 and 42 from the real number data Ar, generating real number data Dr of second output data D.The data Dr is routed to an outputterminal 50. Further, the adder/subtractor 26 sums the imaginary number data Ai and the output data ofthe switch 34whilesubtracting the output data of the switch 44, generating imaginary number data Di(= Ai - Bi cos 6 + Br sin 6). The data Di is applied to an outputterminal 52.

The computing device having the above construction will be operated as follows.

Assume, for example, that the store 18 has stored in its firstto eighth addresses the real number data associated with the eight dataxO-x7 (in the case of N = 8). Where N = 8, atthe stage 1, onlythe butterfly operations with an integer portion P of "0" are effected sequentially for data with the variables 0 and 4,for data with the variables 1 and 5, for data with the variables 2 and 6, and for data with the variables 3 and 7. Then, the switches 36 and 44 are connected respectively to the contacts 36b and 44b, while the switches 34 and 42 are connected respectively to the contacts 34c and 42c.As a result, the switch 36 deliversthereal numberdataBrappliedtotheinput terminal 14 directlywithout multiplication, and the switch44deliverstheimaginarynumberdata Bi applied to the inputterminal 16 directlywithout multiplication. In the meantime, no output is produced from the switch 34 or 42.

In the above condition, data represented by Ar + Br appears atthe outputterminal 46, data represented byAi + Bi appears atthe outputterminal 48, data represented byAr- Bi appears at the outputterminal 50, and data represented byAi-Bi appears atthe outputterminal 52. In this instance, atthe stage 1, only the real number data are fed from the store 18 to the inputterminals 10 and 14, while no imaginary number data is supplied to the inputterminal 12 or 16.

As a result, onlythe real number data are picked up from the outputterminals 46 and 50 and written into the first and eighth addresses ofthe store 18 as data associated with the variables 0-7.

Next, first butterfly operations atthe stage 2 are performed. As seen from Figs. 1 and 3, a first butterfly operation with an integer portion P of "O" is performed for data with the variables 0 and 2 and for data with the variables 1 and 3, and then a second butterfly operation with an integer P of "2" is effected for data with the variableds 4 and 6 and for data with the variables 5 and 7. In the course of the first butterfly operation in which P is "0", the switches 36 and 44 are connected respectively to the contacts 36c and 44c in the same manner a atthe stage 1, while the switches 34 and 42 are connected respectivelyto the contacts 34cand 42c.During the second butterfly operation with Pwhich is "2", the switches 36 and44are connected respectively to the contacts 36b and 44b, and the switches 34 and 42 are connected respectivelyto the contacts 34b and 42b.

Bythe above procedure, in the first and third addresses ofthe store 18from which data associated with the variables 0 and 2 have been read, real number data Cr and Dr produced bythe butterfly operations ofthe above data and picked up from the outputterminals46 and 50 are written. Also, in the second and fourth addresses ofthe store 18 from which data associated with the variables 1 and 3 have been read, the real number data Cr and Dr produced bythe butterfly operations ofthe above data and picked up from the outputterminals 46 and 50 are written.

In the second butterfly operation period, real number data Cr expressed byAr appears at the output terminal 46 and is written into the address of the store 18 from which data associated with variable 4 or 5 has been read. Real number data Dr expressed by Ar is picked up from the output terminal 50 and written into the address from which data associated with the variable 6 or7 has been read. Simultaneously, imaginary number data Ci expressed by-Bi is produced from the outputterminal 48, and imaginary number data Di expressed byBi is producedfromthe outputterminal 52. These imaginary number data Ci and Di are written respectively into predetermined addresses ofthe store 18 otherthanthefirstto eighth addresses.

The butterfly operations atthe stage 2 described above are followed bythose at the stage 3. As seen from Figs. 1 and 3, butterfly operations atthe stage 3 occur in the order of a first butterfly operation with an integer portion of "O" fordata associated with the variables 0 and 1, a second butterfly operation with an integer portion P of"2" for data associated with the variables 2 and 3, a third butterfly operation with an integer portion P of "4" between data associated with the variables 4 and 5, and a fourth butterfly operation with an integer portion Pof"6" between data associated with the variables with 6 and 7.The switches 34,36,42 and 44 are conditioned in the same manner as atthe stage 1 forthe first butterfly operation period, in the same manner as in the second butterfly operation period at the stage 2 for the second butterfly operation period, and connected respectively to the contacts 34a, 36a, 42a and 44a for the third and fourth butterfly periods.

Bythe above procedure,forthethird and fourth butterfly operation periods, data output from any of the multipliers 28,30,38 and 40 are delivered through the associatedswitches34,36,42 and 44 asthe real number data Brand imaginary number data Bi. In the manner described, real number data Cr, imaginary number data Ci, real number data Cr and imaginary number data Di generated bythe equations (8) and (9) are developed respectively at the outputterminals 46, 48,50and 52 andwritten respectively into predetermined addresses ofthe store 18.

In short, in the illustrative embodiment, for the two types land 11 which do not require multiplication,the switches 34,36,42 and 44 are actuated to directly deliver data arrived at the input terminals 14 and 16 without effecting multiplication; for a type which requires multiplication (butterfly operations with P which is "4" or larger), output data of the multipliers 28,30,38 and 40 are selected. This cuts down the frequency of required multiplication, compared to the prior art FFT computing device.The frequency of appearance ofthetype I in which the integer P is "O" is, as known by analogy in view of Figs. 3 and 5, generally N - 1 times, while thefrequency of appearance ofthetype II in which the integer P is "2" is (N/2)- 1 times. Hence,thefrequencyofmultiplica- tion in accordance with this embodiment is (N/2) log 2 N - [ (N - 1) + {(N/2)-l}] = (N/2) log 2 N-(3N/2) + 2 Thefrequencyofmultiplication attainable with the above embodiment which is expressed bythe above equation is related with the number of input data as represented by a in Fig. 7.It will be seen that the frequency achieved with the embodiment is smaller than that of the prior art computing device by (3N/2)- 2 times.

It will be noted that the operations with the construction shown in Fig. 6 may be performed inside an electronic computer.

The contacts 42b and 44b of the switches 42 and 44 included in the arrangement of Fig. 6 do not constitute any essential part ofthe embodiment.

It will be understood from the foregoing that in accordance with thefirst embodiment ofthe present invention a required FFT operation is attainable with a simple and economical construction and with a frequency of multiplication which is smallerthan the frequency (N/2) log 2 N heretofore required as represented by {(N/2) log 2 N-(3/2)N + 2). since the cut-down in the frequency of multiplication is closely related which with a cut-down in operation time, there can be attained such a short operation time which may visually be recognized as real time, even if the sampling number N is 256. The device, therefore, may find application to real-time display of speech signals in the form of musical notes. The decrease in thefrequency of multiplication is reflected to advantage bya higher accuracy of operation.

Asto an integer portion P which is "4" or "6", the angle 6 is 45 degrees or 135 degrees as shown in Fig.

4, in any case resulting in an equation Isin el = |cos 61 = 2 and,therefore,W9is expressed as or Itfollowsthatwhen WSis 2 #' - (meaning 6 = 45 degrees), the following equations are produced from the equations (4) and (8):: c =Ar + 42 (Br + Bi) + j{Ai + -2(Bi + Bi) + j(Ai + #### ~ Br)} ---- (10) Therefore, to obtain C, two times of multiplication are required, i.e., once for computing 2 (Br + Bi) and onceforcomputing ff2 (the same appliesto D).Although this is alsotrue for the case wherein the angle 6 is 135 degrees, the required frequency of multiplication in such a case is just one halfthefourtimesofmultiplication heretofore required as represented by the equations (8) and (9).

Where the integer portion P is "8" or larger, butterfly operations with fourtimes of multiplication is performed according to the equations (8) and (9).

Reference will be made to Figs. 8-1 1 for describing a second embodiment of the present invention.

As dicussed in relation with the first embodiment, multiplication is needless forthe type I in which the integer portion P is "0" and the type II in which it is "2". Forthetype Ill in which P is "4" or "6", multiplication, although necessary, can be halved in frequency compared to the prior art practice; for the type IV in which P is "8" or larger,fourtimes of multiplication are required as in the prior art practice.

With these in view, the second embodiment of the present invention is constructed such that, disting uishing the types land II from thetypes Ill and IV, specific computing units are assigned to the types I and ll to perform addition and subtraction only and specific operation units are assigned to the types Ill and IV for necessary butterfly operations. Again, such a a construction will reduce the frequency of multiplica- tion heretofore required for butterfly operations for FFT.

Referring to Fig. 8,the computing device con structedwith the above principle is shown. A store 54 has stored real number portions of "N" input data.

The input data are sequentially applied from the store 54to a demultiplexer 60 via input terminals 55 and 57.

The demultiplexer 60 has other two inputterminals 56 and 58. Assuming the case of N = 8, the real numeral portion of data xo read out of the store 54 arrives atthe input terminal 55 of the demultiplexer 60 and real number portion of data x4 arrives at the inputterminal 57. As seen from Fig. 3, sincethe demultiplexer 60 knows that the butterfly operations with an integer portion P of "0" will occur at the stage 1, it supplies the two input data to an operation unit 64 in response to an output of a controller 62.As shown in Fig. 9A,the operation unit 64 comprises an adder 66forsumming the input real number data Ar at the input terminal 55 and the input real number data Brat the inputterminal 57, and a subtractor for subtracting one ofthem from the other. The operation unit 64 produces real number data Cr of output data Cat an outputterminal 70, and real number data Dr of output data D at an outputterminal 72. The operation unit 64 is employed to perform butterfly operations when the j integer portion P is "O".

The two real number data outputfrom the opera tion unit 64 are individuallyfed outto output terminals 76 and 78 by a multiplexer 74 which is controlled by an output of the controller 62. The real number data Cr appearing atthe outputterminal 76 is written into the first address ofthe store 54 in which the real number portion of the data x0 has been stored. On the other hand, the real number Dr appearing at the output terminal 78 is written into the fifth address ofthe store 54in which the real number portion ofthe data x4 has been stored.

Thereafter, real number data of data x1 and real number data of data x5 both stored in the store 54 are read thereoutofto be commonly fed to the operation unit 64 via the input terminals 55 and 57 and demultiplexer 60. The operation unit 64 performs the previously mentioned butterfly operation and deliv ers its outputs to the outputterminals 76 and 78 via the multiplexer 74. Real number data Cr produced at the outputterminal 76 is written into the second address ofthe store 54 in which the real number portion of the data x1 has been stored, while real numberdata Drproduced atthe outputterminal 78 is written into the sixth address in which the real number portion of the data Xs has been stored.Such a procedure is sequentially repeated for data x2 and x6 andfor data xs and x7, thereby completing the butterfly operation atthe stage 1. The results ofthe operations, i.e. data representative of real number portions, are written into the third, fourth, seventh and eighth addresses of the store 54.

Next, real number data stored in thefirst and third addresses of the store 54are read out and applied to the demultiplexer 60 via the inputterminals 55 and 57 shown in Fig. 8. As will be seen from Figs. 1 and 3, it is known in advance that atthe stage 2 a butterfly operation with an integer portion Pod "O" will be performed firstfor both the data associated with the variables 0 and 2 and the data associated with the 5 variables 1 and 3, followed by a butterfly operation with an integer portion P of "2"for both the data associated with the variables 4 and 6 and the data associated with the variables 5 an 7.Therefore, when the above-mentioned real number data have arrived atthe inputterminals 55 and 57, the controller 62 controls the demultiplexer 60 to route the real number data to the operation unit 64. Two real number data Cr and Droutputfrom the operation unit 64 are written respectively into the first and third addresses of the store 54via the multiplexer 74 and outputterminals76 and 78. Likewise, real number data read out of the second and forth addresses ofthe store 54 are subjected to butterfly operationsat the operation unit 64 and, then, written into the second and fourth addresses.

Subsequently, real number data read out ofthe fifth and seventh addresses of the store 54 arefedto an operation unit80viathe inputterminals 55and 57 and demultiplexer 60. As shown in Fig. 9B, the operation unit 80 comprises adders 82 and 84 and subtractors 86 and 88 and constructed to produce at output terminals 90 and 92 real number data Cr and imaginary number data Ci of the first output data C and, at outputterminals 94 and 96, real number data Dr and imaginary number data Di ofthe second output data D. By the operation unit 80, the two input data A and B are subjected to a butterfly operation with an integer P "2".The data Cr, Ci, Dr and Di read out of the operation unit 80 are fed respectivelyto output terminals 76, 78, 98 and 100. The real number data Cr and Dr appearing atthe output terminals 76 and 78 are written respectively into thefifth and seventh addresses of the store 54, while the imaginarynumberdata Ci and Di appearing attheoutput terminals 98 and 100 are written respectively and newly into, for example, the thirteenth and fifteenth addresses ofthe store 54.

In the same manner, real number data read out of the sixth and seventh addresses ofthe store 54 are allowed for butterfly operations atthe operation unit 80. The resulting real number data Cr and Dr are written respectively into the sixth and eighth addresses ofthe store 54, and imaginary number data Ci and Di newly into the fourteenth and sixteenth addresses of the store 54. This completes the butterfly operations at the stage 2. Concerning the operation unit80, the imaginary number data Ai and Bi applied to two of thefour inputterminals are always zero and, therefore, the construction shown in Fig. 9B may be replaced with one shown in Fig. 1 OA. The operation unit shown in Fig. 1 OA includes a sine converter 158 which changes sine data. The construction shown in Fig. 1 OAwill be readily understood and, therefore, need no description.

Next, as seen from Figs. 1 and 3, butterfly operations at the stage 3 are effected inthe orderofa butterfly operation with an integer P "2" performed bythe operation unit 64for data associated with the variables 0 and 1, a butterfly operation with an integer P"2"performedbytheoperationunit80fordata associated with the variables 2 and 3, a butterfly operation with an integer "4" performed by an operation unit 102 for data associated with the variables4and 5, and a butterfly operation with an integer"6" performed by an operation unit 104for data associated with the variables 6 and 7.The resulting real number data Cr and Dr appear respec tivelyatthe outputterminals 76 and 78, while imaginary number data Ci and Di appear respectively atthe outputterminals 98 and 100.

Asshownin Fig. the operation unit 102 comprises adders 106, 108 and 110, subtractors 112, 114 and 116, and multipliers 118 and 120. The multiplier 118 produces data by multiplying the sum ofthe second input data Brand Bi by a coefficient ##, 2' while the multiplier 120 produces data by multiplying by a coefficient7/2 a value produced by subtracting 2 the real number data Brfrom the imaginary number data Bi. Appearing respectively at output terminals 122 and 124 of the operation unit are real num ber dat; Cr and imaginary number data Ci represented bythe equation (10). Meanwhile, appearing respectively at outputterminals 126 and 128 are real number data Dr and imaginary number data Di which are represented bytheequation (11).

As shown in Fig. 9D,theoperation unit 104 comprises adders 130,132,134 and 136, subtractors 138 and 140, and multipliers 142 and 144.The multiplier 142 produces data by multiplying output data (Bi-Br) of the subtractor 138 by a coefficient 92.

2 The multiplier 144 produces data by multiplying output data (Bi + Br) ofthe adder 134 by the coefficient7/22. Appearing respectively at output terminals 146,148,150 and 152 ofthe operation unit 104 are the real number data Cr, imaginary number data Ci, real number data Dr and imaginary number data Ci which are produced by the butterfly operations based on the equations (8) and (9) when the phase rotation factor Ws is- .V2 phase rotationfactorWsis- -2-J 2 In the above-described case, because N is 8, the butterfly operations complete in three successive stages, that is, butterfly operations with "8" or larger integer portion does not occur.However, when N is 16 or largerwhich resultsfour or more successive stages, a butterfly operation with "8" or larger integer portion is required. An operation unit 154 shown in Fig. 8 serves such butterfly operations with "8" and larger integer portions P.As in the prior art device,the operation unit 154 performs butterfly operations represented bythe equations (8) and (9). In that case, a coefficient matching with a phase rotation factor WS will be read out of a predetermined address of a coefficient store 156 in response to an output of the controller62 and fed tothe operation unit 154.

As described herein above, in accordance with the second embodiment of the present invention, the operation unit 64 is assigned for addition and subtraction forthetype I, the operation unit 80 is assigned forthe addition and subtraction for the type II, the operation units 102 and 104 are assigned forthe operation ofthetype Ill, and the operation unit is assigned forthe operation ofthe type IV. This is effective to reduce the required frequency of multiplication compared to the prior art FFTcomputing device. That is, the types land It require no multiplication andthetype Ill requires only one half thefrequencyofmultiplication necessaryforthe prior art FFT computing device.Thus, the frequency of multiplication in this particular embodiment is produced by: (N/2) log 2 N - [ (N - 1) + {(N/2) - 1 } + ((N/4)-1) ] = (N/2) log 2 N - (7N/4) + 3 The frequency of multiplication represented by such an equation is related with the number N of input data as indicated by a in Fig. 1 As shown, it is (7N/4) - 3 times lowerthan the frequency heretofore required.

It will be noted thatthe operation with the construction shown in Fig. may be effected within an electronic computer. As forthe inverse transform in the equation (2), because the imaginary number portion is not always zero, the operation unit 64 employs the construction shown in Fig. lOB. However, its operational algorithm remains unchanged and, therefore, will not be described for simplicity.

Thus, the second embodiment described above, like the first embodiment, achieves a lower frequency of multiplication for FFT andtthereby, a shorter operation time. Wherethe sampling number N is 256, for example, the operation will complete in only 60 ms which is short enough to appear real time to human eyesight.

Various modifications will become possible for those skilled in the art after receiving the teachings of the present disclosure without departing from the scope thereof.

Claims (9)

1. A computing device for fast Fourier transform which generates a fast Fouriertransformed data array bysequentiallyperformingoninputdataa butterfly computation by use of a phase rotation factor, said computing device comprising: first adder/subtractor means and second adder/ subtractor means each being supplied with, among first and second input data, a real number portion of at least said first input data; third adder/subtractor means and fourth adder/ subtractor means each being supplied with at least an imaginary number portion of the first input data; first multiplier means and second multiplier means each being supplied with a real number portion of the second input data; third multiplier means and fourth multiplier means each being supplied with an imaginary number portion ofthe second input data; and switching means for delivering to said first to fourth adder/subtractor means a real number portion and an imaginary number portion of the second inputdata without causing said firstto fourth multiplier means to multiply said real number portion and said imaginary number portion by the phase rotation factorwhen the value of the phase rotation factor is respectively 1 and j, and delivering to the firstto fourth adder!subtractor means a result of multiplication of a real number portion and an imaginary number portion of the second input data by the phase rotation factor caused by the first to fourth multiplier means when the value of the phase rotation factor has values otherthanl andj.

2. Acomputing device as claimed in claim 1, in which the first to fourth adder/su btractor means comprise adders.

3. Acomputing device as claimed in claim 1, further comprising a data storeforstoring data associated with real number portions and imaginary number portions each being at least equal in number to the input data.

4. A computing device as claimed in claim 1, further comprising a coefficient store for storing data associated with real numberportionsand imaginary number portions ofthe phase rotation factor which are supplied to the firstto fourth multiplier means.

5. A computing device for fast Fourier transform which generates a fast Fouriertransformed data array by sequentially performing on input data a butterfly computation by use of a phase rotation factor, said computing device comprising: first switching meansfor switchingly delivering the inputdata in response to avalueofthe phase rotation factor; first computation means and second computation means supplied by said first switching means with input data to be subjected to butterfly computation with the phase rotation factorwhen the value of the phase rotation factor is 1 and j;; third computation means switchinglysupplied by thefirst switching means with input data to be subjected to butterfly computation with a phase rotation factor having a real number portion and an imaginary number portion which are common in absolute value; fourth computation means supplied by the first switching means with input data to be subjected to butterfly computation with a phase rotation factor having other values; coefficient store means for applying to said fourth computation means in a predetermined sequence multiplication coefficients which are stored in said store means; and; second switching meansforswitchinglydelivering data outputfrom the first to fourth computation means in a pedetermined sequence and by dividing said data into real number portions and imaginary number portions.

6. Acomputing device as claimed in claim 5, in which each ofthe first and second switching means comprises a multiplexer.

7. Acomputing device as claimed in claim 5, further comprising a data store having a capacity for storing data associated with real numbers and imaginary numbers each being at least equal in numberto the input data.

8. A device, for generating a Fast FourierTransformed data array which includes means for operating upon input data A, B, to output data in the form A + WSB. whereWs is a complex multiplication factor, the operating meanscomprising: calculation means, for performing multiplication, addition andlorsubtraction operations upon the input data and meansfor controlling the calculation means to perform solely addition andior subtraction operations upon the input data when the multiplication factor is of a form which does not change the absolute magnitude of B.

9. A computing device substantially as herein be fore described with reference to the accompanying drawings.