JPH0228188B2 - KOSOKUFUURIE HENKANNOENZANSOCHI - Google Patents

Description

[Detailed description of the invention]

INDUSTRIAL APPLICATION FIELD The present invention relates to an arithmetic device for fast Fourier transform,
The present invention relates to an arithmetic device that performs fast Fourier transform (FFT) operations at high speed. Prior Art As is well known, the frequency spectrum of an analog signal waveform can be obtained by Fourier transforming the analog signal waveform. It has been known for some time that signal waves can be generated by multiplying the Fourier transform output by the transfer function of a filter and performing inverse Fourier transform. However, even when electronic computers were used, the above-mentioned Fourier transform often required a long calculation time, but in 1965, Cooley and Tukey announced the use of fast Fourier transform. Transformation (FFT: first
Since it was shown that the calculation time can be significantly reduced by using Fourier transform, this
FFT is currently used for frequency analysis and recognition of audio signals, etc.
Synthesis, digital filters, image data processing,
It is well known that it is used in many technical fields such as medical tomography and optical measurement. There is a lot of literature regarding FFT (e.g. EO
BRIGHAM, co-translated by Miyagawa and Imai, "Fast Fourier Transform", Science and Technology Publishing, '74, pp. 166-182)
Since it is well known, its detailed explanation will be omitted, but its principle is based on the discrete Fourier transform (DFT: discrete Fourier transform) and its inverse transform (IDFT: inverse discrete Fourier transform).・DFT: X _k = _N-1 〓 ^p=0 X _p・W ^pk (1) IDFT: X _p = 1/N _N-1 〓 ^k=0 X _k・W ^-pk (2) Here, in the calculation of W=exp{(-j2π)/N} (3) To avoid repeating the same multiplication over and over again, divide the long sequence of DFT into small numbers and calculate how many times. This algorithm reduces the number of multiplications and shortens the calculation time by dividing the calculation into two parts.
In equations (1) and (2), xp is a sample value series of the time function, Xk is a sample value series of the frequency spectrum, and p and k are positive numbers in the range from O to N-1, respectively. Indicates an integer. In addition, in formulas (1) to (3), pk
Letting s be W pk , W ^pk is expressed as W ^pk = W ^s = cos {(2πs)/N} −jsin {(2πs)/N} (4). This W ^s is a variable called a phase rotation factor. When formula (1) is directly calculated, W is a complex number and xp may also be a complex number, so N ² complex number multiplications and N (N-1) complex number additions are required. On the other hand, according to FFT, the subtraction is expressed as the product of N/2, which is half of the number of data N in the input data string, and log ₂ N, which is the number of stages (number of columns in the calculation example). It requires addition of the number of times and a complex number twice that number. Therefore, assuming that the calculation time is proportional to the number of multiplications, FFT can significantly reduce the calculation time compared to the above-mentioned direct calculation method. Problems to be Solved by the Invention However, even though the above-mentioned FFT has significantly shortened the computation time, it is difficult to visually display an image based on the data obtained based on the FFT computation results on a display device. There was a problem in that it was difficult to make the calculation time so fast that it could be considered real time. Therefore, the present invention classifies the phase rotation factors into two types: one that does not require multiplication and one that requires multiplication, and focuses on the periodic appearance of these phase rotation factors to calculate successive phase rotation factors. By predicting and efficiently performing butterfly calculations, the number of multiplications can be reduced compared to conventional FFT calculation devices.
It is an object of the present invention to provide a fast Fourier transform calculation device that can shorten the calculation time to the extent that it can be visually considered to be real time. Means for Solving the Problems The present invention is an arithmetic device that sequentially performs a butterfly operation using a phase rotation factor on input data to obtain a fast Fourier transformed data string. first and second input data to which at least the real part of the first input data is supplied;
and third and fourth adder/subtractors to which at least the imaginary part of the first input data is supplied;
When the value of the phase rotation factor is 1 or -j, the real part and imaginary part of the second input data are output as they are to the first to fourth adders/subtractors, respectively, without being multiplied by the phase rotation factor. However, when the value of the phase rotation factor is a value other than the above, the results of multiplying the phase rotation factor by the real part and imaginary part of the second input data are sent to the first to fourth adders/subtractors. It is composed of a switching means for outputting an output, and one embodiment thereof will be described below with reference to the drawings. Embodiment The present invention classifies the phase rotation factor W ^s , which is a variable on the FFT signal flow diagram, into two types (type, type) that do not require multiplication and a type that requires multiplication. It is designed to efficiently perform butterfly calculations by focusing on the periodic appearance of . First, the principle will be explained. The calculations required for the FFT algorithm can be expressed concisely by a signal flow diagram as shown in Figure 1. Figure 1 is a signal flow diagram when the number N of data in the sample value series xp of the time function of equation (1) is " ₈ ". The 3rd, 3rd, and 4th node sequences are called calculation sequences, but are also referred to as stage 1, stage 2, and stage 3 here. At each node of the calculation sequence (stage) in the signal flow diagram, two solid lines representing a transmission path are entered from the previous node. The transmission path multiplies the numerical value output from the node in the previous column by the phase rotation factor W ^s and transmits the result to the node in the next column. That is, looking at the four adjacent nodes among the nodes shown in FIG. 1, as shown in FIG. In this case, the output data C is A+BW ^s
The output data D is the data resulting from the calculation of A-BW ^s , and it is well known that these basic calculations are called butterfly calculations. The butterfly operation is performed in the order of stage 1 → stage 2 → stage 3. The number of times of the above butterfly operation is equal to N/2, which is half of the input data, and the number of stages (number of calculation columns).
It is the product of log ₂ N, and in the example of FIG. 1, N=8, so it is 12 times. As can be seen from Figure 1, each stage has two nodes into which the transmission paths from the same pair of nodes in the previous stage enter (these two nodes are called a dual node pair), and stage l The spacing between pairs of dual nodes in is N/2 ^l .
In general, the phase rotation factor at one node and the phase rotation factor at its dual node have the same absolute value and only differ in sign, so the multiplication of complex numbers is necessary to calculate the value of the dual node pair. It is known that one time is enough. Also, at one node, the value of s of the phase rotation factor W ^s that is multiplied by the data of the node in the previous column is:
Assuming that the subscripts "0" to "7" of data xo to _x7 are called arguments, the nodes in each column are represented by arguments,
Each argument is represented by a binary number with the minimum number of bits Υ that can represent the maximum value of the argument, this binary number is bit-shifted to the right by the value obtained by subtracting the number of stages l from Υ, and "0" is written to the left Υ-l bits. It can be obtained by supplementing , and then reversing the bit order of the binary number. In this way, in order to find the value of s, it is necessary to shift the Υ-bit binary number representing the argument to the right by Υ-l bits, but in order to perform this in arithmetic processing, the argument (this It is known that bit order reversal must be performed on the integer part (denoted by P) when dividing (2〓 ^-l ). Therefore, in the example of FIG. 1, the value of s is one of "0", "2", "1", and "3". From the above, the relationship among the arguments, the number of stages, and each value of the integer part P can be expressed in a chart as shown in FIG. 3, taking the case of FIG. 1 as an example. Third
In the figure, the mark X indicates the other node that does not require multiplication among the two nodes forming the dual node pair described above. Further, the value represented by the stage number and argument indicates the value of the integer part P. For example, when the stage number is "1" and the argument is "0" to "3", the integer part P is: Since l is 1, Υ is 3, and n is 0 to 3, it is "0". Also, the number of stages is 2,
When the argument is either "4" or "5", the integer part P is "2" because l is 2, Υ is 3, and n is 4 or 5. Also, the value of the above integer part P and the phase rotation factor W ^s
angle θ (where θ is 2πs/N in equation (4))
The relationship is as shown in FIG. In the case of Figure 1, the integer part P is, as can be seen from Figure 3,
It will be either "0", "2", "4", or "6",
When P is "0", θ is 0°, when it is "2", θ ₂ (=90°), when it is "4", θ ₄ (=45°), and "6".
” then θ ₆ (=135°). Also, as an example, the number of data in the input data string is 256.
(=2 ⁸ ), the argument is 256, the number of stages is 8 (=
log ₂ 256) and each value of the integer part P is illustrated in the same manner as shown in FIG. 3, as shown in FIG. 5. In this case, the value of the integer part P takes an even number between "8" and "254" in addition to the above "0", "2", "4", and "6". In addition, the angle θ when the integer part P is "8", "10", "12", and "14" is the solid line indicated by 8, 10, 12, and 14 and the solid line indicated by 0 in FIG. It is expressed as the angle formed by By the way, the input data A, shown in FIG.
If B is respectively expressed as A=A _R +jA _I B=B _R +jB _I (5), then from equations (4) and (5), C=A+BW ^s = (A _R +B _R・cosθ+B _I sinθ+ j( A _I +B _I cosθ−B _R sinθ) = A _R +T _R +j (A _I +T _I ) (6) D=A−BW ^s = A _R −T _R +j (A _I −T _I ) (7) As can be seen from equation (6), two multiplications are required to obtain T _R , and two multiplications are also required to obtain T _I , and in the end, C
To obtain , a total of four multiplications are required (D
(same as well). Note that by storing T _R and T _I in the memory when calculating C, they can be used when calculating D without having to be calculated again. Therefore, as can be seen from Figure 4, the integer part P
When the value of is “0”, θ is 0°, and cosθ=
1, sinθ=0, so W ^s is “1” from equation (4)
Therefore, from equations (6) and (7), C=A+B, D=
A-B, and C and D can be generated by butterfly operations consisting only of addition and subtraction. Moreover,
In the butterfly operation in stage 1, the input data is only the real part and the imaginary part is 0, so when the value of the integer part P is "0", A _I = B _I = 0 in equation (5). , C becomes A _R +B _R , and D becomes A _R −
B _R , and since the calculation is performed only on the real part, the output data will also be only the real part. As a result, if the integer part P is "0", the input data to be subjected to butterfly calculation and the phase rotation factor each consist of only the real part even in stage 2 and after, so the calculation of the imaginary part is not necessary. . Also, when the value of the integer part P is "2", since θ is 90°, W ^s becomes -j, and in this case, the output data has a real part and an imaginary part, but C and D can be generated only by addition and subtraction. Also, when the value of the integer part P is "4" or "6", as can be seen from Figure 4, θ is 45° and 135°, so in either case, Therefore, W ^s is

[Formula] or

[Formula] becomes. Therefore, W _s

When [formula] (when θ=45°), from formulas (4) and (6), becomes. Therefore, to find C,

[Formula] and

A total of two multiplications are required to calculate [Formula] and (the same applies to D). The same holds true for θ=135°. However, it can be seen that in this case, only half the number of multiplications is required compared to the total of four multiplications shown in the conventional equations (6) and (7). Further, when the value of the integer multiple P is "8" or more, a butterfly operation involving a total of four multiplications is performed based on equations (6) and (7). Therefore, in the present invention, there is no need to multiply W ^s in the case of a type in which the integer part P is "0" and in the case of a type in which P is "2", and when P is "4" or "6", Considering that in the case of a certain type and in the case of a type in which P is a value of "8" or more, four times of multiplication are required as in the past, we distinguish between types and In the case of a type that does not have one, the changeover switch performs only the necessary additions and subtractions using the data taken out from the input side of the multiplier, and by performing the necessary butterfly calculations, butterfly processing is performed with fewer multiplications compared to the number of multiplications in conventional FFT. It is characterized by the fact that it performs calculations. FIG. 6 shows a block system diagram of an embodiment of the apparatus of the present invention constructed based on the above principle. In the figure, input terminals 1 and 2 are used to receive real part data A _R and imaginary part data of the first input data A among the two input data A and B to be subjected to the butterfly operation, respectively.
A _I comes in, and the real part data B _R and imaginary part data B _I of the second input data B are input to input terminals 3 and 4.
comes in. These data A _R , A _I , B _R , and
B _I is read from a memory (not shown).
This memory has a storage capacity greater than the storage capacity for storing the same number of real part data as the data number N and N imaginary part data. Above data A _R
are adder/subtractor (strictly speaking, adder) 5 and adder/subtractor 7
and data A _I are supplied to adders/subtractors 6 and 8, respectively.
are supplied respectively. Further, the data B _R is supplied to multipliers 9 and 10, respectively, and the phase rotation factor W ^s read from a coefficient memory (not shown) is supplied to multipliers 9 and 10, respectively.
After being multiplied by the imaginary part data sin θ and the real part data cos θ, the contacts 19a and 17 of the changeover switches S ₃ and S ₁
supplied to a. Changeover switches S ₁ and S ₃ are 3 each
The configuration is such that the switch is connected to any one of the contacts 17a to 17c and 19a to 19c, and the real part data is connected to the contacts 17b and 19b, respectively.
B _R is applied, and contacts 17c and 19c are each grounded. On the other hand, the imaginary part data B _I is supplied to multipliers 11 and 12, respectively, where it is multiplied by the imaginary part data sin θ and the real part data cos θ of the phase rotation factor W ^s .
The voltage is applied to the contacts 18a and 20a of the changeover switches S ₂ and S ₄ . The changeover switches S ₂ and S ₄ have three contacts 18a to 18c, 20a to 20c similarly to S ₁ and S ₃ .
, and is configured to be connected to one of the three contacts. The above data B _I is directly input to the input terminal 4 to the contacts 18b and 20b.
The contacts 18c and 20c are each grounded. The above-mentioned changeover switches _S1 to _S4 are independently controlled by switching pulses from a switching pulse generating circuit (not shown). Adder/subtractor 5 receives real part data from input terminal 1
The real part data of the first output data C is obtained by adding A _R and each data from the changeover switches S ₁ and S ₂ respectively.
C _R (=A _R +B _R cosθ+B _I sinθ) is generated and output to the output terminal 13. Further, the adder/subtractor 6 adds the imaginary part data A _I from the input terminal 2 and the data from the changeover switch _S4, respectively, and subtracts the output data from the changeover switch _S3 to obtain the first output data C.
The imaginary part data C _I (=A _I +B _I cosθ−B _R sinθ) is generated and output to the output terminal 14. Also, the adder/subtractor 7 is operated by a changeover switch from the above real part data A _R.
By subtracting each output data of S ₁ and S ₂ , the real part data D _R of the second output data D (=A _R −B _R cosθ−B _I
sinθ) and outputs it to the output terminal 15. Further, the adder/subtractor 8 adds the imaginary part data A _I and the output data of the changeover switch _S3, respectively, and subtracts the output data of the changeover switch _S4 to obtain the second
Imaginary part data D _I (=A _I −B _I cosθ
+B _R sinθ) and outputs it to the output terminal 16. Next, the operation of the above device will be explained. As an example, eight pieces of data x ₀ ~
Assume that the real part data of x ₇ is stored separately in the first to eighth addresses (in the case of N=8). In the case of N=8, as can be seen from Figures 1 and 3, the butterfly operation in stage 1 uses the data of arguments 0 and 4, the data of arguments 1 and 5, the data of arguments 2 and 6, and the data of argument 3. Between the data of and 7, only the butterfly operation in which the integer part P is "0" is sequentially performed. Therefore, the changeover switch
S ₁ and S ₄ are connected to contacts 17b and 20b, respectively, and changeover switches S ₂ and S ₃ are connected to contacts 18c and 19c, respectively. As a result, the input real part data of input terminal 3 is output from changeover switch _S1 .
B _R is taken out as is without being multiplied,
Further, the input imaginary part data B _I of the input terminal ₄ is taken out as it is from the changeover switch S4 without being multiplied, while the output is not taken out from the changeover switches _S2 and _S4 . Therefore, data represented by A _R +B _R , A _I +B _I , A _R -B _R and A _I -B _I are output to the output terminals 13, 14, 15 and 16. However, in stage 1, only the real part data is read from the memory and supplied to input terminals 1 and 3, whereas the imaginary part data is not supplied to input terminals 2 and 4. The real part data is taken out only from 13 and 15 and written to the first to eighth addresses of the memory as data of arguments 0 to 7, respectively. Next, stage 2 butterfly calculation is performed. As can be seen from Figures 1 and 3, in the butterfly operation of stage 2, the first butterfly operation where the integer part P is "0" is first performed between each data of arguments 0 and 2, 1 and 3. is done, then argument 4
A second butterfly operation in which the integer part P is "2" is performed between the data 6, 5, and 7. During the first butterfly calculation period when P is 0, the switches S ₁ and S ₄ are connected to the contacts 17b and 20b, respectively, as in stage 1, and the switches S ₂ and S ₃ are connected to the contacts 17b and 20b, respectively. 18c and 19c, respectively. Also, the second case where the value of P above is “2”
During the butterfly calculation period, selector switches S ₁ and S ₄
are connected to contacts 17c and 20c, respectively, and changeover switches S ₂ and S ₃ are connected to contacts 18b and 19
b, respectively. As a result, the first and third addresses of the memory from which the data of arguments 0 and 2 were read are loaded from the output terminals 13 and 15 obtained by performing the first butterfly operation on those data. The second and fourth addresses of the memory, where the real part data C _R and D _R are written and the data of arguments 1 and 3 are read, are obtained by performing the first butterfly operation on those data. In addition, real part data C _R and D _R from output terminals 13 and 15 are written. Also, during the second butterfly calculation period, the real part data represented by A _R is output from the output terminal 13.
C _R is taken out and the data of argument 4 or 5 is written to the read address of the memory, and the real part data D _R represented by A _R is taken out from the output terminal 15 and the data of argument 6 or 7 is written. Data is written to the address from which it was read. At the same time, imaginary part data C _I represented by _-BR is taken out from the output terminal 14, and imaginary part data _DI represented by _BR is taken out from the output terminal 16. These imaginary part data C _I and D _I are respectively written to predetermined addresses other than the first to eighth addresses of the memory. When the above stage 2 butterfly calculation is completed, the stage 3 butterfly calculation is performed next. As can be seen from Figures 1 and 3, this stage 3 butterfly operation is the first butterfly operation where the integer part P is 0 between the data of arguments 0 and 1, and the data of arguments 2 and 3. Second butterfly operation with integer part P between ``2'', arguments 4 and 5
The third butterfly operation where the integer part P is "4" between the data of arguments 6 and 7 is performed sequentially in the order of the fourth butterfly operation where the integer part P is "6" between the data of arguments 6 and 7. It will be done. Changeover switches S ₁ to _{S 4} are
During the first butterfly computation period, the connection mode is the same as that of the stage 1, and during the second butterfly computation period, the connection mode is the same as that of the second butterfly computation period of the stage 2. Furthermore, during the third and fourth butterfly calculation periods, the contacts 17a, 18a, and 19a are switched, respectively.
and 20a. As a result, during the third and fourth butterfly calculation periods, both the real part data B _R and the imaginary part data B _I are multiplied by any one of the multipliers 9 to 12, and the data are transferred to the changeover switches S ₁ to S _{4 .} taken from.
In this way, from the output terminals 13, 14, 15, and 16, real part data _CR , imaginary part data C _I , and real part data D generated by the calculation formulas (6) and (7) are output. _R and imaginary part data D _I are taken out and written to predetermined addresses in the memory, respectively. In this way, in this embodiment, in the case of two types that do not require multiplication, the changeover switches S ₁ to S ₄
The input data of input terminals 3 and 4 are selected and output as they are without being multiplied, and in the case of a type that requires multiplication (butterfly operation when P is "4" or more), the output data of multipliers 9 to 12 is Since it is designed to selectively output , the number of multiplications can be reduced compared to conventional FFT. That is, the number of occurrences of a type in which the integer part P is "0" is generally N-1 times, as can be inferred from FIGS.
The number of occurrences of the type where is "2" is (N/2)
-1 times, the number of multiplications according to the present invention is (N/2)log ₂ N-[(N-1) + {(N/2)-1}] = (N/2)log ₂ N-( 3N/2)+2. The number of multiplications according to the present invention expressed by the above formula is as shown in Figure 7 in relation to the number of input data N, which is (3N/2 ) - It can be seen that there are only two fewer times. Incidentally, the calculation having the same configuration as that shown in FIG. 6 can also be performed inside the electronic computer. In addition, the contacts 18 of the changeover switches S ₂ and S ₄ in FIG.
b, 20b are not necessarily required. Effects As described above, according to the present invention, according to the same signal flow chart as the conventional FFT without complicating the signal flow chart, when the value of the phase rotation factor is a value that does not need to be multiplied, the switching means The butterfly operation is performed by simply adding and subtracting the input data on the input side of the multiplier, and when multiplication is necessary, the output data of the multiplier is switched and output.This allows for a simple and inexpensive configuration, and reduces the number of multiplications ( N/2)
The required number of multiplications is smaller than log ₂ N by the formula {(N/2)log ₂ N-(3/2)N+2}.
Since FFT calculations can be performed and the reduction in the number of multiplications is closely related to the reduction in calculation time, for example, even if the number of samples N is 256, it can be visually considered to be real time. The calculation time can be shortened, so it can be used for applications such as displaying musical notes in real time at the same time as the sound signal is being produced.Also, since the number of multiplications is reduced, the calculation accuracy is higher than that of FFT. It has features such as being able to improve

[Brief explanation of drawings]

Figure 1 is a diagram showing an example of a signal flow diagram in FFT, Figure 2 is a diagram explaining butterfly operation, and Figures 3 and 5 are examples of relationships between arguments, number of stages, and each value of the integer part, respectively. FIG. 4 is a diagram showing the relationship between the value of the integer part and the angle in the phase rotation factor, FIG. 6 is a block system diagram showing an embodiment of the device of the present invention, and FIG.
FIG. 4 is a diagram showing a comparison between the number of multiplications in FFT and the number of multiplications in the device of the present invention. 1, 3...real part data terminal, 2, 4...imaginary part data input terminal, 5...addition/subtractor (adder),
6 to 8...addition/subtractor, 9 to 12...multiplier, 1
3, 15...Real part data output terminal, 14, 16
...Imaginary part data output terminal, S ₁ to S ₄ ... Selector switch.

Claims (1)

[Claims] 1 An arithmetic device that sequentially performs butterfly operations using a phase rotation factor on input data to obtain a fast Fourier transformed data string, the first input data being one of the first and second input data. first and second adders/subtractors to which at least the real part is supplied; third and fourth adders/subtractors to which at least the imaginary part of the first input data is supplied; and the value of the phase rotation factor is 1 or −j, the real part and imaginary part of the second input data are output as they are to the first to fourth adders/subtractors without being multiplied by the phase rotation factor, and the value of the phase rotation factor is When the value is other than the above, switching means multiplies the phase rotation factor by the real part and imaginary part of the second input data, respectively, and outputs the results to the first to fourth adder/subtractors. Features a fast Fourier transform calculation device.